ESP32 V1 and V2 - protection bits.
ESP32xx V2: revoke bits, protection bits
- refactor efuse component
- adds some APIs for esp32 chips as well as for esp32xx chips
spi_master: fix an issue where master cannot correctly receive data when using DMA in halfduplex mode.
Closes IDFGH-612
See merge request espressif/esp-idf!11354
Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)
Closes https://jira.espressif.com:8443/browse/IDF-2092
Also:
1. Separate static configuration into init phase to improve
performance
2. Add a init code config layer to avoid duplicated configuration
3. Add a HW_CALIBRATION_V1 caps
The ``adc_digi_config_t`` struct is modified on esp32c3: configuration
of clock divider factors are not provided anymore. The SARADC sampling
frequency is provided instead. In this way, we can handle the frequency
limit better.
Alloc handle memory first then hook, we can benifit:
1. Don't have to do malloc in a critical section
2. Don't have to do esp_intr_free in a critical section
Issue Description:
If master is in HD mode, if it sends data without receiving data,
it will still enable the RX DMA because of old version ESP32 silicon issue.
And because there is no correctly linked RX DMA descriptor,
an inlink_dscr_error intr will be seen, which will influence the following RX transactions.
This issue is only found on ESP32.
- add lock for single read and continuous read APIs
- update onetime read start singal delay for hardware limitation[*]
- move adc_caps to soc_caps.h
- update license dates
[*] There is a hardware limitation. If the APB clock frequency is high, the
step of this reg signal: ``onetime_start`` may not be captured by the
ADC digital controller (when its clock frequency is too slow). A rough
estimate for this step should be at least 3 ADC digital controller
clock cycle.
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.
This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
ESP32 in revision0 and revision1 uses touchpad to provide
current to oscillate xtal 32k. But revision2 and revision3
do not need to do that.
Note: touchpad can not work and toupad/ULP wakeup sources
are not available when toupad provides current to xtal 32k
status is 0 when pcnt_hal_clear_intr_status() is called and so the
interrupt will be triggered immediatly again. Store the original
status and pass this as mask to pcnt_hal_clear_intr_status().
Merges https://github.com/espressif/esp-idf/pull/5929
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).
Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h
This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
heap: ported tlsf allocator into multi heap
heap_host_tests: added tlsf allocator into host test
heap_host_test: update freebytes after using free
heap_tests: tlsf now passing on host tests without poisoning
multi_heap: added support for memalign using tlsf implementation
heap_caps: removed heap_caps_aligned_free
heap/test: fixed broken aligned alloc test build
heap: added poisoning pattern when blocks are being merged
heap/tests: added timing tests for memory allocation
heap: reduced tlsf structure overhead
heap/tlsf: made all short functions inside of tlsf module as inline to improve timings
heap: moved tlsf heap routines outside of flash memory
newlib: linked multiheap memalign with newlib memalign function
heap: moved block member functions to a separate file so multi_heap can use the functions
heap/test: improved the tlsf timing test
heap/test: added memalign on aligned alloc tests
heap: moved tlsf configuration constants to a separated file
heap: added random allocations test with timings
heap: modified the calculation of heap free bytes
heap: make aligned free true deprecated functions and update their documentation
heap: add extra assert after successive mallocs on small allocation host test
heap: remove legacy aligned alloc implementation.
performance: added malloc and free time performance default values
This commit adds the feature where the TWAI ISR will continue to
run even if the cache is disabled. Whilst cache is disabled, any
received messages will go into the RX queue, and any pending TX
messages in the TX queue will be transmitted. This feature should
be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
Setting cs num to -1 means cs pin is not connected. But passing the value -1 to the
spicommon_cs_initialize() will lead to program crash caused by "array index out
of bounds". We expect the driver to execute well but the driver should not be in
charge of users' behaviour, so this commit prevents the crash.
https://github.com/espressif/esp-idf/issues/5784
This commit seperates the hal context into different configuration
structures based on their members' definitions. Through refactoring
spi_master.c, the device related configuration should be passed in and
set each time before a new transaction. The transaction related
configuration now is a local variable in case of the fact that error
occurs without any notice when user forgets to pass new transaction
configuration in (which means the old driver will use the trans_config
that is saved from last transaction).
Besides, via above refactor, this commit fixs a bug which leads to
wrong cs polarity setting.
Closes https://github.com/espressif/esp-idf/pull/5490
Moreover, via above refactor, this commit also fixs a bug about duplex
mode switching when multiple devices are added to the bus.
Closes https://github.com/espressif/esp-idf/issues/4641
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
ESP32 lets the user choose from using Vref, Lookup Table, and Two-Point Calibration. In ESP32S2 only two-point calibration is supported. This commit support these changes in idf.
Closes https://github.com/espressif/esp-idf/issues/5455
This commit simplies the defines made in the _caps.h header. Kconfig
option dependencies were moved into the LL, and the check for a
valid BRP has bee simplified.
Replace periph_module_enable/disable by periph_wifi_bt_common_module_enable which are in IRAM.
AddIRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rstandIRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rstto fit O0 optimization level.
Delete duplicated spinlock and counter.
Previously both tasks had equal priority, possible for write task and another
internal task to be scheduled at the same time - starving read task and
causing data loss.
Related to IDFCI-59
The under the error condition of rx buffer size is <=128 an error log is printed that reads uart rx buffer length error(>128). Propose an update to better describe the error condition as uart rx buffer length error(<=128).
Signed-off-by: Wu Bo Wen <wubowen@espressif.com>
Merges https://github.com/espressif/esp-idf/pull/5523
This commit adds TWAI driver support for the
ESP32-S2. The following features were added:
- Expanded BRP support
- Expanded CLKOUT Divider Support
- Updated example READMEs
On ESP32, due to fifo reset issue, UART2 will work incorrectly if reset the fifo of UART1(TX fifo and RX fifo). The software can workaround the RX fifo reset issue,
while the TX fifo reset issue can not. When UART2 is used and UART1 is used as the log output port, a software reset can reproduce this issue. So we should reset the UART memory
before the software reset to solve this problem.
The tests used to measure the throughput by FreeRTOS
`xTaskGetTickCount()`. The rounding error can be quite big, compared to
total measurement time (1350 ms for 4-bit mode).
This commit use `esp_timer_get_time()` instead to measure typical time,
which is in microseconds. Moreover, to get rid of the time error from
cache miss, `ccomp_timer_*` are used to get the cache compensated time
to measure the throughput used for unit test performance assertion.
The log in the spi_bus_lock_touch may be annoying. This commit suppress
the log level, and make the log visible only when the device altered.
Resolves https://github.com/espressif/esp-idf/issues/5056
The SPI bus lock on SPI1 introduces two side effects:
1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.
2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.
This commit:
1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.
2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.
3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.
introduced in 49a48644e4.
Closes https://github.com/espressif/esp-idf/issues/5046
When CONFIG_LOG_DEFAULT_LEVEL is verbose, the ESP_(EARLY_)LOGx will try
to print with format string and tag out of the DRAM while the cache is
disabled. This commit puts the TAG into DRAM, and uses the
'ESP_DRAM_LOGx` to fix the cache miss bug.
Also fixes a LoadProhibited issue when last_dev is NULL.
check master read write functions with array of registers)
fix master serial processing code and modbus controller to work with register array
modbus_master: add reading and writing of test value array (58 registers) to check failure is gone
remove parameter temporary buffer from modbus controller to allow more than 24 byte writes
driver: fix issue with TOUT feature
driver: fix uart_rx_timeout issue
driver: fix issue with rxfifo_tout_int_raw not triggered when received fifo_len = 120 byte and all bytes read out of fifo as result of rxfifo_full_int_raw
driver: add function uart_internal_set_always_rx_timeout() to always handle tout interrupt
examples: call uart_internal_set_always_rx_timeout() to handle tout interrupt correctly
examples: update examples to use tout feature
driver: reflect changes of uart_set_always_rx_timeout() function, change uart.c
driver: change conditions to trigger workaround for tout feature in uart.c
driver: change uart_set_always_rx_timeout()
freemodbus: fix tabs, remove commented code
driver: remove uart_ll_is_rx_idle()
tout_thr - move calculation and masking into hal layer update driver and uart_ll (add uart_ll_set_rx_tout)
move tout calculation into uart_ll
move calculation of time out in bit time for esp32s2 into low level uart_ll.h file
move uart_hal_get_symb_len() into hal
update set_rx_timeout() to warn user about incorrect value
update HAL, LL 1
fix uart_xx_set_rx_tout() to convert symbol time into bit time
update param description
update tout calculation in LL
update uart_hal_get_max_rx_timeout_thrd() and uart_ll_get_max_rx_timeout_thrd()
* Add test support for ESP32S2
* Add loop back test
* Support chip internal connection, no external wiring required.
* Delete the relevant codes of PDM of ESP32-S2 ll layer.
* fix dac dma mode issue
* Let `[ignore] case` return to freedom
1) Because this test uses its own ISR, we need to release it with `esp_intr_free` instead of `pcnt_isr_service_uninstall`.
2) `pcnt_evt_queue` needs to be created before the interrupt is registered and needs to be released at the end of each case.
* Add test support for ESP32S2
* Support chip internal connection, no external wiring required.
The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:
- Added bit field members to can_message_t as alternative
to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
DISABLED_FOR_TARGETS macros are used
Partly revert "ci: disable unavailable tests for esp32s2beta"
This partly reverts commit 76a3a5fb48.
Partly revert "ci: disable UTs for esp32s2beta without runners"
This partly reverts commit eb158e9a22.
Partly revert "fix unit test and examples for s2beta"
This partly reverts commit 9baa7826be.
Partly revert "efuse: Add support for esp32s2beta"
This partly reverts commit db84ba868c.
This commit removes any function calls within
the CAN driver that result in a call to ESP_LOG
whilst inside a critical section.
These function calls are either moved outside
critical sections (e.g., intr_alloc and gpio
functions), or substituted (e.g., assert()).
Closes https://github.com/espressif/esp-idf/issues/4412
* Modify the function implementation of ESP32-S2 RTC GPIO
On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
* Add ESP32-S2 support of unit test
* Modify the pull-up test of unit test
* Modify the interrupt test of unit test
* Modify input and output mode test of unit test
1. The fault signal 3 for unit 2 is corrected to the right value
2. Now `mcpwm_fault_set_oneshot_mode` will clear the status before, no
need to reset the peripheral.
3. The capture feature relies on the prescaler, but it's only
initialized in the mcpwm_init funciton, which is used to initialize a
PWM channel. This means, the capture may not work correctly if no PWM
channel is enabled.
Now the prescaler is also updated when `mcpwm_capture_enable` is
called.
The test case may run after an RTC_WDT_RESET (if we are on rev. 0
ESP32), or software reset (when running test cases locally).
Also moving the test case next to the other timer group driver tests.
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
This commit fixes multiple bugs caused by incorrect calls to
can_enter_reset_mode() and can_exit_reset_mode. Example test
scripts also updated to match new runners.
1. uart_wait_tx_done works incorrect when sending a byte of data.
2. uart_set_rx_timeout sets an incorrect rx timeout value when ref_tick is enabled
closes https://github.com/espressif/esp-idf/issues/3631
There are lot of prints of `Allocate TX buffer for DMA`
Changed these from `ESP_LOGI` to `ESP_LOGD`
Signed-off-by: Vikram Dattu <vikram.dattu@espressif.com>
Do not include bootloader in flash target when secure boot is enabled.
Emit signing warning on all cases where signed apps are enabled (secure
boot and signed images)
Follow convention of capital letters for SECURE_BOOT_SIGNING_KEY
variable, since it is
relevant to other components, not just bootloader.
Pass signing key and verification key via config, not requiring
bootloader to know parent app dir.
Misc. variables name corrections
Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... .
Cleaned up header files from unnecessary headers (releated to soc/... headers).
Description for i2c_slave_read_buffer had leftover from copying from write fct. data
pointer description described the wrong way (writing into internal buffer)
Closes https://github.com/espressif/esp-idf/pull/3268
introduced in f871cc5ffa
The issue is caused by
1. The hal didn't pass the io_mode to LL.
2. The setup_device function overwrite the trans-specific settings.
This MR removes the common dependency from every IDF components to the SOC component.
Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components.
But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components.
In CMAKE, we have two kinds of header visibilities (set by include path visibility):
(Assume component A --(depends on)--> B, B is the current component)
1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B)
2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only)
and we have two kinds of depending ways:
(Assume component A --(depends on)--> B --(depends on)--> C, B is the current component)
1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B)
2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B)
1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default.
2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it.
3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers
4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link)
This is a breaking change. Previous code may depends on the long include chain.
You may need to include the following headers for some files after this commit:
- soc/soc.h
- soc/soc_memory_layout.h
- driver/gpio.h
- esp_sleep.h
The major broken include chain includes:
1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h.
2. ets_sys.h no longer includes soc/soc.h
3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h
some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h
BREAKING CHANGE
stdatomic.h is available both in newlib and GCC include directories.
Normally (if you invoke the compiler without any flags) GCC include
directories are first on the list, so GCC’s stdatomic.h is used. In
IDF, we used to pass newlib include path as an extra include
directory, so newlib’s stdint.h got included instead.
Newlib 2.2.0 stdatomic implementation is compatible with -std=gnu99
but incompatible with -std=gnu11. And GCC doesn’t support atomic_load
with -std=gnu99 (it’s a C11 feature). So when we used atomic_load
with -std=gnu99, it worked due to newlib’s header.
Since we are no longer going to be including newlib headers into IDF,
GCC stdatomic will be used instead. Hence, add -std=gnu11 for source
files which use atomic features.
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
GCC compiler can generate 8-bit stores when modifying bitfields of
volatile structs (https://github.com/espressif/esp-idf/issues/597).
In the specific case of I2C driver, this resulted in byte_num field
to be written using s8i. However the peripheral requires 32-bit
writes, and ignores 8-bit writes. This change modifies the code to
compose the 32-bit command register value first, and then write the
complete value to the hardware.
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2S if
Power Management Framework is enabled.
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
Acquires PM_APB_FREQ_MAX lock when carrying any transaction on I2C if
Power Management Framework is enabled.
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
Removed as much branching (if statements) from the
gpio_intr_service ISR, as possible and split the while loop into
two. Also forced writing the two status*_w1tc variables only once,
instead of every time after calling the external function hooks.
The measurements below, was done using the following tools:
Toolchain version: crosstool-ng-1.22.0-80-g6c4433a
Compiler version: 5.2.0
Here follows a comparison of the gpio_intr_service ISR's
execution time, using a DS1054 oscilloscope. All the time spent
calling external functions, via the function pointers
gpio_isr_func[gpio_num].fn, were disregarded.
With OPTIMIZATION_FLAGS = -Og, 1.34 uSeconds faster:
3.22 uSec (with this patch)
4.56 uSec (with commit 71c90ac4)
100 - (100 * 4.56 / 3.22) = 42% faster
With OPTIMIZATION_FLAGS = -Os, 1.65 uSeconds faster:
2.89 uSec (with this patch)
4.54 uSec (with commit 71c90ac4)
100 - (100 * 4.54 / 2.89) = 57% faster
Signed-off-by: Konstantin Kondrashov <konstantin@espressif.com>
Merges https://github.com/espressif/esp-idf/pull/2861
This commits adds the functions can_clear_transmit_queue() and
can_clear_receive_queue(). Closes#2906
The following bug are fixed:
- CAN_IO_UNUSED is now explicitly cast to enum type. Closes#2825
- Fix multiple documentation errors. Closes#2898, Closes#2794
- can_reconfigure_alerts() returns incorrect current_alerts. Closes#3028
- Add missing header file. Closes#3065
The requirements of pin capabilites is different for spi master and
slave. The master needs CS, SCLK, MOSI to be output-able, while slave
needs MISO to be output-able.
Previous code is for master only.
This commit allows to place other 3 pins than MISO on input-only pins
for slaves. Refactoring for spi_common is also included.
Resolves https://github.com/espressif/esp-idf/issues/2455
New unit tests added
------------------------
**Local:** Local test uses the GPIO matrix to connect the master and the
slave on the same board. When the master needs the iomux, the master
uses the GPIOs of its own, the slave connect to the pins by GPIO matrix;
When the slave needs the iomux, the slave uses the GPIOs of its own, the
master connects to the pins by GPIO matrix.
- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.
**M & S**: Master & slave tests performs the test with two boards. The
master and slave use iomux or gpio matrix according to the config.
- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.
- Provide a new unit test which performs mode test with significant
frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum
frequency allowed.
Paremeterized Test Framework
-----------------------------
The SPI has a lot of parameters, which works in the same process.
This framework provides a way to easily test different parameter sets.
The framework can work in two different ways:
- local test: which requires only one board to perform the test - master
& slave test: which generates two sub test items which uses the same
config set to cooperate to perform the test.
The user defines a (pair if master/slave) set of init/deinit/loop
functions. Then the test framework will call init once, then call loop
several times with different configurations, then call deinit.
Then a unit test can be appended by add a parameter group, and pass it into
a macro.
1. fix error when fading is too fast
2. fix error when setting duty and update immediately
3. update register header file to be in accord with TRM
closes https://github.com/espressif/esp-idf/issues/2903
1. Add missing get function to RMT API: rmt_get_idle_level().
2. Suppress error message from rmt_wait_tx_done() if wait_time==0 (allows for polling).
3. Remove the blank lines between parameter lists.
Merges https://github.com/espressif/esp-idf/pull/2666
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496
1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
I am stealing this delay coding from @jeremyherbert #2493 pr.
2. Change Bus Reset to handle interrupted READ sequences.
The current code does not handle interrupted READ cycles.
If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.
The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.
So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
3. fix typo
correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it. This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!
The DMA cannot receive data correctly when the buffer address is not
WORD aligned. Currently we only check whether the buffer is in the DRAM
region.
The DMA always write in WORDs, so the length arguments should also be
multiples of 32 bits.
A check is added to see whether the buffer is WORD aligned and has valid
length.
The driver decide whether use MOSI/MISO phases according to the buffer
address together with the SPI_TRANS_USE_*DATA. However someone may assue
that these phases will be skipped when the ``length``/``rxlength`` is
set to 0. In fact it is a feature that ``rxlength`` is allowed to be
set to 0 when tx and rx have the same length, and the driver fill the
``rxlength`` to ``length``.
An error check is added when the rxlength is 0 but there is data to be
sent.
It has been observed that, in case of underflow (data unavailability) in
I2S transmission, previously filled up tx descriptors continue to get
transmitted on line, causing noise in case of audio use case.
This change adds optional `tx_desc_auto_clear` field during I2S driver intialization
than can zero initialize tx descriptor in case of underflow situation in
interrupt handler itself.
Closes: https://github.com/espressif/esp-idf/issues/1789
Introduced in 9c23b8e5 and 4f87a62f. To get higher speed, menuconfig
options are added to put ISR and other functions into the IRAM. The
interrupt flag ESP_INTR_FLAG_IRAM is also mistakenly set when the ISR is
put into the IRAM. However callbacks, which are wrote by the user, are
called in the master and slave ISR. The user may not be aware of that
these callbacks are not disabled during flash operations. Any cache miss
during flash operation will cause panic.
Essentially IRAM functions and intrrupt flag ESP_INTR_FLAG_IRAM are
different, the latter means not disabling the ISR during flash
operations. New bus_config flag intr_flags is offered to help set the
interrupt attribute, including priority level, SHARED, IRAM (not
disabled during flash operations). It introduced a small BREAK to
IDFv3.1 (but the same as IDFv3.0) that the user has to manually set IRAM
flag now (therefore he's aware of the IRAM thing) to void the ISR being
disabled during flash operations.
New unity component can be used for testing other applications.
Upstream version of Unity is included as a submodule.
Utilities specific to ESP-IDF unit tests (partitions, leak checking
setup/teardown functions, etc) are kept only in unit-test-app.
Kconfig options are added to allow disabling certain Unity features.
It is an ESP specific FreeRTOS feature that the ISR is always executed
on the core which calls the interrupt register function. In the SPI
driver, the function is always called in the bus initialization
function.
Hence, the ISR will be executed on the core which initialize the driver.
If the core is starved due to higher priority ISRs, or the interrupt is
disabled on the core (spinlock called, etc.), the ISR will not get
executed and SPI transactions will not be handled.
(MINOR CHANGE)
Resolves https://github.com/espressif/esp-idf/issues/2432.
The MISO signal will be delayed if the GPIO matrix is enabled.
However, delay also comes from the slave.
Previous code only considers the former case, and assume the frequency
limitations is only violated when GPIO matrix is used.
Now we are able to calculate the freq limit when extenal MISO delay is
given (feature introduced in 9c6c6ec34ab0641ace89aeb9b1a133eb6fae1a18).
The frequency limit is lower when the external MISO delay is large, and
the limit is likely to be violated even with IOMUX.
Resolves https://github.com/espressif/esp-idf/issues/2690.
This commit resolves a blocking in esp_aes_block function.
Introduce:
The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing.
Fix some related issue with shared using of AES SHA RSA accelerators.
Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
