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timergroup: move interrupt index into peripheral description file

Browse Source 
1. Added timer_group_periph.c file, describing module global signals
   (e.g. interrupt index)
2. Added more caps in soc_caps.h
This commit is contained in:
morris 2020-10-14 11:46:30 +08:00
parent d7b125a87b
commit e4c8ec6174
16 changed files with 142 additions and 59 deletions
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2
components/driver/test/test_timer.c
View File

@ -803,7 +803,7 @@ TEST_CASE("Timer interrupt register", "[hw_timer][leaks=200]")
}
}
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
/**
* Timer clock source:
* 1. configure clock source as APB clock, and enable timer interrupt

56
components/driver/timer.c
View File

@ -17,10 +17,10 @@
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "freertos/xtensa_api.h"
#include "driver/timer.h"
#include "driver/periph_ctrl.h"
#include "hal/timer_hal.h"
#include "soc/timer_periph.h"
#include "soc/rtc.h"
static const char *TIMER_TAG = "timer_group";
@ -83,7 +83,7 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
uint32_t div;
timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
*time = (double)timer_val * div / rtc_clk_apb_freq_get();
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
if (timer_hal_get_use_xtal(&(p_timer_obj[group_num][timer_num]->hal))) {
*time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
}
@ -266,36 +266,10 @@ esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
TIMER_CHECK(fn != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
int intr_source = 0;
uint32_t status_reg = 0;
uint32_t mask = 0;
switch (group_num) {
case TIMER_GROUP_0:
default:
intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer_num;
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE)) {
intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer_num;
}
#endif
timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_0][timer_num]->hal), &status_reg, &mask);
break;
case TIMER_GROUP_1:
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE)) {
intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer_num;
}
#endif
if ((intr_alloc_flags & ESP_INTR_FLAG_EDGE) == 0) {
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
} else {
intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer_num;
}
timer_hal_get_status_reg_mask_bit(&(p_timer_obj[TIMER_GROUP_1][timer_num]->hal), &status_reg, &mask);
break;
}
return esp_intr_alloc_intrstatus(intr_source, intr_alloc_flags, status_reg, mask, fn, arg, handle);
timer_hal_get_status_reg_mask_bit(&(p_timer_obj[group_num][timer_num]->hal), &status_reg, &mask);
return esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_num].t0_irq_id + timer_num, intr_alloc_flags, status_reg, mask, fn, arg, handle);
}
esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config)
@ -305,11 +279,7 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
TIMER_CHECK(config != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
TIMER_CHECK(config->divider > 1 && config->divider < 65537, DIVIDER_RANGE_ERROR, ESP_ERR_INVALID_ARG);
if (group_num == TIMER_GROUP_0) {
periph_module_enable(PERIPH_TIMG0_MODULE);
} else if (group_num == TIMER_GROUP_1) {
periph_module_enable(PERIPH_TIMG1_MODULE);
}
periph_module_enable(timer_group_periph_signals.groups[group_num].module);
if (p_timer_obj[group_num][timer_num] == NULL) {
p_timer_obj[group_num][timer_num] = (timer_obj_t *) heap_caps_calloc(1, sizeof(timer_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
@ -327,15 +297,12 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), config->divider);
timer_hal_set_counter_increase(&(p_timer_obj[group_num][timer_num]->hal), config->counter_dir);
timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), config->alarm_en);
if (config->intr_type == TIMER_INTR_LEVEL) {
timer_hal_set_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
timer_hal_set_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
if (config->intr_type != TIMER_INTR_LEVEL) {
ESP_LOGW(TIMER_TAG, "only support Level Interrupt, switch to Level Interrupt instead");
}
// currently edge interrupt is not supported
// if (config->intr_type == TIMER_INTR_EDGE) {
// timer_hal_set_edge_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
// }
timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), config->counter_en);
#ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK
#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
timer_hal_set_use_xtal(&(p_timer_obj[group_num][timer_num]->hal), config->clk_src);
#endif
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
@ -450,9 +417,12 @@ uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)
uint32_t intr_status = 0;
if (p_timer_obj[group_num][TIMER_0] != NULL) {
timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_0]->hal), &intr_status);
} else if (p_timer_obj[group_num][TIMER_1] != NULL) {
}
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
else if (p_timer_obj[group_num][TIMER_1] != NULL) {
timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_1]->hal), &intr_status);
}
#endif
return intr_status;
}

4
components/hal/esp32/include/hal/timer_ll.h
View File

@ -302,7 +302,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
*/
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
{
*intr_status = hw->int_st_timers.val;
*intr_status = hw->int_st_timers.val & 0x03;
}
/**
@ -316,7 +316,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
{
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
*intr_raw_status = hw->int_raw.val;
*intr_raw_status = hw->int_raw.val & 0x03;
}
/**

4
components/hal/esp32s2/include/hal/timer_ll.h
View File

@ -298,7 +298,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
*/
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
{
*intr_status = hw->int_st.val;
*intr_status = hw->int_st.val & 0x03;
}
/**
@ -312,7 +312,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
{
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
*intr_raw_status = hw->int_raw.val;
*intr_raw_status = hw->int_raw.val & 0x03;
}
/**

4
components/hal/esp32s3/include/hal/timer_ll.h
View File

@ -297,7 +297,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
*/
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
{
*intr_status = hw->int_st.val;
*intr_status = hw->int_st.val & 0x03;
}
/**
@ -311,7 +311,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
{
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
*intr_raw_status = hw->int_raw.val;
*intr_raw_status = hw->int_raw.val & 0x03;
}
/**

13
components/hal/include/hal/timer_types.h
View File

@ -29,7 +29,9 @@ extern "C" {
*/
typedef enum {
TIMER_GROUP_0 = 0, /*!<Hw timer group 0*/
#if SOC_TIMER_GROUPS > 1
TIMER_GROUP_1 = 1, /*!<Hw timer group 1*/
#endif
TIMER_GROUP_MAX,
} timer_group_t;
@ -38,7 +40,9 @@ typedef enum {
*/
typedef enum {
TIMER_0 = 0, /*!<Select timer0 of GROUPx*/
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
TIMER_1 = 1, /*!<Select timer1 of GROUPx*/
#endif
TIMER_MAX,
} timer_idx_t;
@ -64,9 +68,13 @@ typedef enum {
*/
//this is compatible with the value of esp32.
typedef enum {
TIMER_INTR_T0 = BIT(0), /*!< interrupt of timer 0 */
TIMER_INTR_T1 = BIT(1), /*!< interrupt of timer 1 */
TIMER_INTR_T0 = BIT(0), /*!< interrupt of timer 0 */
#if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
TIMER_INTR_T1 = BIT(1), /*!< interrupt of timer 1 */
TIMER_INTR_WDT = BIT(2), /*!< interrupt of watchdog */
#else
TIMER_INTR_WDT = BIT(1), /*!< interrupt of watchdog */
#endif
TIMER_INTR_NONE = 0
} timer_intr_t;
FLAG_ATTR(timer_intr_t)
@ -85,7 +93,6 @@ typedef enum {
*/
typedef enum {
TIMER_INTR_LEVEL = 0, /*!< Interrupt mode: level mode*/
//TIMER_INTR_EDGE = 1, /*!< Interrupt mode: edge mode, Not supported Now*/
TIMER_INTR_MAX
} timer_intr_mode_t;

1
components/soc/esp32/CMakeLists.txt
View File

@ -14,6 +14,7 @@ set(srcs
"sigmadelta_periph.c"
"soc_memory_layout.c"
"spi_periph.c"
"timer_periph.c"
"touch_sensor_periph.c"
"uart_periph.c")

6
components/soc/esp32/include/soc/soc_caps.h
View File

@ -186,7 +186,11 @@
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 0
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
// No contents here
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (10)

29
components/soc/esp32/timer_periph.c Normal file
View File

@ -0,0 +1,29 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/soc.h"
#include "soc/timer_periph.h"
const timer_group_signal_conn_t timer_group_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_TIMG0_MODULE,
.t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
},
[1] = {
.module = PERIPH_TIMG1_MODULE,
.t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
}
}
};

1
components/soc/esp32s2/CMakeLists.txt
View File

@ -13,6 +13,7 @@ set(srcs
"sigmadelta_periph.c"
"soc_memory_layout.c"
"spi_periph.c"
"timer_periph.c"
"touch_sensor_periph.c"
"uart_periph.c"
"usb_periph.c")

7
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -190,7 +190,12 @@
#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
#define SOC_TIMER_GROUP_SUPPORT_XTAL 1
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */

17
components/soc/esp32s3/include/soc/timer_group_caps.h → components/soc/esp32s2/timer_periph.c
View File

@ -1,4 +1,4 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -12,6 +12,17 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/timer_periph.h"
#define SOC_TIMER_GROUP_SUPPORT_XTAL 1
const timer_group_signal_conn_t timer_group_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_TIMG0_MODULE,
.t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
},
[1] = {
.module = PERIPH_TIMG1_MODULE,
.t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
}
}
};

1
components/soc/esp32s3/CMakeLists.txt
View File

@ -15,6 +15,7 @@ set(srcs
"sigmadelta_periph.c"
"soc_memory_layout.c"
"spi_periph.c"
"timer_periph.c"
"touch_sensor_periph.c"
"uart_periph.c")

7
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -69,7 +69,12 @@
#include "systimer_caps.h"
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
#include "timer_group_caps.h"
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#include "touch_sensor_caps.h"

28
components/soc/esp32s3/timer_periph.c Normal file
View File

@ -0,0 +1,28 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/timer_periph.h"
const timer_group_signal_conn_t timer_group_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_TIMG0_MODULE,
.t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
},
[1] = {
.module = PERIPH_TIMG1_MODULE,
.t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
}
}
};

21
components/soc/include/soc/timer_periph.h
View File

@ -13,5 +13,26 @@
// limitations under the License.
#pragma once
#include <stdint.h>
#include "soc/timer_group_reg.h"
#include "soc/timer_group_struct.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
struct {
const periph_module_t module; // Peripheral module
const int t0_irq_id; // Interrupt ID of the first timer in the group
} groups[SOC_TIMER_GROUPS];
} timer_group_signal_conn_t;
extern const timer_group_signal_conn_t timer_group_periph_signals;
#ifdef __cplusplus
}
#endif