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rmt: support esp32s3

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This commit is contained in:
chenjianqiang 2020-08-13 16:55:56 +08:00 committed by morris
parent 99fae0f0b5
commit 9465af0066
12 changed files with 2305 additions and 2827 deletions
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32
components/driver/rmt.c
View File

@ -24,6 +24,7 @@
#include "freertos/semphr.h"
#include "freertos/ringbuf.h"
#include "soc/soc_memory_layout.h"
#include "soc/rtc.h"
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#include "esp_rom_gpio.h"
@ -490,7 +491,11 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu
esp_rom_gpio_connect_out_signal(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0);
} else {
gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
#if SOC_RMT_TX_RX_CHANNEL_INDEPENDENT
esp_rom_gpio_connect_in_signal(gpio_num, RMT_SIG_IN0_IDX + channel - RMT_LL_TX_CHAN_NUM, 0);
#else
esp_rom_gpio_connect_in_signal(gpio_num, RMT_SIG_IN0_IDX + channel, 0);
#endif
}
return ESP_OK;
}
@ -520,14 +525,21 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
rmt_ll_reset_tx_pointer(dev, channel);
rmt_ll_reset_rx_pointer(dev, channel);
if (rmt_param->flags & RMT_CHANNEL_FLAGS_ALWAYS_ON) {
#ifdef SOC_RMT_SUPPORT_REF_TICK
// clock src: REF_CLK
rmt_source_clk_hz = REF_CLK_FREQ;
rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_REF);
#elif defined SOC_RMT_SUPPORT_XTAL_CLOCK
// clock src: XTAL_CLK
rmt_source_clk_hz = rtc_clk_xtal_freq_get() * 1000000;
rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_XTAL);
#endif
} else {
// clock src: APB_CLK
rmt_source_clk_hz = APB_CLK_FREQ;
rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_APB);
}
esp_rom_printf("rmt_source_clk_hz: %d\n", rmt_source_clk_hz);
rmt_ll_set_mem_blocks(dev, channel, mem_cnt);
rmt_ll_set_mem_owner(dev, channel, RMT_MEM_OWNER_HW);
RMT_EXIT_CRITICAL();
@ -545,7 +557,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
}
#endif
/* always enable tx ping-pong */
rmt_ll_enable_tx_pingpong(dev, true);
rmt_ll_enable_tx_pingpong(dev, channel, true);
/*Set idle level */
rmt_ll_enable_tx_idle(dev, channel, rmt_param->tx_config.idle_output_en);
rmt_ll_set_tx_idle_level(dev, channel, idle_level);
@ -1189,11 +1201,21 @@ esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(clock_hz, "parameter clock_hz can't be null", ESP_ERR_INVALID_ARG);
RMT_ENTER_CRITICAL();
if (rmt_ll_get_counter_clock_src(rmt_contex.hal.regs, channel) == RMT_BASECLK_REF) {
*clock_hz = rmt_hal_get_counter_clock(&rmt_contex.hal, channel, REF_CLK_FREQ);
} else {
*clock_hz = rmt_hal_get_counter_clock(&rmt_contex.hal, channel, APB_CLK_FREQ);
uint32_t rmt_source_clk_hz = 0;
if (rmt_ll_get_counter_clock_src(rmt_contex.hal.regs, channel) == RMT_BASECLK_APB) {
rmt_source_clk_hz = APB_CLK_FREQ;
}
#ifdef SOC_RMT_SUPPORT_REF_TICK
else if (rmt_ll_get_counter_clock_src(rmt_contex.hal.regs, channel) == RMT_BASECLK_REF) {
rmt_source_clk_hz = REF_CLK_FREQ;
}
#endif
#ifdef SOC_RMT_SUPPORT_XTAL_CLOCK
else if (rmt_ll_get_counter_clock_src(rmt_contex.hal.regs, channel) == RMT_BASECLK_XTAL) {
rmt_source_clk_hz = rtc_clk_xtal_freq_get() * 1000000;
}
#endif
*clock_hz = rmt_hal_get_counter_clock(&rmt_contex.hal, channel, rmt_source_clk_hz);
RMT_EXIT_CRITICAL();
return ESP_OK;
}

24
components/driver/test/test_rmt.c
View File

@ -141,9 +141,17 @@ TEST_CASE("RMT miscellaneous functions", "[rmt]")
TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
TEST_ASSERT_EQUAL_UINT8(160, div_cnt);
#if SOC_RMT_SUPPORT_REF_TICK
TEST_ESP_OK(rmt_set_source_clk(channel, RMT_BASECLK_REF));
TEST_ESP_OK(rmt_get_source_clk(channel, &src_clk));
TEST_ASSERT_EQUAL_INT(RMT_BASECLK_REF, src_clk);
#endif
#if SOC_RMT_SUPPORT_XTAL_CLOCK
TEST_ESP_OK(rmt_set_source_clk(channel, RMT_BASECLK_XTAL));
TEST_ESP_OK(rmt_get_source_clk(channel, &src_clk));
TEST_ASSERT_EQUAL_INT(RMT_BASECLK_XTAL, src_clk);
#endif
TEST_ESP_OK(rmt_set_memory_owner(channel, RMT_MEM_OWNER_RX));
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
@ -205,7 +213,11 @@ static void do_nec_tx_rx(uint32_t flags)
uint32_t cmd = 0x20;
bool repeat = false;
int tx_channel = 0;
#ifdef CONFIG_IDF_TARGET_ESP32S3
int rx_channel = 4;
#else
int rx_channel = 1;
#endif
// test on different flags combinations
rmt_setup_testbench(tx_channel, rx_channel, flags);
@ -302,7 +314,11 @@ TEST_CASE("RMT TX stop", "[rmt]")
uint32_t cmd = 0x20;
bool repeat = false;
int tx_channel = 0;
#ifdef CONFIG_IDF_TARGET_ESP32S3
int rx_channel = 4;
#else
int rx_channel = 1;
#endif
rmt_setup_testbench(tx_channel, rx_channel, 0);
@ -361,7 +377,11 @@ TEST_CASE("RMT TX stop", "[rmt]")
TEST_CASE("RMT Ping-Pong operation", "[rmt]")
{
int tx_channel = 0;
#ifdef CONFIG_IDF_TARGET_ESP32S3
int rx_channel = 4;
#else
int rx_channel = 1;
#endif
rmt_item32_t frames[SOC_RMT_CHANNEL_MEM_WORDS * 2]; // send two block data using ping-pong
RingbufHandle_t rb = NULL;
uint32_t size = sizeof(frames) / sizeof(frames[0]);
@ -478,7 +498,11 @@ TEST_CASE("RMT TX loop", "[rmt]")
uint32_t cmd = 0x20;
bool repeat = false;
int tx_channel = 0;
#ifdef CONFIG_IDF_TARGET_ESP32S3
int rx_channel = 4;
#else
int rx_channel = 1;
#endif
uint32_t count = 0;
rmt_setup_testbench(tx_channel, rx_channel, RMT_TESTBENCH_FLAGS_LOOP_ON);

2
components/hal/esp32/include/hal/rmt_ll.h
View File

@ -96,7 +96,7 @@ static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t cha
return div == 0 ? 256 : div;
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->apb_conf.mem_tx_wrap_en = enable;
}

2
components/hal/esp32s2/include/hal/rmt_ll.h
View File

@ -98,7 +98,7 @@ static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t cha
return div == 0 ? 256 : div;
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->apb_conf.mem_tx_wrap_en = enable;
}

207
components/hal/esp32s3/include/hal/rmt_ll.h
View File

@ -25,6 +25,10 @@ extern "C" {
#define RMT_LL_HW_BASE (&RMT)
#define RMT_LL_MEM_BASE (&RMTMEM)
#define RMT_LL_TX_CHAN_NUM (4)
#define RMT_LL_TX_CHAN_MASK (0x0F)
#define RMT_LL_RX_CHAN_MASK (0xF0)
static inline void rmt_ll_set_sclk(rmt_dev_t *dev, uint32_t source, uint32_t div_num, uint32_t div_frac_a, uint32_t div_frac_b)
{
dev->sys_conf.sclk_active = 0;
@ -49,14 +53,18 @@ static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t chann
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 0;
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].apb_mem_rst = 0;
}
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->rx_conf[channel].conf1.apb_mem_rst = 1;
dev->rx_conf[channel].conf1.mem_wr_rst = 1;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_wr_rst = 1;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_wr_rst = 0;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.apb_mem_rst = 1;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.apb_mem_rst = 0;
}
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
@ -67,10 +75,14 @@ static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_conf[channel].tx_stop = 1;
dev->tx_conf[channel].conf_update = 1;
}
static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_en = enable;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.conf_update = 1;
}
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
@ -89,26 +101,35 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev)
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->tx_conf[channel].mem_size = block_num;
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].mem_size = block_num;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.mem_size = block_num;
}
}
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_conf[channel].mem_size) : (dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.mem_size);
}
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
dev->tx_conf[channel].div_cnt = div;
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].div_cnt = div;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.div_cnt = div;
}
}
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
return dev->tx_conf[channel].div_cnt;
return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_conf[channel].div_cnt) : (dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.div_cnt);
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->tx_conf[channel].mem_tx_wrap_en = enable;
}
static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
@ -118,20 +139,24 @@ static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.idle_thres = thres;
}
static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.idle_thres;
}
static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
{
if (channel >= RMT_LL_TX_CHAN_NUM) {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_owner = owner;
}
}
static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_owner;
}
static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
@ -141,7 +166,7 @@ static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool
static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return false;
return dev->tx_conf[channel].tx_conti_mode;
}
static inline void rmt_ll_set_tx_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
@ -162,7 +187,7 @@ static inline void rmt_ll_enable_tx_loop_count(rmt_dev_t *dev, uint32_t channel,
static inline void rmt_ll_enable_tx_sync(rmt_dev_t *dev, bool enable)
{
dev->tx_sim.tx_sim_en = enable;
dev->tx_sim.en = enable;
}
static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
@ -173,24 +198,30 @@ static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
static inline uint32_t rmt_ll_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_sim.val &= ~(1 << channel);
return dev->tx_sim.val & 0x0F;
return dev->tx_sim.val & RMT_LL_TX_CHAN_MASK;
}
static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_filter_en = enable;
}
static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_filter_thres = thres;
}
static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
{
dev->sys_conf.sclk_sel = src;
dev->sys_conf.sclk_div_num = 0;
dev->sys_conf.sclk_div_a = 0;
dev->sys_conf.sclk_div_b = 0;
}
static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->sys_conf.sclk_sel;
}
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@ -215,7 +246,7 @@ static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_status[channel].val) : (dev->rx_status[channel - RMT_LL_TX_CHAN_NUM].val);
}
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
@ -225,113 +256,148 @@ static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_
static inline void rmt_ll_set_rx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->rx_lim[channel - RMT_LL_TX_CHAN_NUM].rx_lim = limit;
}
static inline uint32_t rmt_ll_get_rx_limit(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->rx_lim[channel - RMT_LL_TX_CHAN_NUM].rx_lim;
}
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3));
dev->int_ena.val |= (enable << (channel * 3));
if (enable) {
dev->int_ena.val |= (BIT(0) << (channel));
} else {
dev->int_ena.val &= ~(BIT(0) << (channel));
}
}
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 1));
dev->int_ena.val |= (enable << (channel * 3 + 1));
if (enable) {
dev->int_ena.val |= (BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
} else {
dev->int_ena.val &= ~(BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 2));
dev->int_ena.val |= (enable << (channel * 3 + 2));
if(channel < RMT_LL_TX_CHAN_NUM) {
if (enable) {
dev->int_ena.val |= (BIT(4) << (channel));
} else {
dev->int_ena.val &= ~(BIT(4) << (channel));
}
} else {
if (enable) {
dev->int_ena.val |= (BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
} else {
dev->int_ena.val &= ~(BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
}
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 12));
dev->int_ena.val |= (enable << (channel + 12));
if (enable) {
dev->int_ena.val |= (BIT(8) << (channel));
} else {
dev->int_ena.val &= ~(BIT(8) << (channel));
}
}
static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 16));
dev->int_ena.val |= (enable << (channel + 16));
if (enable) {
dev->int_ena.val |= (BIT(12) << (channel));
} else {
dev->int_ena.val &= ~(BIT(12) << (channel));
}
}
static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 20));
dev->int_ena.val |= (enable << (channel + 20));
if (enable) {
dev->int_ena.val |= (BIT(24) << (channel - RMT_LL_TX_CHAN_NUM));
} else {
dev->int_ena.val &= ~(BIT(24) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3));
dev->int_clr.val = (BIT(0) << (channel));
}
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 1));
dev->int_clr.val = (BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
}
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 2));
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->int_clr.val = (BIT(4) << (channel));
} else {
dev->int_clr.val = (BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 12));
dev->int_clr.val = (BIT(8) << (channel));
}
static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 16));
dev->int_clr.val = (BIT(12) << (channel));
}
static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 20));
dev->int_clr.val = (BIT(24) << (channel -RMT_LL_TX_CHAN_NUM));
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6);
return dev->int_st.val & RMT_LL_TX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7);
return (dev->int_st.val >> 12) & RMT_LL_RX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 4) & RMT_LL_TX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 16) & RMT_LL_RX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);
return ((dev->int_st.val >> 4) & RMT_LL_TX_CHAN_MASK) | ((dev->int_st.val >> 16) & RMT_LL_RX_CHAN_MASK);
}
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF000) >> 12;
}
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF0000) >> 16;
return (dev->int_st.val >> 8) & RMT_LL_TX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF00000) >> 20;
return (dev->int_st.val >> 20) & RMT_LL_RX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 12) & RMT_LL_TX_CHAN_MASK;
}
static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
@ -349,21 +415,39 @@ static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
typeof(dev->rx_carrier[0]) reg;
reg.high_thres = high_ticks;
reg.low_thres = low_ticks;
dev->rx_carrier[channel].val = reg.val;
dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].val = reg.val;
}
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{
if (channel < RMT_LL_TX_CHAN_NUM) {
*high_ticks = dev->tx_carrier[channel].high;
*low_ticks = dev->tx_carrier[channel].low;
} else {
*high_ticks = dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].high_thres;
*low_ticks = dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].low_thres;
}
}
// This function has different meaning for TX and RX
// TX: enable to modulate carrier
// RX: enable to demodulate carrier
static inline void rmt_ll_enable_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->tx_conf[channel].carrier_en = enable;
if (channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].carrier_en = enable;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.carrier_en = enable;
}
}
static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->tx_conf[channel].carrier_out_lv = level;
if (channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].carrier_out_lv = level;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.carrier_out_lv = level;
}
}
// set true, enable carrier in all RMT state (idle, reading, sending)
@ -383,6 +467,23 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const r
static inline void rmt_ll_enable_rx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_rx_wrap_en = enable;
}
static inline void rmt_write_fifo(rmt_dev_t *dev, uint32_t channel, const rmt_item32_t *data, uint32_t length)
{
for (uint32_t i = 0; i < length; i++) {
dev->data_ch[channel] = data[i].val;
}
}
static inline void rmt_ll_config_update(rmt_dev_t *dev, uint32_t channel)
{
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].conf_update = 1;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.conf_update = 1;
}
}
/************************************************************************************************

12
components/hal/include/hal/rmt_types.h
View File

@ -53,8 +53,16 @@ typedef enum {
*
*/
typedef enum {
RMT_BASECLK_REF, /*!< RMT source clock is REF_TICK, 1MHz by default */
RMT_BASECLK_APB, /*!< RMT source clock is APB CLK, 80Mhz by default */
#ifdef SOC_RMT_SUPPORT_REF_TICK
RMT_BASECLK_REF = 0, /*!< RMT source clock is REF_TICK, 1MHz by default */
#endif
RMT_BASECLK_APB = 1, /*!< RMT source clock is APB CLK, 80Mhz by default */
#ifdef SOC_RMT_SUPPORT_RTC8M_CLOCK
RMT_BASECLK_RTC8M = 2, /*!< RMT source clock is RTC 8M clock, 8Mhz by default */
#endif
#ifdef SOC_RMT_SUPPORT_XTAL_CLOCK
RMT_BASECLK_XTAL = 3, /*!< RMT source clock is XTAL clock, 40Mhz by default */
#endif
RMT_BASECLK_MAX,
} rmt_source_clk_t;

5
components/soc/esp32/include/soc/soc_caps.h
View File

@ -159,8 +159,9 @@
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels */
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels */
#define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 18

1
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -149,6 +149,7 @@
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 22

15
components/soc/esp32s3/include/soc/rmt_caps.h
View File

@ -18,12 +18,15 @@
extern "C" {
#endif
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#define SOC_RMT_CHANNEL_MEM_WORDS (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels */
#define SOC_RMT_TX_RX_CHANNEL_INDEPENDENT (1) /*!< TX channels and RX channels are independent, channel0~3 transmit only and channel4~8 receive only */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#define SOC_RMT_SUPPORT_RTC8M_CLOCK (1) /*!< Support set RTC 8M clock as the RMT clock source */
#define SOC_RMT_SUPPORT_XTAL_CLOCK (1) /*!< Support set XTAL clock as the RMT clock source */
#ifdef __cplusplus
}

4810
components/soc/esp32s3/include/soc/rmt_reg.h
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File diff suppressed because it is too large Load Diff

12
components/soc/esp32s3/include/soc/rmt_struct.h
View File

@ -17,6 +17,8 @@
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
uint32_t data_ch[8];
union {
@ -281,11 +283,11 @@ typedef volatile struct {
} sys_conf;
union {
struct {
uint32_t tx_sim_ch0 : 1;
uint32_t tx_sim_ch1 : 1;
uint32_t tx_sim_ch2 : 1;
uint32_t tx_sim_ch3 : 1;
uint32_t tx_sim_en : 1;
uint32_t ch0 : 1;
uint32_t ch1 : 1;
uint32_t ch2 : 1;
uint32_t ch3 : 1;
uint32_t en : 1;
uint32_t reserved5 : 27;
};
uint32_t val;

10
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -53,7 +53,15 @@
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
/*-------------------------- RMT CAPS ----------------------------------------*/
#include "rmt_caps.h"
#define SOC_RMT_CHANNEL_MEM_WORDS (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels */
#define SOC_RMT_TX_RX_CHANNEL_INDEPENDENT (1) /*!< TX channels and RX channels are independent, channel0~3 transmit only and channel4~8 receive only */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#define SOC_RMT_SUPPORT_RTC8M_CLOCK (1) /*!< Support set RTC 8M clock as the RMT clock source */
#define SOC_RMT_SUPPORT_XTAL_CLOCK (1) /*!< Support set XTAL clock as the RMT clock source */
/*-------------------------- RTCIO CAPS --------------------------------------*/
#include "rtc_io_caps.h"