mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-19 14:26:01 -04:00
1.update touch driver; 2.update adc/dac driver; 3.add temp sensor driver;
This commit is contained in:
parent
83e00cf643
commit
b055bff580
@ -20,6 +20,7 @@
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#include "soc/dport_reg.h"
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#include "soc/i2s_periph.h"
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#include "esp_log.h"
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#include "soc/io_mux_reg.h"
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#ifndef BOOTLOADER_BUILD
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#include "esp_system.h"
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@ -81,11 +82,25 @@ void bootloader_random_enable(void)
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*/
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SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
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SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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/* Disable IO1 digital function for random function. */
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PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
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PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U);
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WRITE_PERI_REG(SYSCON_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF);
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SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP);
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#endif
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// Test pattern configuration byte 0xAD:
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//--[7:4] channel_sel: 10-->en_test
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//--[3:2] bit_width : 3-->12bit
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@ -94,10 +109,15 @@ void bootloader_random_enable(void)
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
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#endif
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@ -137,18 +157,25 @@ void bootloader_random_disable(void)
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
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/* Restore SYSCON mode registers */
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#if CONFIG_IDF_TARGET_ESP32
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CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
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CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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/* Restore SAR ADC mode */
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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#if CONFIG_IDF_TARGET_ESP32
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
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| SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
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#endif
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
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#endif
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@ -6,6 +6,8 @@ set(COMPONENT_SRCS "can.c"
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"periph_ctrl.c"
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"rmt.c"
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"rtc_module.c"
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"rtc_tempsensor.c"
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"rtc_touchpad.c"
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"sdspi_crc.c"
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"sdspi_host.c"
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"sdspi_transaction.c"
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@ -52,6 +52,7 @@ typedef enum {
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#define ADC_WIDTH_11Bit ADC_WIDTH_BIT_11
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#define ADC_WIDTH_12Bit ADC_WIDTH_BIT_12
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#if CONFIG_IDF_TARGET_ESP32
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typedef enum {
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ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */
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ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO37 */
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@ -77,6 +78,35 @@ typedef enum {
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ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 */
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ADC2_CHANNEL_MAX,
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} adc2_channel_t;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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typedef enum {
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ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */
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ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO2 */
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ADC1_CHANNEL_2, /*!< ADC1 channel 2 is GPIO3 */
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ADC1_CHANNEL_3, /*!< ADC1 channel 3 is GPIO4 */
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ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO5 */
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ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO6 */
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ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO7 */
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ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO8 */
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ADC1_CHANNEL_8, /*!< ADC1 channel 6 is GPIO9 */
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ADC1_CHANNEL_9, /*!< ADC1 channel 7 is GPIO10 */
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ADC1_CHANNEL_MAX,
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} adc1_channel_t;
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typedef enum {
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ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO11 */
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ADC2_CHANNEL_1, /*!< ADC2 channel 1 is GPIO12 */
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ADC2_CHANNEL_2, /*!< ADC2 channel 2 is GPIO13 */
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ADC2_CHANNEL_3, /*!< ADC2 channel 3 is GPIO14 */
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ADC2_CHANNEL_4, /*!< ADC2 channel 4 is GPIO15 */
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ADC2_CHANNEL_5, /*!< ADC2 channel 5 is GPIO16 */
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ADC2_CHANNEL_6, /*!< ADC2 channel 6 is GPIO17 */
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ADC2_CHANNEL_7, /*!< ADC2 channel 7 is GPIO18 */
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ADC2_CHANNEL_8, /*!< ADC2 channel 8 is GPIO19 */
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ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO20 */
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ADC2_CHANNEL_MAX,
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} adc2_channel_t;
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#endif
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typedef enum {
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ADC_CHANNEL_0 = 0, /*!< ADC channel */
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@ -23,11 +23,19 @@ extern "C" {
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#include "esp_err.h"
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#include "soc/dac_periph.h"
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#if CONFIG_IDF_TARGET_ESP32
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typedef enum {
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DAC_CHANNEL_1 = 1, /*!< DAC channel 1 is GPIO25 */
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DAC_CHANNEL_2, /*!< DAC channel 2 is GPIO26 */
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DAC_CHANNEL_MAX,
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} dac_channel_t;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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typedef enum {
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DAC_CHANNEL_1 = 1, /*!< DAC channel 1 is GPIO17 */
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DAC_CHANNEL_2, /*!< DAC channel 2 is GPIO18 */
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DAC_CHANNEL_MAX,
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} dac_channel_t;
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#endif
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/**
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* @brief Get the gpio number of a specific DAC channel.
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36
components/driver/include/driver/temp_sensor.h
Normal file
36
components/driver/include/driver/temp_sensor.h
Normal file
@ -0,0 +1,36 @@
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#ifndef _TEMP_SENSOR_H_
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#define _TEMP_SENSOR_H_
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#include <stdint.h>
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#include "esp_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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typedef enum {
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TEMP_SENSOR_DAC_L0 = 5, // offset = -2, range: 50℃ ~ 125℃, error < 3℃.
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TEMP_SENSOR_DAC_L1 = 7, // offset = -1, range: 20℃ ~ 100℃, error < 2℃.
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TEMP_SENSOR_DAC_L2 = 15, // offset = 0, range:-10℃ ~ 80℃, error < 1℃.
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TEMP_SENSOR_DAC_L3 = 11, // offset = 1, range:-30℃ ~ 50℃, error < 2℃.
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TEMP_SENSOR_DAC_L4 = 10, // offset = 2, range:-40℃ ~ 20℃, error < 3℃.
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TEMP_SENSOR_DAC_DEFAULT = TEMP_SENSOR_DAC_L2,
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} temp_sensor_dac_offset_t;;
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typedef struct temp_sensor {
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temp_sensor_dac_offset_t dac_offset;
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uint8_t clk_div;
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} temp_sensor_t;
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esp_err_t temp_sensor_set_config(temp_sensor_t temps);
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esp_err_t temp_sensor_get_config(temp_sensor_t *temps);
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esp_err_t temp_sensor_start(void);
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esp_err_t temp_sensor_stop(void);
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esp_err_t temp_sensor_read(uint8_t *temp_out);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -32,6 +32,13 @@ typedef enum {
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TOUCH_PAD_NUM7, /*!< Touch pad channel 7 is GPIO27*/
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TOUCH_PAD_NUM8, /*!< Touch pad channel 8 is GPIO33*/
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TOUCH_PAD_NUM9, /*!< Touch pad channel 9 is GPIO32*/
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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TOUCH_PAD_NUM10, /*!< Touch pad channel 6 is */
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TOUCH_PAD_NUM11, /*!< Touch pad channel 7 is */
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TOUCH_PAD_NUM12, /*!< Touch pad channel 8 is */
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TOUCH_PAD_NUM13, /*!< Touch pad channel 9 is */
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TOUCH_PAD_NUM14, /*!< Touch pad channel 9 is */
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#endif
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TOUCH_PAD_MAX,
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} touch_pad_t;
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@ -98,9 +105,104 @@ typedef enum {
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TOUCH_FSM_MODE_MAX,
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} touch_fsm_mode_t;
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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typedef enum {
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TOUCH_PAD_INTR_DONE = 0, //each channel measure done.
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TOUCH_PAD_INTR_ACTIVE = 1,
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TOUCH_PAD_INTR_INACTIVE = 2,
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TOUCH_PAD_INTR_ALL,
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TOUCH_PAD_INTR_MAX
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} touch_pad_intr_type_t;
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typedef enum {
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TOUCH_PAD_INTR_MASK_DONE = BIT(0), //each channel measure done.
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TOUCH_PAD_INTR_MASK_ACTIVE = BIT(1),
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TOUCH_PAD_INTR_MASK_INACTIVE = BIT(2),
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TOUCH_PAD_INTR_MASK_ALL = BIT(2)|BIT(1)|BIT(0),
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TOUCH_PAD_INTR_MASK_MAX
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}touch_pad_intr_mask_t;
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typedef enum {
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TOUCH_PAD_DENOISE_BIT12 = 0,
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TOUCH_PAD_DENOISE_BIT10 = 1,
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TOUCH_PAD_DENOISE_BIT8 = 2,
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TOUCH_PAD_DENOISE_BIT4 = 3,
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TOUCH_PAD_DENOISE_MAX
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} touch_pad_denoise_grade_t;
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typedef enum {
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TOUCH_PAD_DENOISE_CAP_L0 = 0, // 0pf
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TOUCH_PAD_DENOISE_CAP_L1 = 4, // 1.4pf
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TOUCH_PAD_DENOISE_CAP_L2 = 2, // 2.8pf
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TOUCH_PAD_DENOISE_CAP_L3 = 6, // 4.2pf
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TOUCH_PAD_DENOISE_CAP_L4 = 1, // 5.6pf
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TOUCH_PAD_DENOISE_CAP_L5 = 5, // 7.0pf
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TOUCH_PAD_DENOISE_CAP_L6 = 3, // 8.4pf
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TOUCH_PAD_DENOISE_CAP_L7 = 7, // 9.8pf
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TOUCH_PAD_DENOISE_CAP_MAX
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} touch_pad_denoise_cap_t;
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typedef struct touch_pad_denoise {
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touch_pad_denoise_grade_t grade;
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touch_pad_denoise_cap_t cap_level;
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} touch_pad_denoise_t;
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typedef enum {
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TOUCH_PAD_SHIELD_DRV_L0 = 0, // 40pf
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TOUCH_PAD_SHIELD_DRV_L1, // 80pf
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TOUCH_PAD_SHIELD_DRV_L2, // 120pf
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TOUCH_PAD_SHIELD_DRV_L3, // 160pf
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TOUCH_PAD_SHIELD_DRV_L4, // 200pf
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TOUCH_PAD_SHIELD_DRV_L5, // 240pf
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TOUCH_PAD_SHIELD_DRV_L6, // 280pf
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TOUCH_PAD_SHIELD_DRV_L7, // 320pf
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TOUCH_PAD_SHIELD_DRV_MAX
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} touch_pad_shield_driver_t;
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typedef struct touch_pad_waterproof {
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touch_pad_t guard_ring_pad;
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touch_pad_shield_driver_t shield_driver;
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} touch_pad_waterproof_t;
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typedef struct touch_pad_approach {
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touch_pad_t select_pad0;
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touch_pad_t select_pad1;
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touch_pad_t select_pad2;
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uint8_t means_num;
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} touch_pad_approach_t;
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typedef enum {
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TOUCH_PAD_CONN_HIGHZ = 0,
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TOUCH_PAD_CONN_GND = 1,
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TOUCH_PAD_CONN_MAX
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} touch_pad_conn_type_t;
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typedef enum {
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TOUCH_PAD_FILTER_IIR_2 = 0,
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TOUCH_PAD_FILTER_IIR_4,
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TOUCH_PAD_FILTER_IIR_8,
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TOUCH_PAD_FILTER_JITTER,
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TOUCH_PAD_FILTER_MAX
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} touch_filter_mode_t;
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typedef struct touch_filter_config {
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touch_filter_mode_t mode;
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uint8_t debounce_cnt; //0 ~ 7.
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uint8_t hysteresis_thr; //0 ~ 3. 0: 1/8; 1: 3/32; 2: 1/16; 3: 1/32;
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uint8_t noise_thr; //0 ~ 3. 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8;
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uint8_t noise_neg_thr; //0 ~ 3. 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8;
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uint8_t neg_noise_limit;//0 ~ 15.
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uint8_t jitter_step; //0 ~ 15.
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} touch_filter_config_t;
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#define TOUCH_PAD_THRESHOLD_MAX 0x1FFFFF//0x3FFFFF
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#endif
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typedef intr_handle_t touch_isr_handle_t;
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#if CONFIG_IDF_TARGET_ESP32
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#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT (0x1000) /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
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#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0x7fff) /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
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#define TOUCH_PAD_MEASURE_WAIT_DEFAULT (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
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@ -109,6 +211,19 @@ typedef intr_handle_t touch_isr_handle_t;
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#define TOUCH_TRIGGER_SOURCE_DEFAULT (TOUCH_TRIGGER_SOURCE_SET1) /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
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#define TOUCH_PAD_BIT_MASK_MAX (0x3ff)
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT (0xf) /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
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#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (300) /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
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#define TOUCH_PAD_MEASURE_WAIT_DEFAULT (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
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#define TOUCH_FSM_MODE_DEFAULT (TOUCH_FSM_MODE_SW) /*!<The touch FSM my be started by the software or timer */
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#define TOUCH_TRIGGER_MODE_DEFAULT (TOUCH_TRIGGER_BELOW) /*!<Interrupts can be triggered if sensor value gets below or above threshold */
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#define TOUCH_TRIGGER_SOURCE_DEFAULT (TOUCH_TRIGGER_SOURCE_SET1) /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
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#define TOUCH_PAD_BIT_MASK_MAX (0x7fff) /* 15 bits */
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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/**
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* @brief Initialize touch module.
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* @note The default FSM mode is 'TOUCH_FSM_MODE_SW'. If you want to use interrupt trigger mode,
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@ -559,6 +674,69 @@ esp_err_t touch_pad_filter_delete();
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*/
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esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_cycle);
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esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_cycle);
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esp_err_t touch_pad_set_inactive_connect(touch_pad_conn_type_t type);
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esp_err_t touch_pad_get_inactive_connect(touch_pad_conn_type_t *type);
|
||||
esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, touch_volt_atten_t atten);
|
||||
esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl, touch_volt_atten_t *atten);
|
||||
esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope);
|
||||
esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope);
|
||||
esp_err_t touch_pad_io_init(touch_pad_t touch_num);
|
||||
esp_err_t touch_pad_fsm_start(touch_fsm_mode_t mode);
|
||||
esp_err_t touch_pad_fsm_stop();
|
||||
esp_err_t touch_pad_get_fsm_mode(touch_fsm_mode_t *mode);
|
||||
esp_err_t touch_pad_sw_start(touch_pad_t *current_scan);
|
||||
uint8_t touch_pad_means_is_done();
|
||||
esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold);
|
||||
esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold);
|
||||
esp_err_t touch_pad_set_group_mask(uint16_t enable_mask);
|
||||
esp_err_t touch_pad_get_group_mask(uint16_t *enable_mask);
|
||||
esp_err_t touch_pad_clear_group_mask(uint16_t enable_mask);
|
||||
uint32_t touch_pad_get_status();
|
||||
esp_err_t touch_pad_clear_status();
|
||||
uint32_t touch_pad_get_int_status();
|
||||
uint32_t touch_pad_get_scan_curr();
|
||||
esp_err_t touch_pad_intr_enable(touch_pad_intr_type_t type);
|
||||
esp_err_t touch_pad_intr_disable(touch_pad_intr_type_t type);
|
||||
uint32_t touch_pad_intr_get_mask();
|
||||
esp_err_t touch_pad_isr_register(intr_handler_t fn, void* arg, touch_pad_intr_mask_t intr_mask);
|
||||
esp_err_t touch_pad_config(touch_pad_t touch_num);
|
||||
esp_err_t touch_pad_init();
|
||||
esp_err_t touch_pad_read_raw(touch_pad_t touch_num, uint32_t *raw_data);
|
||||
esp_err_t touch_pad_read_baseline(touch_pad_t touch_num, uint32_t *basedata);
|
||||
esp_err_t touch_pad_filter_baseline_read(touch_pad_t touch_num, uint32_t *basedata);
|
||||
esp_err_t touch_pad_filter_baseline_reset(touch_pad_t touch_num);
|
||||
esp_err_t touch_pad_read_debounce(touch_pad_t touch_num, uint32_t *debounce);
|
||||
esp_err_t touch_pad_read_thresh(touch_pad_t touch_num, uint32_t *thresh_out);
|
||||
esp_err_t touch_pad_filter_set_config(touch_filter_config_t filter_info);
|
||||
esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info);
|
||||
esp_err_t touch_pad_filter_start();
|
||||
esp_err_t touch_pad_filter_stop();
|
||||
esp_err_t touch_pad_denoise_enable();
|
||||
esp_err_t touch_pad_denoise_disable();
|
||||
esp_err_t touch_pad_denoise_set_config(touch_pad_denoise_t denoise);
|
||||
esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise);
|
||||
esp_err_t touch_pad_denoise_data_get(uint32_t *data);
|
||||
esp_err_t touch_pad_waterproof_set_config(touch_pad_waterproof_t waterproof);
|
||||
esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof);
|
||||
esp_err_t touch_pad_waterproof_enable();
|
||||
esp_err_t touch_pad_waterproof_disable();
|
||||
esp_err_t touch_pad_approach_set_config(touch_pad_approach_t approach);
|
||||
esp_err_t touch_pad_approach_get_config(touch_pad_approach_t *approach);
|
||||
esp_err_t touch_pad_approach_disable();
|
||||
uint32_t touch_pad_approach_get_cnt(uint8_t pad);
|
||||
esp_err_t touch_pad_reset();
|
||||
void touch_pad_fake_trigger(touch_pad_t pad_num);
|
||||
|
||||
/** sleep pad **/
|
||||
esp_err_t touch_pad_sleep_pad_config(touch_pad_t pad, uint32_t sleep_thr, uint8_t is_approach);
|
||||
void touch_sleep_baseline_get(uint32_t *baseline);
|
||||
void touch_sleep_debounce_get(uint32_t *debounce);
|
||||
void touch_sleep_approach_cnt_get(uint32_t *approach_cnt);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -109,6 +109,7 @@ portMUX_TYPE adc2_spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||
//prevent ADC1 being used by I2S dma and other tasks at the same time.
|
||||
static _lock_t adc1_i2s_lock;
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
typedef struct {
|
||||
TimerHandle_t timer;
|
||||
uint16_t filtered_val[TOUCH_PAD_MAX];
|
||||
@ -121,6 +122,7 @@ static touch_pad_filter_t *s_touch_pad_filter = NULL;
|
||||
// check if touch pad be inited.
|
||||
static uint16_t s_touch_pad_init_bit = 0x0000;
|
||||
static filter_cb_t s_filter_cb = NULL;
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
typedef volatile struct {
|
||||
@ -497,6 +499,11 @@ esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num)
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold);
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.pad_hold.val |= BIT(gpio_num);
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
#endif
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -511,6 +518,11 @@ esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num)
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].hold);
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
RTC_MODULE_CHECK(rtc_gpio_is_valid_gpio(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.pad_hold.val &= ~(BIT(gpio_num));
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
#endif
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -602,7 +614,7 @@ esp_err_t rtc_gpio_force_hold_all()
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
/*---------------------------------------------------------------
|
||||
Touch Pad
|
||||
---------------------------------------------------------------*/
|
||||
@ -1248,10 +1260,24 @@ esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num)
|
||||
*pad_num = touch_pad_num_wrap((touch_pad_t)(__builtin_ffs(touch_mask) - 1));
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
/*---------------------------------------------------------------
|
||||
ADC Common
|
||||
---------------------------------------------------------------*/
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down
|
||||
#define SENS_FORCE_XPD_AMP_PD 2 // Force power down
|
||||
#define SENS_FORCE_XPD_AMP_PU 3 // Force power up
|
||||
|
||||
#define SENS_SAR1_ATTEN_VAL_MASK 0x3
|
||||
#define SENS_SAR2_ATTEN_VAL_MASK 0x3
|
||||
|
||||
#define SENS_FORCE_XPD_SAR_SW_M (BIT(1))
|
||||
#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
|
||||
#define SENS_FORCE_XPD_SAR_PD 2 // Force power down
|
||||
#define SENS_FORCE_XPD_SAR_PU 3 // Force power up
|
||||
#endif
|
||||
|
||||
static esp_err_t adc_set_fsm_time(int rst_wait, int start_wait, int standby_wait, int sample_cycle)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
@ -1345,13 +1371,18 @@ static esp_err_t adc_set_atten(adc_unit_t adc_unit, adc_channel_t channel, adc_a
|
||||
void adc_power_always_on()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
#endif
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
}
|
||||
|
||||
void adc_power_on()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//The power FSM controlled mode saves more power, while the ADC noise may get increased.
|
||||
#ifndef CONFIG_ADC_FORCE_XPD_FSM
|
||||
//Set the power always on to increase precision.
|
||||
@ -1363,6 +1394,20 @@ void adc_power_on()
|
||||
} else {
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
|
||||
}
|
||||
#endif
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
//The power FSM controlled mode saves more power, while the ADC noise may get increased.
|
||||
#ifndef CONFIG_ADC_FORCE_XPD_FSM
|
||||
//Set the power always on to increase precision.
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
#else
|
||||
//Use the FSM to turn off the power while not used to save power.
|
||||
if (SENS.sar_power_xpd_sar.force_xpd_sar & SENS_FORCE_XPD_SAR_SW_M) {
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
} else {
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
}
|
||||
@ -1370,9 +1415,14 @@ void adc_power_on()
|
||||
void adc_power_off()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//Bit1 0:Fsm 1: SW mode
|
||||
//Bit0 0:SW mode power down 1: SW mode power on
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
|
||||
#endif
|
||||
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
}
|
||||
|
||||
@ -1413,6 +1463,7 @@ esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
|
||||
esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if (adc_unit & ADC_UNIT_1) {
|
||||
// Enable ADC data invert
|
||||
SENS.sar_read_ctrl.sar1_data_inv = inv_en;
|
||||
@ -1421,6 +1472,16 @@ esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
|
||||
// Enable ADC data invert
|
||||
SENS.sar_read_ctrl2.sar2_data_inv = inv_en;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
if (adc_unit & ADC_UNIT_1) {
|
||||
// Enable ADC data invert
|
||||
SENS.sar_reader1_ctrl.sar1_data_inv = inv_en;
|
||||
}
|
||||
if (adc_unit & ADC_UNIT_2) {
|
||||
// Enable ADC data invert
|
||||
SENS.sar_reader2_ctrl.sar2_data_inv = inv_en;
|
||||
}
|
||||
#endif
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1430,6 +1491,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
|
||||
ADC_CHECK_UNIT(adc_unit);
|
||||
RTC_MODULE_CHECK(bits < ADC_WIDTH_MAX, "ADC bit width error", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if (adc_unit & ADC_UNIT_1) {
|
||||
SENS.sar_start_force.sar1_bit_width = bits;
|
||||
SENS.sar_read_ctrl.sar1_sample_bit = bits;
|
||||
@ -1438,6 +1500,16 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
|
||||
SENS.sar_start_force.sar2_bit_width = bits;
|
||||
SENS.sar_read_ctrl2.sar2_sample_bit = bits;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
if (adc_unit & ADC_UNIT_1) {
|
||||
SENS.sar_meas1_ctrl1.sar1_bit_width = bits;
|
||||
SENS.sar_reader1_ctrl.sar1_sample_bit = bits;
|
||||
}
|
||||
if (adc_unit & ADC_UNIT_2) {
|
||||
SENS.sar_meas2_ctrl1.sar2_bit_width = bits;
|
||||
SENS.sar_reader2_ctrl.sar2_sample_bit = bits;
|
||||
}
|
||||
#endif
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1445,6 +1517,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
|
||||
// this function should be called in the critical section
|
||||
static void adc_set_controller(adc_unit_t unit, adc_controller_t ctrl )
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if ( unit == ADC_UNIT_1 ) {
|
||||
switch( ctrl ) {
|
||||
case ADC_CTRL_RTC:
|
||||
@ -1505,18 +1578,87 @@ static void adc_set_controller(adc_unit_t unit, adc_controller_t ctrl )
|
||||
break;
|
||||
default:
|
||||
ESP_LOGE(TAG, "adc2 selects invalid controller");
|
||||
break;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
ESP_LOGE(TAG, "invalid adc unit");
|
||||
assert(0);
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
if ( unit == ADC_UNIT_1 ) {
|
||||
switch( ctrl ) {
|
||||
case ADC_CTRL_RTC:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = false; //RTC controller controls the ADC, not digital controller
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = true; //RTC controller controls the ADC,not ulp coprocessor
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = true; //RTC controller controls the data port, not ulp coprocessor
|
||||
SENS.sar_hall_ctrl.xpd_hall_force = true; // RTC controller controls the hall sensor power,not ulp coprocessor
|
||||
SENS.sar_hall_ctrl.hall_phase_force = true; // RTC controller controls the hall sensor phase,not ulp coprocessor
|
||||
break;
|
||||
case ADC_CTRL_ULP:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = false;
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = false;
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = false;
|
||||
SENS.sar_hall_ctrl.xpd_hall_force = false;
|
||||
SENS.sar_hall_ctrl.hall_phase_force = false;
|
||||
break;
|
||||
case ADC_CTRL_DIG:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = true;
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = true;
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = true;
|
||||
SENS.sar_hall_ctrl.xpd_hall_force = true;
|
||||
SENS.sar_hall_ctrl.hall_phase_force = true;
|
||||
break;
|
||||
default:
|
||||
ESP_LOGE(TAG, "adc1 selects invalid controller");
|
||||
break;
|
||||
}
|
||||
} else if ( unit == ADC_UNIT_2) {
|
||||
switch( ctrl ) {
|
||||
case ADC_CTRL_RTC:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = true; //RTC controller controls the ADC,not ulp coprocessor
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = true; //RTC controller controls the data port, not ulp coprocessor
|
||||
// SENS.sar_read_ctrl2.sar2_dig_force = false; //RTC controller controls the ADC, not digital controller
|
||||
// SENS.sar_read_ctrl2.sar2_pwdet_force = false; //RTC controller controls the ADC, not PWDET
|
||||
SYSCON.saradc_ctrl.sar2_mux = true; //RTC controller controls the ADC, not PWDET
|
||||
break;
|
||||
case ADC_CTRL_ULP:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = false;
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = false;
|
||||
// SENS.sar_read_ctrl2.sar2_dig_force = false;
|
||||
// SENS.sar_read_ctrl2.sar2_pwdet_force = false;
|
||||
SYSCON.saradc_ctrl.sar2_mux = true;
|
||||
break;
|
||||
case ADC_CTRL_DIG:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = true;
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = true;
|
||||
// SENS.sar_read_ctrl2.sar2_dig_force = true;
|
||||
// SENS.sar_read_ctrl2.sar2_pwdet_force = false;
|
||||
SYSCON.saradc_ctrl.sar2_mux = true;
|
||||
break;
|
||||
case ADC2_CTRL_PWDET:
|
||||
//currently only used by Wi-Fi
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = true;
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = true;
|
||||
// SENS.sar_read_ctrl2.sar2_dig_force = false;
|
||||
// SENS.sar_read_ctrl2.sar2_pwdet_force = true;
|
||||
SYSCON.saradc_ctrl.sar2_mux = false;
|
||||
break;
|
||||
default:
|
||||
ESP_LOGE(TAG, "adc2 selects invalid controller");
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
ESP_LOGE(TAG, "invalid adc unit");
|
||||
assert(0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// this function should be called in the critical section
|
||||
static int adc_convert( adc_unit_t unit, int channel)
|
||||
{
|
||||
uint16_t adc_value;
|
||||
uint16_t adc_value = 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if ( unit == ADC_UNIT_1 ) {
|
||||
SENS.sar_meas_start1.sar1_en_pad = (1 << channel); //only one channel is selected.
|
||||
while (SENS.sar_slave_addr1.meas_status != 0);
|
||||
@ -1535,6 +1677,26 @@ static int adc_convert( adc_unit_t unit, int channel)
|
||||
ESP_LOGE(TAG, "invalid adc unit");
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
if ( unit == ADC_UNIT_1 ) {
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected.
|
||||
while (SENS.sar_slave_addr1.meas_status != 0);
|
||||
SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
|
||||
SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
|
||||
while (SENS.sar_meas1_ctrl2.meas1_done_sar == 0);
|
||||
adc_value = SENS.sar_meas1_ctrl2.meas1_data_sar;
|
||||
} else if ( unit == ADC_UNIT_2 ) {
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected.
|
||||
|
||||
SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0
|
||||
SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1
|
||||
while (SENS.sar_meas2_ctrl2.meas2_done_sar == 0) {}; //read done
|
||||
adc_value = SENS.sar_meas2_ctrl2.meas2_data_sar;
|
||||
} else {
|
||||
ESP_LOGE(TAG, "invalid adc unit");
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
#endif
|
||||
return adc_value;
|
||||
}
|
||||
|
||||
@ -1675,6 +1837,7 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
|
||||
|
||||
static inline void adc1_fsm_disable()
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//channel is set in the convert function
|
||||
SENS.sar_meas_wait2.force_xpd_amp = SENS_FORCE_XPD_AMP_PD;
|
||||
//disable FSM, it's only used by the LNA.
|
||||
@ -1683,7 +1846,18 @@ static inline void adc1_fsm_disable()
|
||||
SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
|
||||
SENS.sar_meas_wait1.sar_amp_wait1 = 1;
|
||||
SENS.sar_meas_wait1.sar_amp_wait2 = 1;
|
||||
SENS.sar_meas_wait2.sar_amp_wait3 = 1;
|
||||
SENS.sar_meas_wait2.sar_amp_wait3 = 1;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
//channel is set in the convert function
|
||||
SENS.sar_meas1_ctrl1.force_xpd_amp = SENS_FORCE_XPD_AMP_PD;
|
||||
//disable FSM, it's only used by the LNA.
|
||||
SENS.sar_amp_ctrl3.amp_rst_fb_fsm = 0;
|
||||
SENS.sar_amp_ctrl3.amp_short_ref_fsm = 0;
|
||||
SENS.sar_amp_ctrl3.amp_short_ref_gnd_fsm = 0;
|
||||
SENS.sar_amp_ctrl1.sar_amp_wait1 = 1;
|
||||
SENS.sar_amp_ctrl1.sar_amp_wait2 = 1;
|
||||
SENS.sar_amp_ctrl2.sar_amp_wait3 = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
esp_err_t adc1_i2s_mode_acquire()
|
||||
@ -1693,9 +1867,15 @@ esp_err_t adc1_i2s_mode_acquire()
|
||||
_lock_acquire( &adc1_i2s_lock );
|
||||
ESP_LOGD( RTC_MODULE_TAG, "i2s mode takes adc1 lock." );
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
//switch SARADC into DIG channel
|
||||
SENS.sar_read_ctrl.sar1_dig_force = 1;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
//switch SARADC into DIG channel
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 1;
|
||||
#endif
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1705,13 +1885,18 @@ esp_err_t adc1_adc_mode_acquire()
|
||||
//lazy initialization
|
||||
//for adc1, block until acquire the lock
|
||||
_lock_acquire( &adc1_i2s_lock );
|
||||
ESP_LOGD( RTC_MODULE_TAG, "adc mode takes adc1 lock." );
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
// for now the WiFi would use ADC2 and set xpd_sar force on.
|
||||
// so we can not reset xpd_sar to fsm mode directly.
|
||||
// We should handle this after the synchronization mechanism is established.
|
||||
|
||||
//switch SARADC into RTC channel
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SENS.sar_read_ctrl.sar1_dig_force = 0;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 0;
|
||||
#endif
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -1864,6 +2049,7 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
|
||||
static inline void adc2_config_width(adc_bits_width_t width_bit)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//sar_start_force shared with ADC1
|
||||
SENS.sar_start_force.sar2_bit_width = width_bit;
|
||||
//cct set to the same value with PHY
|
||||
@ -1874,15 +2060,34 @@ static inline void adc2_config_width(adc_bits_width_t width_bit)
|
||||
SENS.sar_read_ctrl2.sar2_data_inv = 1;
|
||||
//Set The adc sample width,invert adc value,must digital sar2_bit_width[1:0]=3
|
||||
SENS.sar_read_ctrl2.sar2_sample_bit = width_bit;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
//sar_start_force shared with ADC1
|
||||
SENS.sar_meas2_ctrl1.sar2_bit_width = width_bit;
|
||||
//cct set to the same value with PHY
|
||||
SENS.sar_meas2_mux.sar2_pwdet_cct = 4;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
//Invert the adc value,the Output value is invert
|
||||
SENS.sar_reader2_ctrl.sar2_data_inv = 1;
|
||||
//Set The adc sample width,invert adc value,must digital sar2_bit_width[1:0]=3
|
||||
SENS.sar_reader2_ctrl.sar2_sample_bit = width_bit;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void adc2_dac_disable( adc2_channel_t channel)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 1
|
||||
dac_output_set_enable( DAC_CHANNEL_1, false );
|
||||
} else if ( channel == ADC2_CHANNEL_9 ) {
|
||||
dac_output_set_enable( DAC_CHANNEL_2, false );
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 1
|
||||
dac_output_set_enable( DAC_CHANNEL_1, false );
|
||||
} else if ( channel == ADC2_CHANNEL_7 ) {
|
||||
dac_output_set_enable( DAC_CHANNEL_2, false );
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
//registers in critical section with adc1:
|
||||
@ -1926,7 +2131,6 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
int channel;
|
||||
|
||||
if(gpio == GPIO_NUM_25){
|
||||
channel = 8; //Channel 8 bit
|
||||
}else if (gpio == GPIO_NUM_26){
|
||||
|
99
components/driver/rtc_tempsensor.c
Normal file
99
components/driver/rtc_tempsensor.c
Normal file
@ -0,0 +1,99 @@
|
||||
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <stdlib.h>
|
||||
#include <ctype.h>
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/rtc_io_struct.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "soc/sens_struct.h"
|
||||
#include "temp_sensor.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
|
||||
#define TEMP_SENSOR_XPD_WAIT_DEFAULT 0xFF /* Set wait cycle time(8MHz) from power up to reset enable. */
|
||||
|
||||
portMUX_TYPE rtc_temp_spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||
static SemaphoreHandle_t rtc_touch_mux = NULL;
|
||||
|
||||
esp_err_t temp_sensor_set_config(temp_sensor_t temps)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_temp_spinlock);
|
||||
SENS.sar_tctrl.tsens_dac = temps.dac_offset;
|
||||
SENS.sar_tctrl.tsens_clk_div = temps.clk_div;
|
||||
SENS.sar_tctrl.tsens_power_up_force = 1;
|
||||
SENS.sar_tctrl2.tsens_xpd_wait = TEMP_SENSOR_XPD_WAIT_DEFAULT;
|
||||
SENS.sar_tctrl2.tsens_xpd_force = 1;
|
||||
SENS.sar_tctrl2.tsens_reset = 1;// Reset the temp sensor.
|
||||
SENS.sar_tctrl2.tsens_reset = 0;// Clear the reset status.
|
||||
portEXIT_CRITICAL(&rtc_temp_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t temp_sensor_get_config(temp_sensor_t *temps)
|
||||
{
|
||||
if(temps) {
|
||||
portENTER_CRITICAL(&rtc_temp_spinlock);
|
||||
temps->dac_offset = SENS.sar_tctrl.tsens_dac;
|
||||
temps->clk_div = SENS.sar_tctrl.tsens_clk_div;
|
||||
portEXIT_CRITICAL(&rtc_temp_spinlock);
|
||||
return ESP_OK;
|
||||
} else {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t temp_sensor_start(void)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_temp_spinlock);
|
||||
SENS.sar_tctrl.tsens_dump_out = 0;
|
||||
SENS.sar_tctrl2.tsens_clkgate_en = 1;
|
||||
SENS.sar_tctrl.tsens_power_up = 1;
|
||||
portEXIT_CRITICAL(&rtc_temp_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t temp_sensor_stop(void)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_temp_spinlock);
|
||||
SENS.sar_tctrl.tsens_power_up = 0;
|
||||
SENS.sar_tctrl2.tsens_clkgate_en = 0;
|
||||
portEXIT_CRITICAL(&rtc_temp_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t temp_sensor_read(uint8_t *temp_out)
|
||||
{
|
||||
if(temp_out) {
|
||||
portENTER_CRITICAL(&rtc_temp_spinlock);
|
||||
SENS.sar_tctrl.tsens_dump_out = 1;
|
||||
while(!SENS.sar_tctrl.tsens_ready);
|
||||
*temp_out = SENS.sar_tctrl.tsens_out;
|
||||
SENS.sar_tctrl.tsens_dump_out = 0;
|
||||
portEXIT_CRITICAL(&rtc_temp_spinlock);
|
||||
return ESP_OK;
|
||||
} else {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
#endif
|
738
components/driver/rtc_touchpad.c
Normal file
738
components/driver/rtc_touchpad.c
Normal file
@ -0,0 +1,738 @@
|
||||
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <stdlib.h>
|
||||
#include <ctype.h>
|
||||
#include "esp_log.h"
|
||||
#include "soc/rtc_periph.h"
|
||||
#include "soc/sens_periph.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/rtc_io_struct.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "soc/sens_struct.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_cntl_struct.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "rtc_io.h"
|
||||
#include "touch_pad.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/xtensa_api.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "freertos/timers.h"
|
||||
#include "esp_intr_alloc.h"
|
||||
#include "sys/lock.h"
|
||||
#include "driver/rtc_cntl.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "sdkconfig.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
#include "esp32s2beta/rom/ets_sys.h"
|
||||
#endif
|
||||
|
||||
#ifndef NDEBUG
|
||||
// Enable built-in checks in queue.h in debug builds
|
||||
#define INVARIANTS
|
||||
#endif
|
||||
#include "sys/queue.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
|
||||
#define TOUCH_PAD_FILTER_FACTOR_DEFAULT (4) // IIR filter coefficient.
|
||||
#define TOUCH_PAD_SHIFT_DEFAULT (4) // Increase computing accuracy.
|
||||
#define TOUCH_PAD_SHIFT_ROUND_DEFAULT (8) // ROUND = 2^(n-1); rounding off for fractional.
|
||||
#define DAC_ERR_STR_CHANNEL_ERROR "DAC channel error"
|
||||
|
||||
static portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||
static const char *RTC_MODULE_TAG = "RTC_MODULE";
|
||||
|
||||
#define RTC_MODULE_CHECK(a, str, ret_val) if (!(a)) { \
|
||||
ESP_LOGE(RTC_MODULE_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \
|
||||
return (ret_val); \
|
||||
}
|
||||
|
||||
#define RTC_RES_CHECK(res, ret_val) if ( (a) != ESP_OK) { \
|
||||
ESP_LOGE(RTC_MODULE_TAG,"%s:%d (%s)", __FILE__, __LINE__, __FUNCTION__); \
|
||||
return (ret_val); \
|
||||
}
|
||||
static SemaphoreHandle_t rtc_touch_mux = NULL;
|
||||
|
||||
// check if touch pad be inited.
|
||||
static uint16_t s_touch_pad_init_bit = 0x0000;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Touch Pad
|
||||
---------------------------------------------------------------*/
|
||||
esp_err_t touch_pad_isr_register(intr_handler_t fn, void* arg, touch_pad_intr_mask_t intr_mask)
|
||||
{
|
||||
RTC_MODULE_CHECK(intr_mask < TOUCH_PAD_INTR_MASK_MAX, "intr mask err", ESP_ERR_INVALID_ARG);
|
||||
RTC_MODULE_CHECK(fn, "Touch_Pad ISR null", ESP_ERR_INVALID_ARG);
|
||||
return rtc_isr_register(fn, arg, intr_mask << RTC_CNTL_TOUCH_DONE_INT_ENA_S);
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_isr_deregister(intr_handler_t fn, void *arg)
|
||||
{
|
||||
return rtc_isr_deregister(fn, arg);
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_cycle)
|
||||
{
|
||||
xSemaphoreTake(rtc_touch_mux, portMAX_DELAY);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
// touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK( can be 150k or 32k depending on the options)
|
||||
RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_cycle;
|
||||
//touch sensor measure time= meas_cycle / 8Mhz
|
||||
RTCCNTL.touch_ctrl1.touch_meas_num = meas_cycle;
|
||||
//the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
|
||||
RTCCNTL.touch_ctrl2.touch_xpd_wait = 255; //wait volt stable
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
xSemaphoreGive(rtc_touch_mux);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_cycle)
|
||||
{
|
||||
RTC_MODULE_CHECK(sleep_cycle != NULL, "parameter is NULL", ESP_ERR_INVALID_ARG);
|
||||
RTC_MODULE_CHECK(meas_cycle != NULL, "parameter is NULL", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
*sleep_cycle = RTCCNTL.touch_ctrl1.touch_sleep_cycles;
|
||||
*meas_cycle = RTCCNTL.touch_ctrl1.touch_meas_num;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_set_inactive_connect(touch_pad_conn_type_t type)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_inactive_connection = type;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_inactive_connect(touch_pad_conn_type_t *type)
|
||||
{
|
||||
if(type) {
|
||||
*type = RTCCNTL.touch_scan_ctrl.touch_inactive_connection;
|
||||
return ESP_FAIL;
|
||||
} else {
|
||||
return ESP_OK;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, touch_volt_atten_t atten)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if (refh > TOUCH_HVOLT_KEEP) {
|
||||
RTCCNTL.touch_ctrl2.touch_drefh = refh;
|
||||
}
|
||||
if (refl > TOUCH_LVOLT_KEEP) {
|
||||
RTCCNTL.touch_ctrl2.touch_drefl = refl;
|
||||
}
|
||||
if (atten > TOUCH_HVOLT_ATTEN_KEEP) {
|
||||
RTCCNTL.touch_ctrl2.touch_drange = atten;
|
||||
}
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl, touch_volt_atten_t *atten)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if (refh) {
|
||||
*refh = RTCCNTL.touch_ctrl2.touch_drefh;
|
||||
}
|
||||
if (refl) {
|
||||
*refl = RTCCNTL.touch_ctrl2.touch_drefl;
|
||||
}
|
||||
if (atten) {
|
||||
*atten = RTCCNTL.touch_ctrl2.touch_drange;
|
||||
}
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCIO.touch_pad[touch_num].tie_opt = TOUCH_PAD_TIE_OPT_LOW;
|
||||
RTCIO.touch_pad[touch_num].dac = slope;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if(slope) {
|
||||
*slope = RTCIO.touch_pad[touch_num].dac;
|
||||
}
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_io_init(touch_pad_t touch_num)
|
||||
{
|
||||
RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG);
|
||||
RTC_MODULE_CHECK((touch_num > TOUCH_PAD_NUM0), "touch IO error", ESP_ERR_INVALID_ARG);
|
||||
gpio_num_t gpio_num = GPIO_NUM_1;
|
||||
gpio_num = touch_num;
|
||||
rtc_gpio_init(gpio_num);
|
||||
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
|
||||
rtc_gpio_pulldown_dis(gpio_num);
|
||||
rtc_gpio_pullup_dis(gpio_num);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_wait_init_done()
|
||||
{
|
||||
// TODO
|
||||
return ESP_FAIL;
|
||||
}
|
||||
|
||||
/*touch_pad_fsm_start_vf, after set mask*/
|
||||
esp_err_t touch_pad_fsm_start(touch_fsm_mode_t mode)
|
||||
{
|
||||
RTC_MODULE_CHECK((mode < TOUCH_FSM_MODE_MAX), "touch fsm mode error", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_ctrl2.touch_start_en = 0; //stop touch fsm
|
||||
RTCCNTL.touch_ctrl2.touch_start_force = mode;
|
||||
RTCCNTL.touch_ctrl2.touch_slp_timer_en = (mode == TOUCH_FSM_MODE_TIMER ? 1 : 0);
|
||||
RTCCNTL.touch_ctrl2.touch_clkgate_en = 1; //enable touch clock for FSM. or force enable.
|
||||
SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_MAX; // clear baseline
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_fsm_stop()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_ctrl2.touch_start_en = 0; //stop touch fsm
|
||||
RTCCNTL.touch_ctrl2.touch_slp_timer_en = 0;
|
||||
RTCCNTL.touch_ctrl2.touch_clkgate_en = 0; //enable touch clock for FSM. or force enable.
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_fsm_mode(touch_fsm_mode_t *mode)
|
||||
{
|
||||
if (mode) {
|
||||
*mode = RTCCNTL.touch_ctrl2.touch_start_force;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* If doing measure, the flag will be self-clear.
|
||||
* After measure, the flag will be set.
|
||||
*/
|
||||
uint8_t touch_pad_means_is_done()
|
||||
{
|
||||
return SENS.sar_touch_chn_st.touch_meas_done;
|
||||
}
|
||||
|
||||
/* return the current scan channel. */
|
||||
esp_err_t touch_pad_sw_start(touch_pad_t *current_scan)
|
||||
{
|
||||
RTC_MODULE_CHECK((RTCCNTL.touch_ctrl2.touch_start_force == TOUCH_FSM_MODE_SW),
|
||||
"touch IO error", ESP_FAIL);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_ctrl2.touch_start_en = 0;
|
||||
RTCCNTL.touch_ctrl2.touch_start_en = 1;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
if(current_scan) {
|
||||
*current_scan = SENS.sar_touch_status0.touch_scan_curr;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/* If set "TOUCH_PAD_THRESHOLD_MAX", the filter is not triger. */
|
||||
esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold)
|
||||
{
|
||||
RTC_MODULE_CHECK((threshold != 0), "threshold error", ESP_ERR_INVALID_ARG);
|
||||
RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG);
|
||||
RTC_MODULE_CHECK((touch_num > TOUCH_PAD_NUM0), "touch0 no thresh", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
SENS.touch_thresh[touch_num-1].thresh = threshold;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold)
|
||||
{
|
||||
RTC_MODULE_CHECK((touch_num < TOUCH_PAD_MAX), "touch IO error", ESP_ERR_INVALID_ARG);
|
||||
if (threshold) {
|
||||
*threshold = SENS.touch_thresh[touch_num-1].thresh;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/* If set mask, the FSM timer should be stop firsty.
|
||||
* Noitce: The touchpad that in scan map ,should be deinit digital function firstly.
|
||||
* */
|
||||
esp_err_t touch_pad_set_group_mask(uint16_t enable_mask)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_scan_pad_map |= (enable_mask&TOUCH_PAD_BIT_MASK_MAX);
|
||||
SENS.sar_touch_conf.touch_outen |= (enable_mask&TOUCH_PAD_BIT_MASK_MAX);
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_group_mask(uint16_t *enable_mask)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
*enable_mask = SENS.sar_touch_conf.touch_outen \
|
||||
& RTCCNTL.touch_scan_ctrl.touch_scan_pad_map \
|
||||
& TOUCH_PAD_BIT_MASK_MAX;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/* If clear all mask, the FSM timer should be stop firsty. */
|
||||
esp_err_t touch_pad_clear_group_mask(uint16_t enable_mask)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
SENS.sar_touch_conf.touch_outen &= ~(enable_mask&TOUCH_PAD_BIT_MASK_MAX);
|
||||
RTCCNTL.touch_scan_ctrl.touch_scan_pad_map &= ~(enable_mask&TOUCH_PAD_BIT_MASK_MAX);
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR touch_pad_get_int_status()
|
||||
{
|
||||
return REG_READ(RTC_CNTL_INT_ST_REG) >> (RTC_CNTL_TOUCH_DONE_INT_ST_S) & (TOUCH_PAD_INTR_MASK_ALL);
|
||||
}
|
||||
|
||||
/*
|
||||
* The "touch_pad_active" will be change auto.
|
||||
* If status bit is 1, this pad is be active, else, this pad is inactive.
|
||||
*/
|
||||
uint32_t IRAM_ATTR touch_pad_get_status()
|
||||
{
|
||||
return (SENS.sar_touch_chn_st.touch_pad_active & TOUCH_PAD_BIT_MASK_MAX);
|
||||
}
|
||||
// get current scan channel. note: in interrupt and set a litter sleep time.
|
||||
uint32_t IRAM_ATTR touch_pad_get_scan_curr()
|
||||
{
|
||||
return (SENS.sar_touch_status0.touch_scan_curr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Normaly, Should't call this function manual. .
|
||||
*/
|
||||
esp_err_t IRAM_ATTR touch_pad_clear_status()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
SENS.sar_touch_conf.touch_status_clr = 1;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_intr_enable(touch_pad_intr_type_t type)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if(type == TOUCH_PAD_INTR_DONE) {
|
||||
RTCCNTL.int_ena.rtc_touch_done = 1;
|
||||
} else if(type == TOUCH_PAD_INTR_ACTIVE) {
|
||||
RTCCNTL.int_ena.rtc_touch_active = 1;
|
||||
} else if(type == TOUCH_PAD_INTR_INACTIVE) {
|
||||
RTCCNTL.int_ena.rtc_touch_inactive = 1;
|
||||
} else if(type == TOUCH_PAD_INTR_ALL){
|
||||
RTCCNTL.int_ena.rtc_touch_done = 1;
|
||||
RTCCNTL.int_ena.rtc_touch_active = 1;
|
||||
RTCCNTL.int_ena.rtc_touch_inactive = 1;
|
||||
} else {
|
||||
ESP_LOGE(RTC_MODULE_TAG, "no this intr type");
|
||||
}
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_intr_disable(touch_pad_intr_type_t type)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if(type == TOUCH_PAD_INTR_DONE) {
|
||||
RTCCNTL.int_ena.rtc_touch_done = 0;
|
||||
} else if(type == TOUCH_PAD_INTR_ACTIVE) {
|
||||
RTCCNTL.int_ena.rtc_touch_active = 0;
|
||||
} else if(type == TOUCH_PAD_INTR_INACTIVE) {
|
||||
RTCCNTL.int_ena.rtc_touch_inactive = 0;
|
||||
} else if(type == TOUCH_PAD_INTR_ALL){
|
||||
RTCCNTL.int_ena.rtc_touch_done = 0;
|
||||
RTCCNTL.int_ena.rtc_touch_active = 0;
|
||||
RTCCNTL.int_ena.rtc_touch_inactive = 0;
|
||||
} else {
|
||||
ESP_LOGE(RTC_MODULE_TAG, "no this intr type");
|
||||
}
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR touch_pad_intr_get_mask()
|
||||
{
|
||||
return REG_READ(RTC_CNTL_INT_ENA_REG) >> (RTC_CNTL_TOUCH_DONE_INT_ENA_S) & (TOUCH_PAD_INTR_MASK_ALL);
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_config(touch_pad_t touch_num)
|
||||
{
|
||||
RTC_MODULE_CHECK(rtc_touch_mux != NULL, "Touch pad not initialized", ESP_FAIL);
|
||||
RTC_MODULE_CHECK(touch_num < TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG);
|
||||
|
||||
touch_pad_io_init(touch_num);
|
||||
touch_pad_set_cnt_mode(touch_num, TOUCH_PAD_SLOPE_7);
|
||||
touch_pad_set_thresh(touch_num, TOUCH_PAD_THRESHOLD_MAX);
|
||||
touch_pad_set_group_mask(BIT(touch_num));
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_init()
|
||||
{
|
||||
if (rtc_touch_mux == NULL) {
|
||||
rtc_touch_mux = xSemaphoreCreateMutex();
|
||||
}
|
||||
if (rtc_touch_mux == NULL) {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
touch_pad_intr_disable(TOUCH_PAD_INTR_ALL);
|
||||
touch_pad_clear_group_mask(TOUCH_PAD_BIT_MASK_MAX);
|
||||
touch_pad_clear_status();
|
||||
touch_pad_set_meas_time(TOUCH_PAD_SLEEP_CYCLE_DEFAULT, TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
|
||||
// Set reference voltage for charging/discharging
|
||||
touch_pad_set_voltage(TOUCH_HVOLT_2V7, TOUCH_LVOLT_0V5, TOUCH_HVOLT_ATTEN_0V5);
|
||||
touch_pad_set_inactive_connect(TOUCH_PAD_CONN_GND);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_deinit()
|
||||
{
|
||||
RTC_MODULE_CHECK(rtc_touch_mux != NULL, "Touch pad not initialized", ESP_FAIL);
|
||||
xSemaphoreTake(rtc_touch_mux, portMAX_DELAY);
|
||||
s_touch_pad_init_bit = 0x0000;
|
||||
touch_pad_fsm_stop();
|
||||
touch_pad_clear_status();
|
||||
touch_pad_intr_disable(TOUCH_PAD_INTR_ALL);
|
||||
xSemaphoreGive(rtc_touch_mux);
|
||||
vSemaphoreDelete(rtc_touch_mux);
|
||||
rtc_touch_mux = NULL;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/*raw data 的单位是时间,单位是 1/8MHz */
|
||||
IRAM_ATTR esp_err_t touch_pad_read_raw(touch_pad_t touch_num, uint32_t *raw_data)
|
||||
{
|
||||
RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL);
|
||||
if (raw_data) {
|
||||
*raw_data = SENS.touch_meas[touch_num].meas_out;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
|
||||
IRAM_ATTR esp_err_t touch_pad_filter_baseline_read(touch_pad_t touch_num, uint32_t *basedata)
|
||||
{
|
||||
RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL);
|
||||
if (basedata) {
|
||||
*basedata = SENS.sar_touch_status[touch_num-1].touch_pad_baseline;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
IRAM_ATTR esp_err_t touch_pad_read_debounce(touch_pad_t touch_num, uint32_t *debounce)
|
||||
{
|
||||
RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL);
|
||||
if (debounce) {
|
||||
*debounce = SENS.sar_touch_status[touch_num-1].touch_pad_debounce;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
IRAM_ATTR esp_err_t touch_pad_read_thresh(touch_pad_t touch_num, uint32_t *thresh_out)
|
||||
{
|
||||
RTC_MODULE_CHECK(touch_num > TOUCH_PAD_NUM0, "Touch pad0 is forbidden", ESP_FAIL);
|
||||
if (thresh_out) {
|
||||
*thresh_out = SENS.touch_thresh[touch_num-1].thresh;
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/* Should be call after clk enable and filter enable. */
|
||||
esp_err_t touch_pad_filter_baseline_reset(touch_pad_t touch_num)
|
||||
{
|
||||
RTC_MODULE_CHECK(touch_num <= TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if(touch_num == TOUCH_PAD_MAX) {
|
||||
SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_MAX;
|
||||
} else {
|
||||
SENS.sar_touch_chn_st.touch_channel_clr = BIT(touch_num);
|
||||
}
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_filter_set_config(touch_filter_config_t filter_info)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_filter_ctrl.touch_filter_mode = filter_info.mode;
|
||||
RTCCNTL.touch_filter_ctrl.touch_debounce = filter_info.debounce_cnt;
|
||||
RTCCNTL.touch_filter_ctrl.touch_hysteresis = filter_info.hysteresis_thr;
|
||||
RTCCNTL.touch_filter_ctrl.touch_noise_thres = filter_info.noise_thr;
|
||||
RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres = filter_info.noise_neg_thr;
|
||||
RTCCNTL.touch_filter_ctrl.touch_neg_noise_limit = filter_info.neg_noise_limit;
|
||||
RTCCNTL.touch_filter_ctrl.touch_jitter_step = filter_info.jitter_step;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
filter_info->mode = RTCCNTL.touch_filter_ctrl.touch_filter_mode;
|
||||
filter_info->debounce_cnt = RTCCNTL.touch_filter_ctrl.touch_debounce;
|
||||
filter_info->hysteresis_thr = RTCCNTL.touch_filter_ctrl.touch_hysteresis;
|
||||
filter_info->noise_thr = RTCCNTL.touch_filter_ctrl.touch_noise_thres;
|
||||
filter_info->noise_neg_thr = RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_filter_start()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_filter_ctrl.touch_filter_en = 1;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_filter_stop()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_filter_ctrl.touch_filter_en = 0;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_denoise_enable()
|
||||
{
|
||||
touch_pad_clear_group_mask(BIT(TOUCH_PAD_NUM0));
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_denoise_en = 1;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_denoise_disable()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_denoise_set_config(touch_pad_denoise_t denoise)
|
||||
{
|
||||
touch_pad_set_cnt_mode(TOUCH_PAD_NUM0, TOUCH_PAD_SLOPE_7);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_ctrl2.touch_refc = denoise.cap_level;
|
||||
RTCCNTL.touch_scan_ctrl.touch_denoise_res = denoise.grade;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise)
|
||||
{
|
||||
if(denoise) {
|
||||
denoise->grade = RTCCNTL.touch_scan_ctrl.touch_denoise_res;
|
||||
denoise->cap_level = RTCCNTL.touch_ctrl2.touch_refc;
|
||||
return ESP_OK;
|
||||
} else {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_denoise_data_get(uint32_t *data)
|
||||
{
|
||||
*data = SENS.sar_touch_status0.touch_denoise_data;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* waterproof function include two setting part: 'shield pad driver' and 'guard ring pad num'
|
||||
* @note waterproof and touch function are mutually exclusive. if config touch14, dont use shield.
|
||||
* @note self-calibration is implemented in hardware.
|
||||
* @note touch_out_ring point to touch0, can disable the guatd ring function ?
|
||||
* @note "touch_bufdrv" should user config ?
|
||||
*/
|
||||
esp_err_t touch_pad_waterproof_set_config(touch_pad_waterproof_t waterproof)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_out_ring = waterproof.guard_ring_pad;
|
||||
RTCCNTL.touch_scan_ctrl.touch_bufdrv = waterproof.shield_driver;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof)
|
||||
{
|
||||
if(waterproof) {
|
||||
waterproof->guard_ring_pad = RTCCNTL.touch_scan_ctrl.touch_out_ring;
|
||||
waterproof->shield_driver = RTCCNTL.touch_scan_ctrl.touch_bufdrv;
|
||||
return ESP_OK;
|
||||
} else {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_waterproof_enable()
|
||||
{
|
||||
touch_pad_clear_group_mask(BIT(TOUCH_PAD_NUM14));
|
||||
touch_pad_io_init(TOUCH_PAD_NUM14);
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 1;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_waterproof_disable()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 0;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* @note approach pad can set three pin.
|
||||
* @note if clear the approach pad, point this pad to touch0 and then reset this channel baseline.
|
||||
* @note the approach thresh is abs value.
|
||||
* @note TODO: add channel reset reg.
|
||||
*/
|
||||
esp_err_t touch_pad_approach_set_config(touch_pad_approach_t approach)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
if(approach.select_pad0) {
|
||||
SENS.sar_touch_conf.touch_approach_pad0 = approach.select_pad0;
|
||||
}
|
||||
if(approach.select_pad1) {
|
||||
SENS.sar_touch_conf.touch_approach_pad1 = approach.select_pad1;
|
||||
}
|
||||
if(approach.select_pad2) {
|
||||
SENS.sar_touch_conf.touch_approach_pad2 = approach.select_pad2;
|
||||
}
|
||||
RTCCNTL.touch_approach.touch_approach_meas_time = approach.means_num;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_approach_get_config(touch_pad_approach_t *approach)
|
||||
{
|
||||
if(approach) {
|
||||
approach->select_pad0 = SENS.sar_touch_conf.touch_approach_pad0;
|
||||
approach->select_pad1 = SENS.sar_touch_conf.touch_approach_pad1;
|
||||
approach->select_pad2 = SENS.sar_touch_conf.touch_approach_pad2;
|
||||
approach->means_num = RTCCNTL.touch_approach.touch_approach_meas_time;
|
||||
return ESP_OK;
|
||||
} else {
|
||||
return ESP_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t touch_pad_approach_get_cnt(uint8_t pad)
|
||||
{
|
||||
uint32_t cnt = 0;
|
||||
if(pad == 0){
|
||||
cnt = SENS.sar_touch_status16.touch_approach_pad0_cnt;
|
||||
} else if(pad == 1) {
|
||||
cnt = SENS.sar_touch_status16.touch_approach_pad1_cnt;
|
||||
} else if(pad == 2) {
|
||||
cnt = SENS.sar_touch_status16.touch_approach_pad2_cnt;
|
||||
} else if(pad == 3) {
|
||||
cnt = SENS.sar_touch_status16.touch_slp_approach_cnt;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
|
||||
/* TODO */
|
||||
esp_err_t touch_pad_approach_disable()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
SENS.sar_touch_conf.touch_approach_pad0 = 0;
|
||||
SENS.sar_touch_conf.touch_approach_pad1 = 0;
|
||||
SENS.sar_touch_conf.touch_approach_pad2 = 0;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/* After touch_clkgate_en = 0, reset the whole of touch module. */
|
||||
esp_err_t touch_pad_reset()
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_ctrl2.touch_reset = 0;
|
||||
RTCCNTL.touch_ctrl2.touch_reset = 1;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/************** sleep pad setting ***********************/
|
||||
|
||||
esp_err_t touch_pad_sleep_pad_config(touch_pad_t pad, uint32_t sleep_thr, uint8_t is_approach)
|
||||
{
|
||||
portENTER_CRITICAL(&rtc_spinlock);
|
||||
RTCCNTL.touch_slp_thres.touch_slp_pad = pad;
|
||||
RTCCNTL.touch_slp_thres.touch_slp_th = sleep_thr;
|
||||
RTCCNTL.touch_slp_thres.touch_slp_approach_en = is_approach?1:0;
|
||||
portEXIT_CRITICAL(&rtc_spinlock);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get sleep touch pad baseline data.
|
||||
*
|
||||
* @param baseline
|
||||
*/
|
||||
void touch_sleep_baseline_get(uint32_t *baseline)
|
||||
{
|
||||
*baseline = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_BASELINE);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get sleep touch pad debounce data.
|
||||
*
|
||||
* @param debounce
|
||||
*/
|
||||
void touch_sleep_debounce_get(uint32_t *debounce)
|
||||
{
|
||||
*debounce = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_DEBOUNCE);
|
||||
}
|
||||
|
||||
/**
|
||||
* Get sleep touch pad approach cnt data.
|
||||
*
|
||||
* @param approach_cnt
|
||||
*/
|
||||
void touch_sleep_approach_cnt_get(uint32_t *approach_cnt)
|
||||
{
|
||||
*approach_cnt = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS16_REG, SENS_TOUCH_SLP_APPROACH_CNT);
|
||||
}
|
||||
|
||||
esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num)
|
||||
{
|
||||
uint32_t touch_mask = SENS.sar_touch_chn_st.touch_pad_active;
|
||||
*pad_num = __builtin_ffs(touch_mask) - 1;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
#endif
|
@ -406,7 +406,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status()
|
||||
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
|
||||
return TOUCH_PAD_MAX;
|
||||
}
|
||||
uint32_t touch_mask = REG_GET_FIELD(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN);
|
||||
uint32_t touch_mask = REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL1_REG, RTC_CNTL_TOUCH_MEAS_NUM);
|
||||
assert(touch_mask != 0 && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
|
||||
return (touch_pad_t) (__builtin_ffs(touch_mask) - 1);
|
||||
}
|
||||
|
@ -336,7 +336,7 @@ extern "C" {
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_S 14
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
|
||||
/*description: CK8M wait cycles in slow_clk_rtc*/
|
||||
#define RTC_CNTL_CK8M_WAIT 0x000000FF
|
||||
@ -1451,7 +1451,7 @@ extern "C" {
|
||||
#define RTC_CNTL_DBG_ATTEN_V 0xF
|
||||
#define RTC_CNTL_DBG_ATTEN_S 22
|
||||
/* reserved for driver to check */
|
||||
#define RTC_CNTL_DBG_ATTEN_DEFAULT 3
|
||||
#define RTC_CNTL_DBG_ATTEN_DEFAULT 15
|
||||
|
||||
#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084)
|
||||
/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
|
||||
|
@ -1,9 +1,9 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
@ -64,37 +64,34 @@ typedef volatile struct {
|
||||
} slp_timer1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 30;
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/
|
||||
uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/
|
||||
uint32_t timer_sys_rst: 1; /*enable to record system reset time*/
|
||||
uint32_t valid: 1; /*To indicate the register is updated*/
|
||||
uint32_t update: 1; /*Set 1: to update register with RTC timer*/
|
||||
};
|
||||
uint32_t val;
|
||||
} time_update;
|
||||
uint32_t time0; /*RTC timer low 32 bits*/
|
||||
uint32_t time_low0; /*RTC timer low 32 bits*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t time_hi: 16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} time1;
|
||||
} time_high0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18;
|
||||
uint32_t cocpu_wakeup: 1; /*riscV cocpu wake up register*/
|
||||
uint32_t cocpu_wakeup_force_en: 1; /*riscV cocpu force wake up*/
|
||||
uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/
|
||||
uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/
|
||||
uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/
|
||||
uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/
|
||||
uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/
|
||||
uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/
|
||||
uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t sdio_active_ind: 1; /*SDIO active indication*/
|
||||
uint32_t slp_wakeup: 1; /*leep wakeup bit*/
|
||||
uint32_t slp_reject: 1; /*leep reject bit*/
|
||||
uint32_t sleep_en: 1; /*sleep enable bit*/
|
||||
uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/
|
||||
uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/
|
||||
uint32_t reserved2: 20;
|
||||
uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/
|
||||
uint32_t reserved23: 5;
|
||||
uint32_t sdio_active_ind: 1; /*SDIO active indication*/
|
||||
uint32_t slp_wakeup: 1; /*leep wakeup bit*/
|
||||
uint32_t slp_reject: 1; /*leep reject bit*/
|
||||
uint32_t sleep_en: 1; /*sleep enable bit*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state0;
|
||||
@ -136,10 +133,10 @@ typedef volatile struct {
|
||||
} timer4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ulp_cp_subtimer_prediv: 8;
|
||||
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
|
||||
uint32_t rtcmem_wait_timer: 9;
|
||||
uint32_t rtcmem_powerup_timer: 7;
|
||||
uint32_t reserved0: 8;
|
||||
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
|
||||
uint32_t rtcmem_wait_timer: 9;
|
||||
uint32_t rtcmem_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer5;
|
||||
@ -153,9 +150,7 @@ typedef volatile struct {
|
||||
} timer6;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 19;
|
||||
uint32_t pkdet_cal_force_en: 2; /*pkdet force option*/
|
||||
uint32_t pwdet_cal_force_en: 2; /*pwdet force option*/
|
||||
uint32_t reserved0: 23;
|
||||
uint32_t plla_force_pd: 1; /*PLLA force power down*/
|
||||
uint32_t plla_force_pu: 1; /*PLLA force power up*/
|
||||
uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/
|
||||
@ -180,95 +175,130 @@ typedef volatile struct {
|
||||
} reset_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wakeup_cause: 12; /*wakeup cause*/
|
||||
uint32_t rtc_wakeup_ena: 12; /*wakeup enable bitmap*/
|
||||
uint32_t wakeup_cause: 15; /*wakeup cause*/
|
||||
uint32_t rtc_wakeup_ena: 15; /*wakeup enable bitmap*/
|
||||
uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/
|
||||
uint32_t reserved25: 7;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wakeup_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/
|
||||
uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/
|
||||
uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/
|
||||
uint32_t rtc_touch: 1; /*enable touch interrupt*/
|
||||
uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/
|
||||
uint32_t rtc_tsens: 1; /*enable tsens interrupt*/
|
||||
uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/
|
||||
uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/
|
||||
uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/
|
||||
uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/
|
||||
uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/
|
||||
uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/
|
||||
uint32_t rtc_touch_inactive: 1; /*enable touch inactive interrupt*/
|
||||
uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/
|
||||
uint32_t rtc_tsens: 1; /*enable tsens interrupt*/
|
||||
uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/
|
||||
uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/
|
||||
uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*enable cocpu trap interrupt*/
|
||||
uint32_t rtc_cocpu_trap: 1;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt raw*/
|
||||
uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/
|
||||
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/
|
||||
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/
|
||||
uint32_t rtc_touch: 1; /*touch interrupt raw*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/
|
||||
uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/
|
||||
uint32_t rtc_tsens: 1; /*tsens interrupt raw*/
|
||||
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/
|
||||
uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt raw*/
|
||||
uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/
|
||||
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/
|
||||
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/
|
||||
uint32_t rtc_touch_done: 1; /*touch interrupt raw*/
|
||||
uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/
|
||||
uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt raw*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/
|
||||
uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/
|
||||
uint32_t rtc_tsens: 1; /*tsens interrupt raw*/
|
||||
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/
|
||||
uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/
|
||||
uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt raw*/
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt state*/
|
||||
uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/
|
||||
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/
|
||||
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/
|
||||
uint32_t rtc_touch: 1; /*touch interrupt state*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/
|
||||
uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/
|
||||
uint32_t rtc_tsens: 1; /*tsens interrupt state*/
|
||||
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/
|
||||
uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt state*/
|
||||
uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/
|
||||
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/
|
||||
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/
|
||||
uint32_t rtc_touch_done: 1; /*touch done interrupt state*/
|
||||
uint32_t rtc_touch_active: 1; /*touch active interrupt state*/
|
||||
uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt state*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/
|
||||
uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/
|
||||
uint32_t rtc_tsens: 1; /*tsens interrupt state*/
|
||||
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/
|
||||
uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/
|
||||
uint32_t rtc_swd: 1; /*super watch dog interrupt state*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt state*/
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/
|
||||
uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/
|
||||
uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/
|
||||
uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/
|
||||
uint32_t rtc_touch: 1; /*Clear touch interrupt state*/
|
||||
uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/
|
||||
uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/
|
||||
uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/
|
||||
uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/
|
||||
uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/
|
||||
uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/
|
||||
uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/
|
||||
uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/
|
||||
uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/
|
||||
uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/
|
||||
uint32_t rtc_touch_inactive: 1; /*Clear touch inactive interrupt state*/
|
||||
uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/
|
||||
uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/
|
||||
uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/
|
||||
uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/
|
||||
uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/
|
||||
uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*Clear cocpu trap interrupt state*/
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t store[4]; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 30;
|
||||
uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/
|
||||
uint32_t ctr_en: 1;
|
||||
uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/
|
||||
uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/
|
||||
uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/
|
||||
uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/
|
||||
uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/
|
||||
uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/
|
||||
uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/
|
||||
uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/
|
||||
uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/
|
||||
uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/
|
||||
uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/
|
||||
uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/
|
||||
uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/
|
||||
uint32_t dac_xtal_32k: 6; /*DAC_XTAL_32K*/
|
||||
uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/
|
||||
uint32_t reserved24: 6;
|
||||
uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/
|
||||
uint32_t ctr_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_xtl_conf;
|
||||
@ -282,12 +312,10 @@ typedef volatile struct {
|
||||
} ext_wakeup_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 24;
|
||||
uint32_t gpio_reject_en: 1; /*enable GPIO reject*/
|
||||
uint32_t sdio_reject_en: 1; /*enable SDIO reject*/
|
||||
uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/
|
||||
uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/
|
||||
uint32_t reject_cause: 4;
|
||||
uint32_t reject_cause: 15; /*sleep reject cause*/
|
||||
uint32_t rtc_sleep_reject_ena:15; /*sleep reject enable*/
|
||||
uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/
|
||||
uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_reject_conf;
|
||||
@ -331,12 +359,7 @@ typedef volatile struct {
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 14;
|
||||
uint32_t dbias_xtal_32k: 2; /*DBIAS_XTAL_32K*/
|
||||
uint32_t dres_xtal_32k: 2; /*DRES_XTAL_32K*/
|
||||
uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/
|
||||
uint32_t dac_xtal_32k: 2; /*DAC_XTAL_32K*/
|
||||
uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/
|
||||
uint32_t reserved0: 22;
|
||||
uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div then set vld to actually switch the clk*/
|
||||
uint32_t rtc_ana_clk_div: 8;
|
||||
uint32_t slow_clk_next_edge: 1;
|
||||
@ -345,22 +368,30 @@ typedef volatile struct {
|
||||
} slow_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 21;
|
||||
uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
|
||||
uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/
|
||||
uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
|
||||
uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/
|
||||
uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t xpd_sdio: 1;
|
||||
uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/
|
||||
uint32_t reserved8: 1;
|
||||
uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current set to 3 after several us.*/
|
||||
uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/
|
||||
uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k*/
|
||||
uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/
|
||||
uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
|
||||
uint32_t sdio_modecurlim: 1; /*select current limit mode*/
|
||||
uint32_t sdio_encurlim: 1; /*enable current limit*/
|
||||
uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
|
||||
uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/
|
||||
uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
|
||||
uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/
|
||||
uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t xpd_sdio: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 24;
|
||||
uint32_t dbg_atten: 2; /*DBG_ATTEN*/
|
||||
uint32_t reserved0: 22;
|
||||
uint32_t dbg_atten: 4; /*DBG_ATTEN*/
|
||||
uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/
|
||||
uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/
|
||||
uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/
|
||||
@ -408,14 +439,8 @@ typedef volatile struct {
|
||||
uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/
|
||||
uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/
|
||||
uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/
|
||||
uint32_t rtc_pad_autohold: 1; /*read only register to indicate rtc pad auto-hold status*/
|
||||
uint32_t clr_rtc_pad_autohold: 1; /*wtite only register to clear rtc pad auto-hold*/
|
||||
uint32_t rtc_pad_autohold_en: 1; /*rtc pad enable auto-hold*/
|
||||
uint32_t rtc_pad_force_noiso: 1; /*rtc pad force no ISO*/
|
||||
uint32_t rtc_pad_force_iso: 1; /*rtc pad force ISO*/
|
||||
uint32_t rtc_pad_force_unhold: 1; /*rtc pad force un-hold*/
|
||||
uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/
|
||||
uint32_t reserved28: 4;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pwc;
|
||||
@ -487,15 +512,14 @@ typedef volatile struct {
|
||||
} dig_iso;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/
|
||||
uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/
|
||||
uint32_t pause_in_slp: 1; /*pause WDT in sleep*/
|
||||
uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/
|
||||
uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/
|
||||
uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/
|
||||
uint32_t sys_reset_length: 3; /*system reset counter length*/
|
||||
uint32_t cpu_reset_length: 3; /*CPU reset counter length*/
|
||||
uint32_t level_int_en: 1; /*N/A*/
|
||||
uint32_t edge_int_en: 1; /*N/A*/
|
||||
uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
|
||||
uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
|
||||
uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/
|
||||
@ -518,7 +542,22 @@ typedef volatile struct {
|
||||
uint32_t wdt_wprotect; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 29;
|
||||
uint32_t swd_reset_flag: 1; /*swd reset flag*/
|
||||
uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/
|
||||
uint32_t reserved2: 16;
|
||||
uint32_t swd_signal_width:10; /*adjust signal width send to swd*/
|
||||
uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/
|
||||
uint32_t swd_feed: 1; /*Sw feed swd*/
|
||||
uint32_t swd_disable: 1; /*disabel SWD*/
|
||||
uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/
|
||||
};
|
||||
uint32_t val;
|
||||
} swd_conf;
|
||||
uint32_t swd_wprotect; /*swd write protect*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 28;
|
||||
uint32_t ent_tsens: 1; /*ENT_TSENS*/
|
||||
uint32_t ent_rtc: 1; /*ENT_RTC*/
|
||||
uint32_t dtest_rtc: 2;
|
||||
};
|
||||
@ -547,14 +586,14 @@ typedef volatile struct {
|
||||
uint32_t xpd_wifi: 1; /*wifi wrap power down*/
|
||||
uint32_t dig_iso: 1; /*digital wrap iso*/
|
||||
uint32_t xpd_dig: 1; /*digital wrap power down*/
|
||||
uint32_t rtc_touch_start: 1; /*touch should start to work*/
|
||||
uint32_t rtc_touch_state_start: 1; /*touch should start to work*/
|
||||
uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/
|
||||
uint32_t rtc_touch_slp: 1; /*touch is in sleep state*/
|
||||
uint32_t rtc_touch_done: 1; /*touch is done*/
|
||||
uint32_t rtc_cocpu_start: 1; /*ulp/cocpu should start to work*/
|
||||
uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/
|
||||
uint32_t rtc_touch_state_done: 1; /*touch is done*/
|
||||
uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/
|
||||
uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/
|
||||
uint32_t rtc_cocpu_slp: 1; /*ulp/cocpu is in sleep state*/
|
||||
uint32_t rtc_cocpu_done: 1; /*ulp/cocpu is done*/
|
||||
uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/
|
||||
uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/
|
||||
uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/
|
||||
uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/
|
||||
uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/
|
||||
@ -573,62 +612,216 @@ typedef volatile struct {
|
||||
uint32_t diag0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc1_hold_force: 1;
|
||||
uint32_t adc2_hold_force: 1;
|
||||
uint32_t pdac1_hold_force: 1;
|
||||
uint32_t pdac2_hold_force: 1;
|
||||
uint32_t sense1_hold_force: 1;
|
||||
uint32_t sense2_hold_force: 1;
|
||||
uint32_t sense3_hold_force: 1;
|
||||
uint32_t sense4_hold_force: 1;
|
||||
uint32_t touch_pad0_hold_force: 1;
|
||||
uint32_t touch_pad1_hold_force: 1;
|
||||
uint32_t touch_pad2_hold_force: 1;
|
||||
uint32_t touch_pad3_hold_force: 1;
|
||||
uint32_t touch_pad4_hold_force: 1;
|
||||
uint32_t touch_pad5_hold_force: 1;
|
||||
uint32_t touch_pad6_hold_force: 1;
|
||||
uint32_t touch_pad7_hold_force: 1;
|
||||
uint32_t x32p_hold_force: 1;
|
||||
uint32_t x32n_hold_force: 1;
|
||||
uint32_t reserved18: 14;
|
||||
uint32_t touch_pad0_hold: 1;
|
||||
uint32_t touch_pad1_hold: 1;
|
||||
uint32_t touch_pad2_hold: 1;
|
||||
uint32_t touch_pad3_hold: 1;
|
||||
uint32_t touch_pad4_hold: 1;
|
||||
uint32_t touch_pad5_hold: 1;
|
||||
uint32_t touch_pad6_hold: 1;
|
||||
uint32_t touch_pad7_hold: 1;
|
||||
uint32_t touch_pad8_hold: 1;
|
||||
uint32_t touch_pad9_hold: 1;
|
||||
uint32_t touch_pad10_hold: 1;
|
||||
uint32_t touch_pad11_hold: 1;
|
||||
uint32_t touch_pad12_hold: 1;
|
||||
uint32_t touch_pad13_hold: 1;
|
||||
uint32_t touch_pad14_hold: 1;
|
||||
uint32_t x32p_hold: 1;
|
||||
uint32_t x32n_hold: 1;
|
||||
uint32_t pdac1_hold: 1;
|
||||
uint32_t pdac2_hold: 1;
|
||||
uint32_t rtc_pad19_hold: 1;
|
||||
uint32_t rtc_pad20_hold: 1;
|
||||
uint32_t rtc_pad21_hold: 1;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} hold_force;
|
||||
} pad_hold;
|
||||
uint32_t dig_pad_hold; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/
|
||||
uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/
|
||||
uint32_t status_clr: 1; /*clear ext wakeup1 status*/
|
||||
uint32_t reserved19: 13;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status: 18; /*ext wakeup1 status*/
|
||||
uint32_t reserved18: 14;
|
||||
uint32_t status: 22; /*ext wakeup1 status*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup1_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 14;
|
||||
uint32_t reserved0: 4;
|
||||
uint32_t int_wait: 10; /*brown out interrupt wait cycles*/
|
||||
uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/
|
||||
uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/
|
||||
uint32_t rst_wait: 10; /*brown out reset wait cycles*/
|
||||
uint32_t rst_ena: 1; /*enable brown out reset*/
|
||||
uint32_t thres: 3; /*brown out threshold*/
|
||||
uint32_t reserved27: 2;
|
||||
uint32_t cnt_clr: 1; /*clear brown out counter*/
|
||||
uint32_t ena: 1; /*enable brown out*/
|
||||
uint32_t det: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} brown_out;
|
||||
uint32_t reserved_3c;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t time_low1; /*RTC timer low 32 bits*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} time_high1;
|
||||
uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/
|
||||
uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/
|
||||
uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time 32k is regarded as dead*/
|
||||
uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this it is regarded as stable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal32k_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ulp_cp_pc_init: 11; /*ULP-coprocessor PC initial address*/
|
||||
uint32_t reserved11: 1;
|
||||
uint32_t ulp_cp_timer_slp_cycle:16; /*sleep cycles for ULP-coprocessor timer*/
|
||||
uint32_t reserved28: 1;
|
||||
uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/
|
||||
uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/
|
||||
uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ulp_cp_timer;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ulp_cp_mem_addr_init: 11;
|
||||
uint32_t ulp_cp_mem_addr_size: 11;
|
||||
uint32_t ulp_cp_mem_offst_clr: 1;
|
||||
uint32_t reserved23: 5;
|
||||
uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/
|
||||
uint32_t ulp_cp_reset: 1; /*ulp coprocessor clk software reset*/
|
||||
uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW*/
|
||||
uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ulp_cp_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cocpu_clk_fo: 1; /*cocpu clk force on*/
|
||||
uint32_t cocpu_start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/
|
||||
uint32_t cocpu_start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/
|
||||
uint32_t cocpu_shut: 1; /*to shut cocpu*/
|
||||
uint32_t cocpu_shut_2_clk_dis: 6; /*time from shut cocpu to disable clk*/
|
||||
uint32_t cocpu_shut_reset_en: 1; /*to reset cocpu*/
|
||||
uint32_t cocpu_sel: 1; /*1: old ULP 0: new riscV*/
|
||||
uint32_t cocpu_done_force: 1; /*1: select riscv done 0: select ulp done*/
|
||||
uint32_t cocpu_done: 1; /*done signal used by riscv to control timer.*/
|
||||
uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} cocpu_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/
|
||||
uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 2;
|
||||
uint32_t touch_drange: 2; /*TOUCH_DRANGE*/
|
||||
uint32_t touch_drefl: 2; /*TOUCH_DREFL*/
|
||||
uint32_t touch_drefh: 2; /*TOUCH_DREFH*/
|
||||
uint32_t touch_xpd_bias: 1; /*TOUCH_XPD_BIAS*/
|
||||
uint32_t touch_refc: 3; /*TOUCH pad0 reference cap*/
|
||||
uint32_t reserved12: 1;
|
||||
uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/
|
||||
uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/
|
||||
uint32_t touch_start_en: 1; /*1: start touch fsm*/
|
||||
uint32_t touch_start_force: 1; /*1: to start touch fsm by SW*/
|
||||
uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
|
||||
uint32_t touch_slp_cyc_div: 2; /*when a touch pad is active sleep cycle could be divided by this number*/
|
||||
uint32_t reserved27: 2;
|
||||
uint32_t touch_reset: 1; /*reset upgrade touch*/
|
||||
uint32_t touch_clk_fo: 1; /*touch clock force on*/
|
||||
uint32_t touch_clkgate_en: 1; /*touch clock enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_denoise_res: 2; /*De-noise resolution: 12/10/8/4 bit*/
|
||||
uint32_t touch_denoise_en: 1; /*touch pad0 will be used to de-noise*/
|
||||
uint32_t reserved3: 5;
|
||||
uint32_t touch_inactive_connection: 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/
|
||||
uint32_t touch_shield_pad_en: 1; /*touch pad14 will be used as shield*/
|
||||
uint32_t touch_scan_pad_map: 15; /*touch scan mode pad enable map*/
|
||||
uint32_t touch_bufdrv: 3; /*touch7 buffer driver strength*/
|
||||
uint32_t touch_out_ring: 4; /*select out ring pad*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_scan_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/
|
||||
uint32_t reserved22: 4;
|
||||
uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/
|
||||
uint32_t touch_slp_pad: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_slp_thres;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 23;
|
||||
uint32_t touch_slp_channel_clr: 1; /*clear touch slp channel*/
|
||||
uint32_t touch_approach_meas_time: 8; /*approach pads total meas times*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_approach;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 12;
|
||||
uint32_t touch_jitter_step: 4; /*touch jitter step*/
|
||||
uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/
|
||||
uint32_t touch_neg_noise_thres: 2;
|
||||
uint32_t touch_noise_thres: 2;
|
||||
uint32_t touch_hysteresis: 2;
|
||||
uint32_t touch_debounce: 3; /*debounce counter*/
|
||||
uint32_t touch_filter_mode: 2; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
|
||||
uint32_t touch_filter_en: 1; /*touch filter enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_filter_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usb_vrefh: 2;
|
||||
uint32_t usb_vrefl: 2;
|
||||
uint32_t usb_vref_override: 1;
|
||||
uint32_t usb_pad_pull_override: 1;
|
||||
uint32_t usb_dp_pullup: 1;
|
||||
uint32_t usb_dp_pulldown: 1;
|
||||
uint32_t usb_dm_pullup: 1;
|
||||
uint32_t usb_dm_pulldown: 1;
|
||||
uint32_t usb_pullup_value: 1;
|
||||
uint32_t usb_pad_enable_override: 1;
|
||||
uint32_t usb_pad_enable: 1;
|
||||
uint32_t usb_txm: 1;
|
||||
uint32_t usb_txp: 1;
|
||||
uint32_t usb_tx_en: 1;
|
||||
uint32_t usb_tx_en_override: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -1,9 +1,9 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
@ -20,82 +20,143 @@ extern "C" {
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_clk_div: 8; /*clock divider*/
|
||||
uint32_t sar1_sample_cycle: 8; /*sample cycles for SAR ADC1*/
|
||||
uint32_t sar1_sample_bit: 2; /*00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width*/
|
||||
uint32_t sar1_clk_div: 8; /*clock divider*/
|
||||
uint32_t sar1_sample_cycle: 8; /*sample cycles for SAR ADC1*/
|
||||
uint32_t sar1_sample_bit: 2; /*00: for 9-bit width*/
|
||||
uint32_t sar1_clk_gated: 1;
|
||||
uint32_t sar1_sample_num: 8;
|
||||
uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/
|
||||
uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/
|
||||
uint32_t reserved29: 3;
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/
|
||||
uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_read_ctrl;
|
||||
uint32_t sar_read_status1; /**/
|
||||
} sar_reader1_ctrl;
|
||||
uint32_t sar_reader1_status; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_bit_width: 2; /*00: 9 bit*/
|
||||
uint32_t sar1_stop: 1; /*stop SAR ADC1 conversion*/
|
||||
uint32_t reserved3: 21;
|
||||
uint32_t force_xpd_amp: 2;
|
||||
uint32_t amp_rst_fb_force: 2;
|
||||
uint32_t amp_short_ref_force: 2;
|
||||
uint32_t amp_short_ref_gnd_force: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/
|
||||
uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/
|
||||
uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/
|
||||
uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/
|
||||
uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/
|
||||
uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_mux;
|
||||
uint32_t sar_atten1; /*2-bit attenuation for each pad*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_amp_wait1:16;
|
||||
uint32_t sar_amp_wait2:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_wait1;
|
||||
} sar_amp_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_amp_wait3: 16;
|
||||
uint32_t force_xpd_amp: 2;
|
||||
uint32_t force_xpd_sar: 2;
|
||||
uint32_t sar2_rstb_wait: 8;
|
||||
uint32_t reserved28: 4;
|
||||
uint32_t sar1_dac_xpd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_amp_fsm_idle: 1;
|
||||
uint32_t amp_rst_fb_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_gnd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_fsm_idle: 1;
|
||||
uint32_t sar_rstb_fsm_idle: 1;
|
||||
uint32_t reserved7: 9;
|
||||
uint32_t sar_amp_wait3: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_wait2;
|
||||
} sar_amp_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm: 4;
|
||||
uint32_t xpd_sar_amp_fsm: 4;
|
||||
uint32_t amp_rst_fb_fsm: 4;
|
||||
uint32_t amp_short_ref_fsm: 4;
|
||||
uint32_t amp_short_ref_gnd_fsm: 4;
|
||||
uint32_t xpd_sar_fsm: 4;
|
||||
uint32_t sar_rstb_fsm: 4;
|
||||
uint32_t sar2_xpd_wait: 8;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_ctrl;
|
||||
uint32_t sar_read_status2; /**/
|
||||
uint32_t ulp_cp_sleep_cyc0; /*sleep cycles for ULP-coprocessor timer*/
|
||||
uint32_t ulp_cp_sleep_cyc1; /**/
|
||||
uint32_t ulp_cp_sleep_cyc2; /**/
|
||||
uint32_t ulp_cp_sleep_cyc3; /**/
|
||||
uint32_t ulp_cp_sleep_cyc4; /**/
|
||||
} sar_amp_ctrl3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_bit_width: 2; /*00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/
|
||||
uint32_t sar2_bit_width: 2; /*00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/
|
||||
uint32_t sar2_en_test: 1; /*SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/
|
||||
uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT PA power detector capacitance tuning.*/
|
||||
uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/
|
||||
uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1*/
|
||||
uint32_t sarclk_en: 1;
|
||||
uint32_t pc_init: 11; /*initialized PC for ULP-coprocessor*/
|
||||
uint32_t sar2_stop: 1; /*stop SAR ADC2 conversion*/
|
||||
uint32_t sar1_stop: 1; /*stop SAR ADC1 conversion*/
|
||||
uint32_t sar2_pwdet_en: 1; /*N/A*/
|
||||
uint32_t reserved25: 7;
|
||||
uint32_t sar2_clk_div: 8; /*clock divider*/
|
||||
uint32_t sar2_sample_cycle: 8; /*sample cycles for SAR ADC2*/
|
||||
uint32_t sar2_sample_bit: 2; /*00: for 9-bit width*/
|
||||
uint32_t sar2_clk_gated: 1;
|
||||
uint32_t sar2_sample_num: 8;
|
||||
uint32_t reserved27: 2;
|
||||
uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/
|
||||
uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_start_force;
|
||||
} sar_reader2_ctrl;
|
||||
uint32_t sar_reader2_status; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mem_wr_addr_init: 11;
|
||||
uint32_t mem_wr_addr_size: 11;
|
||||
uint32_t rtc_mem_wr_offst_clr: 1;
|
||||
uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/
|
||||
uint32_t reserved24: 8;
|
||||
uint32_t sar2_bit_width: 2; /*00: 9 bit*/
|
||||
uint32_t sar2_stop: 1; /*stop SAR ADC2 conversion*/
|
||||
uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/
|
||||
uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/
|
||||
uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/
|
||||
uint32_t sar2_rstb_force: 2;
|
||||
uint32_t sar2_standby_wait: 8;
|
||||
uint32_t sar2_rstb_wait: 8;
|
||||
uint32_t sar2_xpd_wait: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_mem_wr_ctrl;
|
||||
uint32_t sar_atten1; /*2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/
|
||||
uint32_t sar_atten2; /*2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/
|
||||
} sar_meas2_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/
|
||||
uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/
|
||||
uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/
|
||||
uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/
|
||||
uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/
|
||||
uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 28;
|
||||
uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/
|
||||
uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_mux;
|
||||
uint32_t sar_atten2; /*2-bit attenuation for each pad*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 23;
|
||||
uint32_t sar2_dref: 3; /*Adjust saradc2 offset*/
|
||||
uint32_t sar1_dref: 3; /*Adjust saradc1 offset*/
|
||||
uint32_t force_xpd_sar: 2;
|
||||
uint32_t sarclk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_power_xpd_sar;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr1: 11;
|
||||
@ -117,9 +178,7 @@ typedef volatile struct {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr5:11;
|
||||
uint32_t i2c_slave_addr4:11;
|
||||
uint32_t tsens_out: 8; /*temperature sensor data out*/
|
||||
uint32_t tsens_rdy_out: 1; /*indicate temperature sensor out ready*/
|
||||
uint32_t reserved31: 1;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr3;
|
||||
@ -127,236 +186,339 @@ typedef volatile struct {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr7:11;
|
||||
uint32_t i2c_slave_addr6:11;
|
||||
uint32_t i2c_rdata: 8; /*I2C read data*/
|
||||
uint32_t i2c_done: 1; /*indicate I2C done*/
|
||||
uint32_t reserved31: 1;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_xpd_wait: 12;
|
||||
uint32_t tsens_xpd_force: 1;
|
||||
uint32_t tsens_clk_inv: 1;
|
||||
uint32_t tsens_clk_gated: 1;
|
||||
uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/
|
||||
uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/
|
||||
uint32_t tsens_power_up: 1; /*temperature sensor power up*/
|
||||
uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW 0: by FSM*/
|
||||
uint32_t tsens_dump_out: 1; /*temperature sensor dump out only active when reg_tsens_power_up_force = 1*/
|
||||
uint32_t tsens_dos: 4; /*Temperature sensor calibration bits*/
|
||||
uint32_t tsens_force: 1; /*1: select saradc_reg 0: select efuse*/
|
||||
uint32_t tsens_out: 8; /*temperature sensor data out*/
|
||||
uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/
|
||||
uint32_t reserved9: 3;
|
||||
uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/
|
||||
uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/
|
||||
uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/
|
||||
uint32_t tsens_power_up: 1; /*temperature sensor power up*/
|
||||
uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/
|
||||
uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/
|
||||
uint32_t tsens_diz: 1; /*ADC input short*/
|
||||
uint32_t tsens_div_chop: 2; /*0 for steady phase 0 1 for steady phase 1 2 for chopping with ½ frequency of TSENS_CK 3 for chopping with ¼*/
|
||||
uint32_t tsens_dac: 4; /*Temperature sensor offset dac. 15 for 0 offset 5 for -2 7 for -1 11 for 1 10 for 2*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_i2c_ctrl: 28; /*I2C control data only active when reg_sar_i2c_start_force = 1*/
|
||||
uint32_t sar_i2c_start: 1; /*start I2C only active when reg_sar_i2c_start_force = 1*/
|
||||
uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW 0: I2C started by FSM*/
|
||||
uint32_t tsens_xpd_wait: 12;
|
||||
uint32_t tsens_xpd_force: 2;
|
||||
uint32_t tsens_clk_inv: 1;
|
||||
uint32_t tsens_clkgate_en: 1; /*temperature sensor clock enable*/
|
||||
uint32_t tsens_reset: 1; /*temperature sensor reset*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_i2c_ctrl: 28; /*I2C control data*/
|
||||
uint32_t sar_i2c_start: 1; /*start I2C*/
|
||||
uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_i2c_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/
|
||||
uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/
|
||||
uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1*/
|
||||
uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor*/
|
||||
uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/
|
||||
uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor*/
|
||||
uint32_t touch_outen: 15; /*touch controller output enable*/
|
||||
uint32_t touch_status_clr: 1; /*clear all touch active status*/
|
||||
uint32_t reserved16: 4;
|
||||
uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/
|
||||
uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/
|
||||
uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_start1;
|
||||
} sar_touch_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_meas_delay:16; /*the meas length (in 8MHz)*/
|
||||
uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
|
||||
uint32_t touch_out_sel: 1; /*1: when the counter is greater then the threshold the touch pad is considered as “touched” 0: when the counter is less than the threshold the touch pad is considered as “touched”*/
|
||||
uint32_t touch_out_1en: 1; /*1: wakeup interrupt is generated if SET1 is “touched” 0: wakeup interrupt is generated only if SET1 & SET2 is both “touched”*/
|
||||
uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
|
||||
uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
|
||||
uint32_t reserved28: 4;
|
||||
uint32_t thresh: 22; /*Finger threshold for touch pad 1*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_ctrl1;
|
||||
} touch_thresh[14];
|
||||
union {
|
||||
struct {
|
||||
uint32_t l_thresh: 16; /*the threshold for touch pad 1*/
|
||||
uint32_t h_thresh: 16; /*the threshold for touch pad 0*/
|
||||
uint32_t meas_out: 22; /*the counter for touch pad 1*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_thresh[5];
|
||||
} touch_meas[15];
|
||||
union {
|
||||
struct {
|
||||
uint32_t l_val: 16; /*the counter for touch pad 1*/
|
||||
uint32_t h_val: 16; /*the counter for touch pad 0*/
|
||||
uint32_t touch_pad_active: 15; /*touch active status*/
|
||||
uint32_t touch_channel_clr:15; /*Clear touch channel*/
|
||||
uint32_t reserved30: 1;
|
||||
uint32_t touch_meas_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_meas[5];
|
||||
} sar_touch_chn_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_meas_en: 10; /*10-bit register to indicate which pads are “touched”*/
|
||||
uint32_t touch_meas_done: 1; /*fsm set 1 to indicate touch touch meas is done*/
|
||||
uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers*/
|
||||
uint32_t touch_start_en: 1; /*1: start touch fsm valid when reg_touch_start_force is set*/
|
||||
uint32_t touch_start_force: 1; /*1: to start touch fsm by SW 0: to start touch fsm by timer*/
|
||||
uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/
|
||||
uint32_t touch_meas_en_clr: 1; /*to clear reg_touch_meas_en*/
|
||||
uint32_t reserved31: 1;
|
||||
uint32_t touch_denoise_data:22; /*the counter for touch pad 0*/
|
||||
uint32_t touch_scan_curr: 4;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_ctrl2;
|
||||
uint32_t reserved_88;
|
||||
} sar_touch_status0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad_worken:10; /*Bitmap defining the working set during the measurement.*/
|
||||
uint32_t touch_pad_outen2:10; /*Bitmap defining SET2 for generating wakeup interrupt. SET2 is “touched” only if at least one of touch pad in SET2 is “touched”.*/
|
||||
uint32_t touch_pad_outen1:10; /*Bitmap defining SET1 for generating wakeup interrupt. SET1 is “touched” only if at least one of touch pad in SET1 is “touched”.*/
|
||||
uint32_t reserved30: 2;
|
||||
uint32_t touch_pad_baseline: 22;
|
||||
uint32_t reserved22: 7;
|
||||
uint32_t touch_pad_debounce: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_enable;
|
||||
} sar_touch_status[14];
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad2_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad2_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status2;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad3_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad3_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status3;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad4_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad4_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status4;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad5_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad5_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status5;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad6_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad6_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status6;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad7_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad7_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status7;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad8_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad8_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status8;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad9_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad9_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status9;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad10_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad10_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status10;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad11_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad11_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status11;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad12_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad12_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status12;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad13_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad13_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status13;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_pad14_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_pad14_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status14;
|
||||
// union {
|
||||
// struct {
|
||||
// uint32_t touch_slp_baseline:22;
|
||||
// uint32_t reserved22: 7;
|
||||
// uint32_t touch_slp_debounce: 3;
|
||||
// };
|
||||
// uint32_t val;
|
||||
// } sar_touch_status15;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_meas_raw:10; /*touch sensor raw result*/
|
||||
uint32_t reserved10: 22;
|
||||
uint32_t touch_approach_pad2_cnt: 8;
|
||||
uint32_t touch_approach_pad1_cnt: 8;
|
||||
uint32_t touch_approach_pad0_cnt: 8;
|
||||
uint32_t touch_slp_approach_cnt: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_ctrl3;
|
||||
} sar_touch_status16;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_clk_div: 8; /*clock divider*/
|
||||
uint32_t sar2_sample_cycle: 8; /*sample cycles for SAR ADC2*/
|
||||
uint32_t sar2_sample_bit: 2; /*00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width*/
|
||||
uint32_t sar2_clk_gated: 1;
|
||||
uint32_t sar2_sample_num: 8;
|
||||
uint32_t sar2_pwdet_force: 1;
|
||||
uint32_t sar2_dig_force: 1; /*1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL*/
|
||||
uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_read_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/
|
||||
uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/
|
||||
uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1*/
|
||||
uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor*/
|
||||
uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/
|
||||
uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_start2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_fstep: 16; /*frequency step for CW generator can be used to adjust the frequency*/
|
||||
uint32_t sw_tone_en: 1; /*1: enable CW generator 0: disable CW generator*/
|
||||
uint32_t sw_fstep: 16; /*frequency step for CW generator*/
|
||||
uint32_t sw_tone_en: 1; /*1: enable CW generator*/
|
||||
uint32_t debug_bit_sel: 5;
|
||||
uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/
|
||||
uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/
|
||||
uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/
|
||||
uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/
|
||||
uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/
|
||||
uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/
|
||||
uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/
|
||||
uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_dac_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/
|
||||
uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/
|
||||
uint32_t dac_scale1: 2; /*00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/
|
||||
uint32_t dac_scale2: 2; /*00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/
|
||||
uint32_t dac_inv1: 2; /*00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB*/
|
||||
uint32_t dac_inv2: 2; /*00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB*/
|
||||
uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/
|
||||
uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/
|
||||
uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/
|
||||
uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/
|
||||
uint32_t dac_scale1: 2; /*00: no scale*/
|
||||
uint32_t dac_scale2: 2; /*00: no scale*/
|
||||
uint32_t dac_inv1: 2; /*00: do not invert any bits*/
|
||||
uint32_t dac_inv2: 2; /*00: do not invert any bits*/
|
||||
uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/
|
||||
uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_dac_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm: 4;
|
||||
uint32_t sar1_dac_xpd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_amp_fsm_idle: 1;
|
||||
uint32_t amp_rst_fb_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_gnd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_fsm_idle: 1;
|
||||
uint32_t sar_rstb_fsm_idle: 1;
|
||||
uint32_t sar2_rstb_force: 2;
|
||||
uint32_t amp_rst_fb_force: 2;
|
||||
uint32_t amp_short_ref_force: 2;
|
||||
uint32_t amp_short_ref_gnd_force: 2;
|
||||
uint32_t reserved19: 13;
|
||||
uint32_t reserved0: 25;
|
||||
uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/
|
||||
uint32_t clk_en: 1; /*check cocpu whether clk on*/
|
||||
uint32_t reset_n: 1; /*check cocpu whether in reset state*/
|
||||
uint32_t eoi: 1; /*check cocpu whether in interrupt state*/
|
||||
uint32_t trap: 1; /*check cocpu whether in trap state*/
|
||||
uint32_t ebreak: 1; /*check cocpu whether in ebreak*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_ctrl2;
|
||||
} sar_cocpu_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_fo: 1; /*cocpu clk force on*/
|
||||
uint32_t start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/
|
||||
uint32_t start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/
|
||||
uint32_t shut: 1; /*to shut cocpu*/
|
||||
uint32_t shut_2_clk_dis: 6; /*time from shut cocpu to disable clk*/
|
||||
uint32_t shut_reset_en: 1; /*to reset cocpu*/
|
||||
uint32_t sel: 1; /*1: old ULP 0: new riscV*/
|
||||
uint32_t done_force: 1; /*1: select riscv done 0: select ulp done*/
|
||||
uint32_t done: 1; /*done signal used by riscv to control timer.*/
|
||||
uint32_t int_trigger: 1; /*trigger cocpu register interrupt*/
|
||||
uint32_t clk_en: 1; /*check cocpu whether clk on*/
|
||||
uint32_t reset_n: 1; /*check cocpu whether in reset state*/
|
||||
uint32_t eoi: 1; /*check cocpu whether in interrupt state*/
|
||||
uint32_t trap: 1; /*check cocpu whether in trap state*/
|
||||
uint32_t reserved29: 3;
|
||||
uint32_t touch_done: 1; /*int from touch done*/
|
||||
uint32_t touch_inactive: 1; /*int from touch inactive*/
|
||||
uint32_t touch_active: 1; /*int from touch active*/
|
||||
uint32_t saradc1: 1; /*int from saradc1*/
|
||||
uint32_t saradc2: 1; /*int from saradc2*/
|
||||
uint32_t tsens: 1; /*int from tsens*/
|
||||
uint32_t start: 1; /*int from start*/
|
||||
uint32_t sw: 1; /*int from software*/
|
||||
uint32_t swd: 1; /*int from super watch dog*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_ctrl;
|
||||
} sar_cocpu_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t saradc_int_ena: 1;
|
||||
uint32_t tsens_int_ena: 1;
|
||||
uint32_t start_int_ena: 1;
|
||||
uint32_t cocpu_int_ena: 1;
|
||||
uint32_t ebreak_int_ena: 1; /*int enable entry*/
|
||||
uint32_t reserved5: 5;
|
||||
uint32_t saradc_int_clr: 1;
|
||||
uint32_t tsens_int_clr: 1;
|
||||
uint32_t start_int_clr: 1;
|
||||
uint32_t cocpu_int_clr: 1;
|
||||
uint32_t ebreak_int_clr: 1; /*int clear entry*/
|
||||
uint32_t reserved15: 5;
|
||||
uint32_t saradc_int: 1; /*int from saradc*/
|
||||
uint32_t tsens_int: 1; /*int from tsens*/
|
||||
uint32_t start_int: 1; /*int from start*/
|
||||
uint32_t cocpu_int: 1; /*int from register*/
|
||||
uint32_t ebreak_int: 1; /*int from ebreak*/
|
||||
uint32_t reserved25: 7;
|
||||
uint32_t touch_done: 1;
|
||||
uint32_t touch_inactive: 1;
|
||||
uint32_t touch_active: 1;
|
||||
uint32_t saradc1: 1;
|
||||
uint32_t saradc2: 1;
|
||||
uint32_t tsens: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t sw: 1; /*cocpu int enable*/
|
||||
uint32_t swd: 1;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t sar_nouse; /**/
|
||||
} sar_cocpu_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done: 1;
|
||||
uint32_t touch_inactive: 1;
|
||||
uint32_t touch_active: 1;
|
||||
uint32_t saradc1: 1;
|
||||
uint32_t saradc2: 1;
|
||||
uint32_t tsens: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t sw: 1; /*cocpu int status*/
|
||||
uint32_t swd: 1;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done: 1;
|
||||
uint32_t touch_inactive: 1;
|
||||
uint32_t touch_active: 1;
|
||||
uint32_t saradc1: 1;
|
||||
uint32_t saradc2: 1;
|
||||
uint32_t tsens: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t sw: 1; /*cocpu int clear*/
|
||||
uint32_t swd: 1;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pc: 13; /*cocpu Program counter*/
|
||||
uint32_t mem_vld: 1; /*cocpu mem valid output*/
|
||||
uint32_t mem_rdy: 1; /*cocpu mem ready input*/
|
||||
uint32_t mem_wen: 4; /*cocpu mem write enable output*/
|
||||
uint32_t mem_addr: 13; /*cocpu mem address output*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_debug;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 28;
|
||||
uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/
|
||||
uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
|
||||
uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/
|
||||
uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_hall_ctrl;
|
||||
uint32_t sar_nouse; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_date: 28;
|
||||
|
@ -16,34 +16,46 @@
|
||||
#define _SOC_TOUCH_CHANNEL_H
|
||||
|
||||
//Touch channels
|
||||
#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM0
|
||||
#define TOUCH_PAD_NUM0_GPIO_NUM 4
|
||||
|
||||
#define TOUCH_PAD_GPIO0_CHANNEL TOUCH_PAD_NUM1
|
||||
#define TOUCH_PAD_NUM1_GPIO_NUM 0
|
||||
#define TOUCH_PAD_GPIO1_CHANNEL TOUCH_PAD_NUM1
|
||||
#define TOUCH_PAD_NUM1_GPIO_NUM 1
|
||||
|
||||
#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2
|
||||
#define TOUCH_PAD_NUM2_GPIO_NUM 2
|
||||
|
||||
#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3
|
||||
#define TOUCH_PAD_NUM3_GPIO_NUM 15
|
||||
#define TOUCH_PAD_GPIO3_CHANNEL TOUCH_PAD_NUM3
|
||||
#define TOUCH_PAD_NUM3_GPIO_NUM 3
|
||||
|
||||
#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4
|
||||
#define TOUCH_PAD_NUM4_GPIO_NUM 13
|
||||
#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM4
|
||||
#define TOUCH_PAD_NUM4_GPIO_NUM 4
|
||||
|
||||
#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5
|
||||
#define TOUCH_PAD_NUM5_GPIO_NUM 12
|
||||
#define TOUCH_PAD_GPIO5_CHANNEL TOUCH_PAD_NUM5
|
||||
#define TOUCH_PAD_NUM5_GPIO_NUM 5
|
||||
|
||||
#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6
|
||||
#define TOUCH_PAD_NUM6_GPIO_NUM 14
|
||||
#define TOUCH_PAD_GPIO6_CHANNEL TOUCH_PAD_NUM6
|
||||
#define TOUCH_PAD_NUM6_GPIO_NUM 6
|
||||
|
||||
#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7
|
||||
#define TOUCH_PAD_NUM7_GPIO_NUM 27
|
||||
#define TOUCH_PAD_GPIO7_CHANNEL TOUCH_PAD_NUM7
|
||||
#define TOUCH_PAD_NUM7_GPIO_NUM 7
|
||||
|
||||
#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8
|
||||
#define TOUCH_PAD_NUM8_GPIO_NUM 33
|
||||
#define TOUCH_PAD_GPIO8_CHANNEL TOUCH_PAD_NUM8
|
||||
#define TOUCH_PAD_NUM8_GPIO_NUM 8
|
||||
|
||||
#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9
|
||||
#define TOUCH_PAD_NUM9_GPIO_NUM 32
|
||||
#define TOUCH_PAD_GPIO9_CHANNEL TOUCH_PAD_NUM9
|
||||
#define TOUCH_PAD_NUM9_GPIO_NUM 9
|
||||
|
||||
#define TOUCH_PAD_GPIO10_CHANNEL TOUCH_PAD_NUM10
|
||||
#define TOUCH_PAD_NUM10_GPIO_NUM 10
|
||||
|
||||
#define TOUCH_PAD_GPIO11_CHANNEL TOUCH_PAD_NUM11
|
||||
#define TOUCH_PAD_NUM11_GPIO_NUM 11
|
||||
|
||||
#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM12
|
||||
#define TOUCH_PAD_NUM12_GPIO_NUM 12
|
||||
|
||||
#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM13
|
||||
#define TOUCH_PAD_NUM13_GPIO_NUM 13
|
||||
|
||||
#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM14
|
||||
#define TOUCH_PAD_NUM14_GPIO_NUM 14
|
||||
|
||||
#endif
|
||||
|
@ -48,6 +48,7 @@ static const char* TAG = "ulp";
|
||||
|
||||
esp_err_t ulp_run(uint32_t entry_point)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
// disable ULP timer
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
// wait for at least 1 RTC_SLOW_CLK cycle
|
||||
@ -64,6 +65,7 @@ esp_err_t ulp_run(uint32_t entry_point)
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
|
||||
// enable ULP timer
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
#endif
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
@ -112,6 +114,7 @@ esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, siz
|
||||
|
||||
esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if (period_index > 4) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
@ -128,5 +131,6 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
|
||||
}
|
||||
REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t),
|
||||
SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles);
|
||||
#endif
|
||||
return ESP_OK;
|
||||
}
|
||||
|
@ -12,8 +12,9 @@
|
||||
#include "freertos/task.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/adc.h"
|
||||
#include "esp_adc_cal.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp_adc_cal.h"
|
||||
#define DEFAULT_VREF 1100 //Use adc2_vref_to_gpio() to obtain a better estimate
|
||||
#define NO_OF_SAMPLES 64 //Multisampling
|
||||
|
||||
@ -89,4 +90,42 @@ void app_main()
|
||||
}
|
||||
}
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
|
||||
#define NO_OF_SAMPLES 64 //Multisampling
|
||||
|
||||
static const adc_channel_t channel = ADC_CHANNEL_6; // GPIO7 if ADC1, GPIO17 if ADC2
|
||||
static const adc_atten_t atten = ADC_ATTEN_DB_11; // Detect 0 ~ 3.6v
|
||||
static const adc_unit_t unit = ADC_UNIT_2;
|
||||
static const adc_unit_t width = ADC_WIDTH_BIT_12;
|
||||
|
||||
void app_main()
|
||||
{
|
||||
//Configure ADC
|
||||
if (unit == ADC_UNIT_1) {
|
||||
adc1_config_width(width);
|
||||
adc1_config_channel_atten(channel, atten);
|
||||
} else {
|
||||
adc2_config_channel_atten((adc2_channel_t)channel, atten);
|
||||
}
|
||||
|
||||
//Continuously sample ADC1
|
||||
while (1) {
|
||||
uint32_t adc_reading = 0;
|
||||
// Multisampling
|
||||
for (int i = 0; i < NO_OF_SAMPLES; i++) {
|
||||
if (unit == ADC_UNIT_1) {
|
||||
adc_reading += adc1_get_raw((adc1_channel_t)channel);
|
||||
} else {
|
||||
int raw;
|
||||
adc2_get_raw((adc2_channel_t)channel, width, &raw);
|
||||
adc_reading += raw;
|
||||
}
|
||||
}
|
||||
adc_reading /= NO_OF_SAMPLES;
|
||||
printf("ADC%d CH%d Raw: %d\t\n", unit, channel, adc_reading);
|
||||
vTaskDelay(pdMS_TO_TICKS(1000));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -15,7 +15,6 @@
|
||||
#include "driver/adc.h"
|
||||
#include "driver/dac.h"
|
||||
#include "esp_system.h"
|
||||
#include "esp_adc_cal.h"
|
||||
|
||||
#define DAC_EXAMPLE_CHANNEL CONFIG_EXAMPLE_DAC_CHANNEL
|
||||
#define ADC2_EXAMPLE_CHANNEL CONFIG_EXAMPLE_ADC2_CHANNEL
|
||||
|
6
examples/peripherals/temp_sensor/CMakeLists.txt
Normal file
6
examples/peripherals/temp_sensor/CMakeLists.txt
Normal file
@ -0,0 +1,6 @@
|
||||
# The following lines of boilerplate have to be in your project's CMakeLists
|
||||
# in this exact order for cmake to work correctly
|
||||
cmake_minimum_required(VERSION 3.5)
|
||||
|
||||
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
|
||||
project(temp_sensor)
|
9
examples/peripherals/temp_sensor/Makefile
Normal file
9
examples/peripherals/temp_sensor/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# This is a project Makefile. It is assumed the directory this Makefile resides in is a
|
||||
# project subdirectory.
|
||||
#
|
||||
|
||||
PROJECT_NAME := temp_sensor
|
||||
|
||||
include $(IDF_PATH)/make/project.mk
|
||||
|
0
examples/peripherals/temp_sensor/README.md
Normal file
0
examples/peripherals/temp_sensor/README.md
Normal file
4
examples/peripherals/temp_sensor/main/CMakeLists.txt
Normal file
4
examples/peripherals/temp_sensor/main/CMakeLists.txt
Normal file
@ -0,0 +1,4 @@
|
||||
set(COMPONENT_SRCS "temp_sensor_main.c")
|
||||
set(COMPONENT_ADD_INCLUDEDIRS ".")
|
||||
|
||||
register_component()
|
3
examples/peripherals/temp_sensor/main/component.mk
Normal file
3
examples/peripherals/temp_sensor/main/component.mk
Normal file
@ -0,0 +1,3 @@
|
||||
#
|
||||
# Main Makefile. This is basically the same as a component makefile.
|
||||
#
|
46
examples/peripherals/temp_sensor/main/temp_sensor_main.c
Normal file
46
examples/peripherals/temp_sensor/main/temp_sensor_main.c
Normal file
@ -0,0 +1,46 @@
|
||||
/* ADC1 Example
|
||||
|
||||
This example code is in the Public Domain (or CC0 licensed, at your option.)
|
||||
|
||||
Unless required by applicable law or agreed to in writing, this
|
||||
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
CONDITIONS OF ANY KIND, either express or implied.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp_log.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "driver/temp_sensor.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
|
||||
static const char* TAG = "TempSensor";
|
||||
|
||||
void tempsensor_example(void *arg)
|
||||
{
|
||||
// Initialize touch pad peripheral, it will start a timer to run a filter
|
||||
ESP_LOGI(TAG, "Initializing temp sensor");
|
||||
uint8_t temp_out;
|
||||
temp_sensor_t temp_sensor;
|
||||
temp_sensor_get_config(&temp_sensor);
|
||||
ESP_LOGI(TAG, "default dac %d, clk_div %d", temp_sensor.dac_offset, temp_sensor.clk_div);
|
||||
temp_sensor.dac_offset = TEMP_SENSOR_DAC_DEFAULT; // DEFAULT: range:-10℃ ~ 80℃, error < 1℃.
|
||||
temp_sensor_set_config(temp_sensor);
|
||||
temp_sensor_start();
|
||||
ESP_LOGI(TAG, "temp sensor started");
|
||||
while(1) {
|
||||
vTaskDelay(1000 / portTICK_RATE_MS);
|
||||
temp_sensor_read(&temp_out);
|
||||
ESP_LOGI(TAG, "temp out %d", temp_out);
|
||||
}
|
||||
ESP_LOGI(TAG, "test over");
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
void app_main()
|
||||
{
|
||||
xTaskCreate(tempsensor_example, "temp", 2048, NULL, 5, NULL);
|
||||
}
|
||||
#endif
|
||||
|
@ -9,6 +9,7 @@
|
||||
#include <stdio.h>
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "esp_log.h"
|
||||
|
||||
#include "driver/touch_pad.h"
|
||||
@ -16,6 +17,8 @@
|
||||
#include "soc/sens_periph.h"
|
||||
|
||||
static const char* TAG = "Touch pad";
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#define TOUCH_THRESH_NO_USE (0)
|
||||
#define TOUCH_THRESH_PERCENT (80)
|
||||
#define TOUCHPAD_FILTER_TOUCH_PERIOD (10)
|
||||
@ -167,3 +170,187 @@ void app_main()
|
||||
// Start a task to show what pads have been touched
|
||||
xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 2048, NULL, 5, NULL);
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
|
||||
static QueueHandle_t que_touch = NULL;
|
||||
typedef struct touch_msg {
|
||||
touch_pad_intr_mask_t intr_mask;
|
||||
uint32_t pad_num;
|
||||
uint32_t pad_status;
|
||||
uint32_t pad_val;
|
||||
}touch_event_t;
|
||||
|
||||
#define TOUCH_BUTTON_NUM 4
|
||||
#define TOUCH_BUTTON_WATERPROOF_ENABLE 1
|
||||
#define TOUCH_BUTTON_DENOISE_ENABLE 1
|
||||
|
||||
static const touch_pad_t button[TOUCH_BUTTON_NUM] = {
|
||||
TOUCH_PAD_NUM7, // 'SELECT' button.
|
||||
TOUCH_PAD_NUM9, // 'MENU' button.
|
||||
TOUCH_PAD_NUM11, // 'BACK' button.
|
||||
TOUCH_PAD_NUM13, // Guard ring for waterproof design.
|
||||
// if this pad be touched, other pads no response.
|
||||
};
|
||||
|
||||
/*
|
||||
* Touch threshold. The threshold determines the sensitivity of the touch.
|
||||
* This threshold is derived by testing changes in readings from different touch channels.
|
||||
* If (raw_data - baseline) > baseline * threshold, the pad be actived.
|
||||
* If (raw_data - baseline) < baseline * threshold, the pad be inactived.
|
||||
*/
|
||||
static const float button_threshold[TOUCH_BUTTON_NUM] = {
|
||||
0.2, // 20%.
|
||||
0.2, // 20%.
|
||||
0.2, // 20%.
|
||||
0.1, // 10%.
|
||||
};
|
||||
|
||||
/*
|
||||
Handle an interrupt triggered when a pad is touched.
|
||||
Recognize what pad has been touched and save it in a table.
|
||||
*/
|
||||
static void touchsensor_interrupt_cb(void * arg)
|
||||
{
|
||||
int task_awoken = pdFALSE;
|
||||
touch_event_t evt;
|
||||
|
||||
evt.intr_mask = touch_pad_get_int_status();
|
||||
evt.pad_status = touch_pad_get_status();
|
||||
evt.pad_num = touch_pad_get_scan_curr();
|
||||
|
||||
if(evt.intr_mask & TOUCH_PAD_INTR_MASK_DONE) {
|
||||
touch_pad_filter_baseline_read(evt.pad_num, &evt.pad_val);
|
||||
}
|
||||
xQueueSendFromISR(que_touch, &evt, &task_awoken);
|
||||
if (task_awoken == pdTRUE) {
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
}
|
||||
|
||||
static void tp_example_set_thresholds(void)
|
||||
{
|
||||
uint32_t touch_value;
|
||||
for (int i = 0; i<TOUCH_BUTTON_NUM; i++) {
|
||||
//read baseline value
|
||||
touch_pad_read_raw(button[i], &touch_value);
|
||||
//set interrupt threshold.
|
||||
touch_pad_set_thresh(button[i], touch_value * button_threshold[i]);
|
||||
ESP_LOGI(TAG, "test init: touch pad [%d] base %d, thresh %d", \
|
||||
button[i], touch_value, (uint32_t)(touch_value * button_threshold[i]));
|
||||
}
|
||||
}
|
||||
|
||||
static void touchsensor_filter_set(touch_filter_mode_t mode)
|
||||
{
|
||||
/* Filter function */
|
||||
touch_filter_config_t filter_info = {
|
||||
.mode = mode, // Test jitter and filter 1/4.
|
||||
.debounce_cnt = 1, // 1 time count.
|
||||
.hysteresis_thr = 1, // 9.4%
|
||||
.noise_thr = 1, // 37.5%
|
||||
.noise_neg_thr = 1, // 37.5%
|
||||
.neg_noise_limit = 10, // 10 time count.
|
||||
.jitter_step = 4, // use for jitter mode.
|
||||
};
|
||||
touch_pad_filter_set_config(filter_info);
|
||||
touch_pad_filter_start();
|
||||
touch_pad_filter_baseline_reset(TOUCH_PAD_MAX);
|
||||
ESP_LOGI(TAG, "touch pad filter init %d", mode);
|
||||
}
|
||||
|
||||
static void tp_example_read_task(void *pvParameter)
|
||||
{
|
||||
touch_event_t evt = {0};
|
||||
static uint8_t guard_mode_flag = 0;
|
||||
/* Wait touch sensor init done */
|
||||
vTaskDelay(100 / portTICK_RATE_MS);
|
||||
tp_example_set_thresholds();
|
||||
|
||||
while (1) {
|
||||
int ret = xQueueReceive(que_touch, &evt, (portTickType)portMAX_DELAY);
|
||||
if(ret != pdTRUE) {
|
||||
continue;
|
||||
}
|
||||
if(evt.intr_mask & TOUCH_PAD_INTR_MASK_ACTIVE) {
|
||||
/* if guard pad be touched, other pads no response. */
|
||||
if(evt.pad_num == button[3]) {
|
||||
guard_mode_flag = 1;
|
||||
ESP_LOGW(TAG, "TouchSensor [%d] be actived, enter guard mode", evt.pad_num);
|
||||
} else {
|
||||
if(guard_mode_flag == 0) {
|
||||
ESP_LOGI(TAG, "TouchSensor [%d] be actived, status mask 0x%x", evt.pad_num, evt.pad_status);
|
||||
} else {
|
||||
ESP_LOGW(TAG, "In guard mode. No response");
|
||||
}
|
||||
}
|
||||
}
|
||||
if(evt.intr_mask & TOUCH_PAD_INTR_MASK_INACTIVE) {
|
||||
/* if guard pad be touched, other pads no response. */
|
||||
if(evt.pad_num == button[3]) {
|
||||
guard_mode_flag = 0;
|
||||
ESP_LOGW(TAG, "TouchSensor [%d] be actived, exit guard mode", evt.pad_num);
|
||||
} else {
|
||||
if(guard_mode_flag == 0) {
|
||||
ESP_LOGI(TAG, "TouchSensor [%d] be inactived, status mask 0x%x", evt.pad_num, evt.pad_status);
|
||||
}
|
||||
}
|
||||
}
|
||||
if(evt.intr_mask & TOUCH_PAD_INTR_MASK_DONE) {
|
||||
ESP_LOGI(TAG, "TouchSensor [%d] measure done, raw data %d", evt.pad_num, evt.pad_val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void app_main()
|
||||
{
|
||||
touch_event_t evt = {0};
|
||||
if(que_touch == NULL) {
|
||||
que_touch = xQueueCreate(TOUCH_BUTTON_NUM, sizeof(touch_event_t));
|
||||
}
|
||||
// Initialize touch pad peripheral, it will start a timer to run a filter
|
||||
ESP_LOGI(TAG, "Initializing touch pad");
|
||||
/* Initialize touch pad peripheral. */
|
||||
touch_pad_init();
|
||||
for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
|
||||
touch_pad_config(button[i]);
|
||||
touch_pad_set_thresh(button[i], TOUCH_PAD_THRESHOLD_MAX);
|
||||
}
|
||||
|
||||
#if TOUCH_BUTTON_DENOISE_ENABLE
|
||||
/* Denoise setting at TouchSensor 0. */
|
||||
touch_pad_denoise_t denoise = {
|
||||
/* The bits to be cancelled are determined according to the noise level. */
|
||||
.grade = TOUCH_PAD_DENOISE_BIT4,
|
||||
.cap_level = TOUCH_PAD_DENOISE_CAP_L7,
|
||||
};
|
||||
touch_pad_denoise_set_config(denoise);
|
||||
touch_pad_denoise_enable();
|
||||
ESP_LOGI(TAG, "Denoise function init");
|
||||
#endif
|
||||
|
||||
#if TOUCH_BUTTON_WATERPROOF_ENABLE
|
||||
/* Waterproof function */
|
||||
touch_pad_waterproof_t waterproof = {
|
||||
.guard_ring_pad = button[3], // If no ring pad, set 0;
|
||||
/* It depends on the number of the parasitic capacitance of the shield pad. */
|
||||
.shield_driver = TOUCH_PAD_SHIELD_DRV_L0, //40pf
|
||||
};
|
||||
touch_pad_waterproof_set_config(waterproof);
|
||||
touch_pad_waterproof_enable();
|
||||
ESP_LOGI(TAG, "touch pad waterproof init");
|
||||
#endif
|
||||
|
||||
/* Filter setting */
|
||||
touchsensor_filter_set(TOUCH_PAD_FILTER_IIR_8);
|
||||
/* Register touch interrupt ISR, enable intr type. */
|
||||
touch_pad_isr_register(touchsensor_interrupt_cb, NULL, TOUCH_PAD_INTR_MASK_ALL);
|
||||
touch_pad_intr_enable(TOUCH_PAD_INTR_INACTIVE);
|
||||
touch_pad_intr_enable(TOUCH_PAD_INTR_ACTIVE);
|
||||
|
||||
/* Enable touch sensor clock. Work mode is "timer trigger". */
|
||||
touch_pad_fsm_start(TOUCH_FSM_MODE_TIMER);
|
||||
|
||||
// Start a task to show what pads have been touched
|
||||
xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 2048, NULL, 5, NULL);
|
||||
}
|
||||
#endif
|
@ -10,7 +10,9 @@
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "driver/touch_pad.h"
|
||||
#include "esp_log.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#define TOUCH_PAD_NO_CHANGE (-1)
|
||||
#define TOUCH_THRESH_NO_USE (0)
|
||||
#define TOUCH_FILTER_MODE_EN (1)
|
||||
@ -69,3 +71,74 @@ void app_main()
|
||||
// Start task to read values sensed by pads
|
||||
xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 2048, NULL, 5, NULL);
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
|
||||
#define TOUCH_BUTTON_NUM 14
|
||||
|
||||
static const char * TAG = "touch read";
|
||||
static const touch_pad_t button[TOUCH_BUTTON_NUM] = {
|
||||
TOUCH_PAD_NUM1,
|
||||
TOUCH_PAD_NUM2,
|
||||
TOUCH_PAD_NUM3,
|
||||
TOUCH_PAD_NUM4,
|
||||
TOUCH_PAD_NUM5,
|
||||
TOUCH_PAD_NUM6,
|
||||
TOUCH_PAD_NUM7,
|
||||
TOUCH_PAD_NUM8,
|
||||
TOUCH_PAD_NUM9,
|
||||
TOUCH_PAD_NUM10,
|
||||
TOUCH_PAD_NUM11,
|
||||
TOUCH_PAD_NUM12,
|
||||
TOUCH_PAD_NUM13,
|
||||
TOUCH_PAD_NUM14
|
||||
};
|
||||
|
||||
/*
|
||||
Read values sensed at all available touch pads.
|
||||
Print out values in a loop on a serial monitor.
|
||||
*/
|
||||
static void tp_example_read_task(void *pvParameter)
|
||||
{
|
||||
uint16_t touch_value;
|
||||
uint16_t touch_filter_value;
|
||||
|
||||
/* Wait touch sensor init done */
|
||||
vTaskDelay(100 / portTICK_RATE_MS);
|
||||
printf("Touch Sensor read, the output format is: \nTouchpad num:[raw data]\n\n");
|
||||
|
||||
while (1) {
|
||||
for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
|
||||
touch_pad_read_raw(button[i], &touch_value); // read raw data.
|
||||
printf("T%d: [%4d] ", button[i], touch_value);
|
||||
}
|
||||
printf("\n");
|
||||
vTaskDelay(200 / portTICK_PERIOD_MS);
|
||||
}
|
||||
}
|
||||
|
||||
void app_main()
|
||||
{
|
||||
/* Initialize touch pad peripheral. */
|
||||
touch_pad_init();
|
||||
for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
|
||||
touch_pad_config(button[i]);
|
||||
touch_pad_set_thresh(button[i], TOUCH_PAD_THRESHOLD_MAX);
|
||||
}
|
||||
|
||||
/* Denoise setting at TouchSensor 0. */
|
||||
touch_pad_denoise_t denoise = {
|
||||
/* The bits to be cancelled are determined according to the noise level. */
|
||||
.grade = TOUCH_PAD_DENOISE_BIT4,
|
||||
.cap_level = TOUCH_PAD_DENOISE_CAP_L7,
|
||||
};
|
||||
touch_pad_denoise_set_config(denoise);
|
||||
touch_pad_denoise_enable();
|
||||
ESP_LOGI(TAG, "Denoise function init");
|
||||
|
||||
/* Enable touch sensor clock. Work mode is "timer trigger". */
|
||||
touch_pad_fsm_start(TOUCH_FSM_MODE_TIMER);
|
||||
|
||||
/* Start task to read values by pads. */
|
||||
xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 2048, NULL, 5, NULL);
|
||||
}
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user