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https://github.com/espressif/esp-idf.git
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Update RMT driver for esp32s2beta
This commit is contained in:
houwenxiang
kooho
parent
cbc153786d
commit
6a8fe5cf79
@ -35,15 +35,18 @@ typedef enum {
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RMT_CHANNEL_1, /*!< RMT Channel 1 */
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RMT_CHANNEL_2, /*!< RMT Channel 2 */
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RMT_CHANNEL_3, /*!< RMT Channel 3 */
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//ESP32-S2 only have 4 channel
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#ifdef CONFIG_IDF_TARGET_ESP32
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RMT_CHANNEL_4, /*!< RMT Channel 4 */
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RMT_CHANNEL_5, /*!< RMT Channel 5 */
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RMT_CHANNEL_6, /*!< RMT Channel 6 */
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RMT_CHANNEL_7, /*!< RMT Channel 7 */
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#endif
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RMT_CHANNEL_MAX
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} rmt_channel_t;
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typedef enum {
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RMT_MEM_OWNER_TX = 0, /*!< RMT RX mode, RMT transmitter owns the memory block*/
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RMT_MEM_OWNER_TX = 0, /*!< RMT TX mode, RMT transmitter owns the memory block*/
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RMT_MEM_OWNER_RX = 1, /*!< RMT RX mode, RMT receiver owns the memory block*/
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RMT_MEM_OWNER_MAX,
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}rmt_mem_owner_t;
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@ -1,4 +1,4 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@ -193,8 +193,12 @@ esp_err_t rmt_tx_stop(rmt_channel_t channel)
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{
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RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
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portENTER_CRITICAL(&rmt_spinlock);
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#ifdef CONFIG_IDF_TARGET_ESP32
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RMTMEM.chan[channel].data32[0].val = 0;
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RMT.conf_ch[channel].conf1.tx_start = 0;
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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RMT.conf_ch[channel].conf1.tx_stop = 1;
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#endif
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RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
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RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
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portEXIT_CRITICAL(&rmt_spinlock);
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@ -317,9 +321,9 @@ esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool* idle_out_en, rmt_idle_
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esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t* status)
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{
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RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
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#if CONFIG_IDF_TARGET_ESP32
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#ifdef CONFIG_IDF_TARGET_ESP32
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*status = RMT.status_ch[channel];
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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*status = RMT.status_ch[channel].val;
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#endif
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return ESP_OK;
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@ -386,9 +390,15 @@ esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_th
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RMT.tx_lim_ch[channel].limit = evt_thresh;
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portEXIT_CRITICAL(&rmt_spinlock);
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rmt_set_tx_wrap_en(true);
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#ifdef CONFIG_IDF_TARGET_ESP32
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rmt_set_intr_enable_mask(BIT(channel + 24));
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} else {
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rmt_clr_intr_enable_mask(BIT(channel + 24));
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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rmt_set_intr_enable_mask(BIT(channel + 12));
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} else {
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rmt_clr_intr_enable_mask(BIT(channel + 12));
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#endif
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}
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return ESP_OK;
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}
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@ -400,7 +410,7 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu
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RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))),
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RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], 2);
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
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if(mode == RMT_MODE_TX) {
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gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
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gpio_matrix_out(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0);
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@ -565,7 +575,12 @@ static void IRAM_ATTR rmt_driver_isr_default(void* arg)
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while (status) {
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int i = __builtin_ffs(status) - 1;
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status &= ~(1 << i);
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#ifdef CONFIG_IDF_TARGET_ESP32
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if(i < 24) {
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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if(i >= 15) {
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} else if(i < 12) {
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#endif
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channel = i / 3;
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rmt_obj_t* p_rmt = p_rmt_obj[channel];
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if(NULL == p_rmt) {
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@ -616,8 +631,13 @@ static void IRAM_ATTR rmt_driver_isr_default(void* arg)
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default:
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break;
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}
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#ifdef CONFIG_IDF_TARGET_ESP32
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} else {
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channel = i - 24;
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#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
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} else if(i >= 12 && i < 16) {
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channel = i - 12;
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#endif
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rmt_obj_t* p_rmt = p_rmt_obj[channel];
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if(p_rmt->tx_data == NULL) {
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@ -13,7 +13,7 @@ PROVIDE ( I2C0 = 0x3f413000 );
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PROVIDE ( UHCI0 = 0x3f414000 );
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PROVIDE ( HOST = 0x3f415000 );
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PROVIDE ( RMT = 0x3f416000 );
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PROVIDE ( RMTMEM = 0x3f416800 );
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PROVIDE ( RMTMEM = 0x3f416400 );
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PROVIDE ( PCNT = 0x3f417000 );
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PROVIDE ( SLC = 0x3f418000 );
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PROVIDE ( LEDC = 0x3f419000 );
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File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@ -18,45 +18,48 @@ extern "C" {
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#endif
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typedef volatile struct {
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uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
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struct{
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uint32_t data_ch[4]; /**/
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struct {
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union {
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struct {
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uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/
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uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/
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uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/
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uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/
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uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/
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uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/
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uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/
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uint32_t div_cnt: 8;
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uint32_t idle_thres: 16;
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uint32_t mem_size: 3;
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uint32_t reserved27: 1;
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uint32_t carrier_en: 1;
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uint32_t carrier_out_lv: 1;
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uint32_t mem_pd: 1;
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uint32_t clk_en: 1;
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};
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uint32_t val;
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} conf0;
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union {
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struct {
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uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/
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uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/
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uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
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uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
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uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
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uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/
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uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/
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uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/
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uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/
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uint32_t tx_start: 1;
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uint32_t rx_en: 1;
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uint32_t mem_wr_rst: 1;
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uint32_t mem_rd_rst: 1;
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uint32_t apb_mem_rst: 1;
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uint32_t mem_owner: 1;
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uint32_t tx_conti_mode: 1;
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uint32_t rx_filter_en: 1;
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uint32_t rx_filter_thres: 8;
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uint32_t reserved16: 1;
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uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/
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uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
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uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/
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uint32_t ref_always_on: 1;
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uint32_t idle_out_lv: 1;
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uint32_t idle_out_en: 1;
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uint32_t tx_stop: 1;
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uint32_t reserved21: 11;
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};
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uint32_t val;
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} conf1;
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} conf_ch[8];
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} conf_ch[4];
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union {
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struct {
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uint32_t mem_waddr_ex: 10;
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uint32_t mem_raddr_ex: 10;
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uint32_t mem_waddr_ex: 9;
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uint32_t reserved9: 1;
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uint32_t mem_raddr_ex: 9;
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uint32_t reserved19: 1;
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uint32_t state: 3;
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uint32_t mem_owner_err: 1;
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uint32_t mem_full: 1;
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@ -66,183 +69,141 @@ typedef volatile struct {
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} status_ch[8];
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} status_ch[4];
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union {
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struct {
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uint32_t waddr: 10;
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uint32_t raddr: 10;
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uint32_t reserved20: 12;
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uint32_t waddr: 9;
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uint32_t reserved9: 1;
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uint32_t raddr: 9;
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uint32_t reserved19: 13;
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};
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uint32_t val;
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} apb_mem_addr_ch[8];
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} apb_mem_addr_ch[4];
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union {
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struct {
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uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
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uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
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uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
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uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
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uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
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uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
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uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
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uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
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uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
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uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
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uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
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uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
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uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
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uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
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uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
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uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
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uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
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uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
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uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
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uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
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uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
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uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
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uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
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uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
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uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/
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uint32_t ch0_tx_end: 1;
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uint32_t ch0_rx_end: 1;
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uint32_t ch0_err: 1;
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uint32_t ch1_tx_end: 1;
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uint32_t ch1_rx_end: 1;
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uint32_t ch1_err: 1;
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uint32_t ch2_tx_end: 1;
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uint32_t ch2_rx_end: 1;
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uint32_t ch2_err: 1;
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uint32_t ch3_tx_end: 1;
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uint32_t ch3_rx_end: 1;
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uint32_t ch3_err: 1;
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uint32_t ch0_tx_thr_event: 1;
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uint32_t ch1_tx_thr_event: 1;
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uint32_t ch2_tx_thr_event: 1;
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uint32_t ch3_tx_thr_event: 1;
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uint32_t ch0_tx_loop: 1;
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uint32_t ch1_tx_loop: 1;
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uint32_t ch2_tx_loop: 1;
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uint32_t ch3_tx_loop: 1;
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uint32_t reserved20: 12;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
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uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/
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uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/
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uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
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uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/
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uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/
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uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
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uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/
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uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/
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uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
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uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/
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uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/
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uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
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uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/
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uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/
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uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
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uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/
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uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/
|
||||
uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/
|
||||
uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
|
||||
uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/
|
||||
uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch0_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch1_rx_end: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
|
||||
uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
|
||||
uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/
|
||||
uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
|
||||
uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
|
||||
uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/
|
||||
uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
|
||||
uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
|
||||
uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/
|
||||
uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
|
||||
uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
|
||||
uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/
|
||||
uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
|
||||
uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
|
||||
uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/
|
||||
uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
|
||||
uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
|
||||
uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/
|
||||
uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
|
||||
uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
|
||||
uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/
|
||||
uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
|
||||
uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
|
||||
uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch0_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch1_rx_end: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
|
||||
uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
|
||||
uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/
|
||||
uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
|
||||
uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
|
||||
uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/
|
||||
uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
|
||||
uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
|
||||
uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/
|
||||
uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
|
||||
uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
|
||||
uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/
|
||||
uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
|
||||
uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
|
||||
uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/
|
||||
uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
|
||||
uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
|
||||
uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/
|
||||
uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
|
||||
uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
|
||||
uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/
|
||||
uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
|
||||
uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
|
||||
uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/
|
||||
uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch0_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch1_rx_end: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/
|
||||
uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/
|
||||
uint32_t low: 16;
|
||||
uint32_t high: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} carrier_duty_ch[8];
|
||||
} carrier_duty_ch[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t limit: 9;
|
||||
uint32_t tx_loop_num: 10;
|
||||
uint32_t tx_loop_cnt_en: 1;
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t limit: 9;
|
||||
uint32_t tx_loop_num: 10;
|
||||
uint32_t tx_loop_cnt_en: 1;
|
||||
uint32_t loop_count_reset: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_lim_ch[8];
|
||||
} tx_lim_ch[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
|
||||
uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
|
||||
uint32_t fifo_mask: 1;
|
||||
uint32_t mem_tx_wrap_en: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -253,12 +214,8 @@ typedef volatile struct {
|
||||
uint32_t ch1: 1;
|
||||
uint32_t ch2: 1;
|
||||
uint32_t ch3: 1;
|
||||
uint32_t ch4: 1;
|
||||
uint32_t ch5: 1;
|
||||
uint32_t ch6: 1;
|
||||
uint32_t ch7: 1;
|
||||
uint32_t en: 1;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_sim;
|
||||
@ -268,70 +225,38 @@ typedef volatile struct {
|
||||
uint32_t ch1: 1;
|
||||
uint32_t ch2: 1;
|
||||
uint32_t ch3: 1;
|
||||
uint32_t ch4: 1;
|
||||
uint32_t ch5: 1;
|
||||
uint32_t ch6: 1;
|
||||
uint32_t ch7: 1;
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ref_cnt_rst;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_tx_loop: 1;
|
||||
uint32_t ch5_tx_loop: 1;
|
||||
uint32_t ch6_tx_loop: 1;
|
||||
uint32_t ch7_tx_loop: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} int1_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_tx_loop: 1;
|
||||
uint32_t ch5_tx_loop: 1;
|
||||
uint32_t ch6_tx_loop: 1;
|
||||
uint32_t ch7_tx_loop: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} int1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_tx_loop: 1;
|
||||
uint32_t ch5_tx_loop: 1;
|
||||
uint32_t ch6_tx_loop: 1;
|
||||
uint32_t ch7_tx_loop: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} int1_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_tx_loop: 1;
|
||||
uint32_t ch5_tx_loop: 1;
|
||||
uint32_t ch6_tx_loop: 1;
|
||||
uint32_t ch7_tx_loop: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} int1_clr;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} rmt_dev_t;
|
||||
extern rmt_dev_t RMT;
|
||||
@ -365,7 +290,7 @@ typedef volatile struct {
|
||||
rmt_item32_t data32[64];
|
||||
rmt_item16_t data16[128];
|
||||
};
|
||||
} chan[8];
|
||||
} chan[4];
|
||||
} rmt_mem_t;
|
||||
extern rmt_mem_t RMTMEM;
|
||||
|
||||
@ -373,4 +298,4 @@ extern rmt_mem_t RMTMEM;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_RMT_STRUCT_H_ */
|
||||
#endif /* _SOC_RMT_STRUCT_H_ */
|
||||
@ -7,9 +7,7 @@ set(SOC_SRCS "cpu_util.c"
|
||||
"rtc_sleep.c"
|
||||
"rtc_time.c"
|
||||
"soc_memory_layout.c"
|
||||
"spi_periph.c"
|
||||
"gpio_periph.c"
|
||||
"rtc_periph.c")
|
||||
"spi_periph.c")
|
||||
|
||||
if(NOT CMAKE_BUILD_EARLY_EXPANSION)
|
||||
set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES
|
||||
|
||||
Loading…
Reference in New Issue
Block a user