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rtc: update rtc related code(rtc_sleep rtc_init) to support esp32s3

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This commit is contained in:
fuzhibo 2020-09-10 16:08:43 +08:00 committed by bot
parent d7b125a87b
commit 93c7cf094e
8 changed files with 236 additions and 166 deletions
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1
components/driver/test/adc_dma_test/test_esp32s2.c
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@ -444,6 +444,7 @@ int test_adc_dig_dma_single_unit(adc_unit_t adc)
adc_dac_dma_linker_deinit();
adc_dac_dma_isr_deregister(adc_dma_isr, NULL);
TEST_ESP_OK( adc_digi_deinit() );
return 0;
}

63
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@ -149,6 +149,18 @@ void rtc_clk_set_xtal_wait(void)
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms);
}
static void wait_dig_dbias_valid(uint64_t rtc_cycles)
{
rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) {
cal_clk = RTC_CAL_8MD256;
}
rtc_clk_cal(cal_clk, rtc_cycles);
}
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
{
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
@ -295,19 +307,6 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
// Enable calibration by software
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
for (int ext_cap = 0; ext_cap < 16; ext_cap++) {
uint8_t cal_result;
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
cal_result = REGI2C_READ_MASK(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
if (cal_result == 0) {
break;
}
if (ext_cap == 15) {
SOC_LOGE(TAG, "BBPLL SOFTWARE CAL FAIL");
}
}
s_cur_pll_freq = pll_freq;
}
@ -330,9 +329,10 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
} else {
SOC_LOGE(TAG, "invalid frequency");
}
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
wait_dig_dbias_valid(2);
REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
rtc_clk_apb_freq_update(80 * MHZ);
ets_update_cpu_frequency(cpu_freq_mhz);
@ -386,24 +386,23 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
{
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) {
rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
}
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_disable();
}
if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
if (config->div > 1) {
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_disable();
}
} else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
}
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
} else if (config->source == RTC_CPU_FREQ_SRC_8M) {
rtc_clk_cpu_freq_to_8m();
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) {
rtc_clk_bbpll_disable();
}
}
}
@ -488,6 +487,13 @@ void rtc_clk_cpu_freq_set_xtal(void)
void rtc_clk_cpu_freq_to_xtal(int freq, int div)
{
ets_update_cpu_frequency(freq);
/* set digital voltage for different cpu freq from xtal */
if (freq <= 2) {
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_2M);
} else {
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
}
wait_dig_dbias_valid(2);
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1);
@ -495,18 +501,13 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
/* switch clock source */
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL);
rtc_clk_apb_freq_update(freq * MHZ);
/* lower the voltage */
if (freq <= 2) {
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_2M);
} else {
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
}
}
static void rtc_clk_cpu_freq_to_8m(void)
{
ets_update_cpu_frequency(8);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
wait_dig_dbias_valid(2);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);

13
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@ -22,10 +22,13 @@
#include "soc/extmem_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_ulp.h"
#include "soc_log.h"
#define RTC_CNTL_MEM_FORCE_PU (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
static char *TAG = "rtcinit";
void rtc_init(rtc_config_t cfg)
{
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
@ -113,21 +116,20 @@ void rtc_init(rtc_config_t cfg)
//cancel digital pu force
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
/* If this mask is enabled, all soc memories cannot enter power down mode */
/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
/* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
/* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
rtc_sleep_pd(pd_cfg);
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
rtc_sleep_pu(pu_cfg);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
// ROM_RAM power domain is removed
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
//cancel digital PADS force no iso
if (cfg.cpu_waiti_clk_gate) {
@ -182,6 +184,7 @@ void rtc_init(rtc_config_t cfg)
break;
}
if (cycle1 >= timeout_cycle) {
SOC_LOGW(TAG, "o_code calibration fail\n");
break;
}
}

30
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@ -27,13 +27,11 @@
#include "soc/rtc.h"
#include "regi2c_ctrl.h"
#define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pd_config_t structure
* Configure whether certain peripherals are powered up in sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
*/
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
@ -48,13 +46,25 @@ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
if (cfg.sram_fpu) {
REG_SET_FIELD(SYSTEM_SRAM_CTRL_2_REG, SYSTEM_SRAM_POWER_UP, SYSTEM_SRAM_POWER_UP);
} else {
REG_SET_FIELD(SYSTEM_SRAM_CTRL_2_REG, SYSTEM_SRAM_POWER_UP, 0);
}
if (cfg.rom_ram_fpu) {
SET_PERI_REG_MASK(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_DRAM0_POWER_UP);
REG_SET_FIELD(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_POWER_UP, SYSTEM_ROM_IRAM0_POWER_UP);
} else {
CLEAR_PERI_REG_MASK(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_DRAM0_POWER_UP);
REG_SET_FIELD(SYSTEM_ROM_CTRL_1_REG, SYSTEM_ROM_IRAM0_POWER_UP, 0);
}
}
void rtc_sleep_init(rtc_sleep_config_t cfg)
{
if (cfg.lslp_mem_inf_fpu) {
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(1);
rtc_sleep_pd(pd_cfg);
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
if (cfg.rtc_mem_inf_follow_cpu) {
@ -132,7 +142,7 @@ void rtc_sleep_set_wakeup_time(uint64_t t)
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
}
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
__attribute__((weak)) uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
{
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
@ -151,8 +161,8 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
/* restore config if it is a light sleep */
if (lslp_mem_inf_fpu) {
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
rtc_sleep_pd(pd_cfg);
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
return reject;
}

7
components/esp_system/sleep_modes.c
View File

@ -202,7 +202,7 @@ static void IRAM_ATTR flush_uarts(void)
for (int i = 0; i < SOC_UART_NUM; ++i) {
#ifdef CONFIG_IDF_TARGET_ESP32
esp_rom_uart_tx_wait_idle(i);
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
esp_rom_uart_tx_wait_idle(i);
}
@ -219,7 +219,7 @@ static void IRAM_ATTR suspend_uarts(void)
while (REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT) != 0) {
;
}
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
@ -238,7 +238,7 @@ static void IRAM_ATTR resume_uarts(void)
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
@ -298,7 +298,6 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
touch_wakeup_prepare();
}
#endif
uint32_t reject_triggers = 0;
if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
/* Light sleep, enable sleep reject for faster return from this function,

6
components/hal/esp32s3/include/hal/adc_ll.h
View File

@ -1071,8 +1071,8 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
/* Enable i2s_write_reg function. */
void phy_get_romfunc_addr(void);
phy_get_romfunc_addr();
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
// CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);//TODO: finish it in MR-10423.
// SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);//TODO: finish it in MR-10423.
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
@ -1122,7 +1122,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
/* Enable i2s_write_reg function. */
void phy_get_romfunc_addr(void);
phy_get_romfunc_addr();
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
// SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); //TODO: finish it in MR-10423.
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);

54
components/soc/esp32s3/include/soc/rtc.h
View File

@ -68,14 +68,16 @@ extern "C" {
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_0V90 0 //voltage is about 0.68v in fact
#define RTC_CNTL_DBIAS_0V95 13
#define RTC_CNTL_DBIAS_1V00 16
#define RTC_CNTL_DBIAS_1V05 18
#define RTC_CNTL_DBIAS_1V10 20
#define RTC_CNTL_DBIAS_1V15 22
#define RTC_CNTL_DBIAS_1V20 24
#define RTC_CNTL_DBIAS_1V25 31 //voltage is about 1.34v in fact
#define RTC_CNTL_DBIAS_SLP 0 ///< sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 ///< digital voltage
#define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18
#define RTC_CNTL_DBIAS_1V05 20
#define RTC_CNTL_DBIAS_1V10 23
#define RTC_CNTL_DBIAS_1V15 25
#define RTC_CNTL_DBIAS_1V20 28
#define RTC_CNTL_DBIAS_1V25 30
#define RTC_CNTL_DBIAS_1V30 31 ///< voltage is about 1.34v in fact
#define DELAY_FAST_CLK_SWITCH 3
#define DELAY_SLOW_CLK_SWITCH 300
@ -110,7 +112,7 @@ extern "C" {
/*
set sleep_init default param
*/
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
@ -561,22 +563,24 @@ uint64_t rtc_deep_slp_time_get(void);
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief Power down flags for rtc_sleep_pd function
* @brief Power up flags for rtc_sleep_pd function
*/
typedef struct {
uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep
uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep
uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep
uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep
uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep
uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep
uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep
} rtc_sleep_pd_config_t;
uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep
uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep
uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep
uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep
uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep
uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
} rtc_sleep_pu_config_t;
/**
* Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
* Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
*/
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
.dig_fpu = (val), \
.rtc_fpu = (val), \
.cpu_fpu = (val), \
@ -584,9 +588,11 @@ typedef struct {
.bb_fpu = (val), \
.nrx_fpu = (val), \
.fe_fpu = (val), \
.sram_fpu = (val), \
.rom_ram_fpu = (val), \
}
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
/**
* @brief sleep configuration for rtc_sleep_init function
@ -626,10 +632,10 @@ typedef struct {
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
.dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V95, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.dig_dbias_slp = RTC_CNTL_DBIAS_SLP, \
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.rtc_dbias_slp = RTC_CNTL_DBIAS_0V95, \
.rtc_dbias_slp = RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \

228
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
View File

@ -462,18 +462,12 @@ extern "C" {
#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23))
#define RTC_CNTL_PLLA_FORCE_PD_V 0x1
#define RTC_CNTL_PLLA_FORCE_PD_S 23
/* RTC_CNTL_SAR_I2C_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
/*description: PLLA force power up*/
#define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22))
#define RTC_CNTL_SAR_I2C_FORCE_PU_M (BIT(22))
#define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x1
#define RTC_CNTL_SAR_I2C_FORCE_PU_S 22
/* RTC_CNTL_SAR_I2C_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description: PLLA force power down*/
#define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21))
#define RTC_CNTL_SAR_I2C_FORCE_PD_M (BIT(21))
#define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x1
#define RTC_CNTL_SAR_I2C_FORCE_PD_S 21
#define RTC_CNTL_SAR_I2C_PU (BIT(22))
#define RTC_CNTL_SAR_I2C_PU_M (BIT(22))
#define RTC_CNTL_SAR_I2C_PU_V 0x1
#define RTC_CNTL_SAR_I2C_PU_S 22
/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_GLITCH_RST_EN (BIT(20))
@ -494,6 +488,78 @@ extern "C" {
#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18
#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038)
/* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_PRO_DRESET_MASK (BIT(25))
#define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25))
#define RTC_CNTL_PRO_DRESET_MASK_V 0x1
#define RTC_CNTL_PRO_DRESET_MASK_S 25
/* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_APP_DRESET_MASK (BIT(24))
#define RTC_CNTL_APP_DRESET_MASK_M (BIT(24))
#define RTC_CNTL_APP_DRESET_MASK_V 0x1
#define RTC_CNTL_APP_DRESET_MASK_S 24
/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23))
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23))
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23
/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22))
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22))
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22
/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21))
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21))
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1
#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21
/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20))
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20))
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1
#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20
/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: PROCPU OcdHaltOnReset*/
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19))
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19))
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1
#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19
/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: APPCPU OcdHaltOnReset*/
#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18))
#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18))
#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1
#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18
/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
/*description: clear APP CPU reset flag*/
#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17))
#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17))
#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1
#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17
/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
/*description: clear PRO CPU reset_flag*/
#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16))
#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16))
#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1
#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16
/* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: APP CPU reset flag*/
#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15))
#define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15))
#define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1
#define RTC_CNTL_RESET_FLAG_APPCPU_S 15
/* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: PRO CPU reset_flag*/
#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14))
#define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14))
#define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1
#define RTC_CNTL_RESET_FLAG_PROCPU_S 14
/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: PRO CPU state vector sel*/
#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
@ -1368,7 +1434,7 @@ extern "C" {
#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V) << (RTC_CNTL_DREFH_SDIO_S))
#define RTC_CNTL_DREFH_SDIO_V 0x3
#define RTC_CNTL_DREFH_SDIO_S 29
/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
#define RTC_CNTL_DREFM_SDIO 0x00000003
#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V) << (RTC_CNTL_DREFM_SDIO_S))
@ -1454,42 +1520,6 @@ extern "C" {
#define RTC_CNTL_SDIO_TIMER_TARGET_S 0
#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080)
/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: */
#define RTC_CNTL_RST_BIAS_I2C (BIT(31))
#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31))
#define RTC_CNTL_RST_BIAS_I2C_V 0x1
#define RTC_CNTL_RST_BIAS_I2C_S 31
/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: DEC_HEARTBEAT_WIDTH*/
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30))
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1
#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30
/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */
/*description: INC_HEARTBEAT_PERIOD*/
#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))
#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29))
#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1
#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29
/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */
/*description: DEC_HEARTBEAT_PERIOD*/
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28))
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28))
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1
#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28
/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: INC_HEARTBEAT_REFRESH*/
#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27))
#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27))
#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1
#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27
/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */
/*description: ENB_SCK_XTAL*/
#define RTC_CNTL_ENB_SCK_XTAL (BIT(26))
#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26))
#define RTC_CNTL_ENB_SCK_XTAL_V 0x1
#define RTC_CNTL_ENB_SCK_XTAL_S 26
/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
/*description: DBG_ATTEN when rtc in monitor state*/
#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F
@ -1577,50 +1607,19 @@ extern "C" {
#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28))
#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1
#define RTC_CNTL_DBOOST_FORCE_PD_S 28
/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
/*description: RTC_DBIAS during wakeup*/
#define RTC_CNTL_DBIAS_WAK 0x00000007
#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V) << (RTC_CNTL_DBIAS_WAK_S))
#define RTC_CNTL_DBIAS_WAK_V 0x7
#define RTC_CNTL_DBIAS_WAK_S 25
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DIG_DBIAS_0V85 0
#define RTC_CNTL_DIG_DBIAS_0V90 1
#define RTC_CNTL_DIG_DBIAS_0V95 2
#define RTC_CNTL_DIG_DBIAS_1V00 3
#define RTC_CNTL_DIG_DBIAS_1V05 4
#define RTC_CNTL_DIG_DBIAS_1V10 5
#define RTC_CNTL_DIG_DBIAS_1V15 6
#define RTC_CNTL_DIG_DBIAS_1V20 7
/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */
/*description: RTC_DBIAS during sleep*/
#define RTC_CNTL_DBIAS_SLP 0x00000007
#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V) << (RTC_CNTL_DBIAS_SLP_S))
#define RTC_CNTL_DBIAS_SLP_V 0x7
#define RTC_CNTL_DBIAS_SLP_S 22
/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
/*description: SCK_DCAP*/
#define RTC_CNTL_SCK_DCAP 0x000000FF
#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V) << (RTC_CNTL_SCK_DCAP_S))
#define RTC_CNTL_SCK_DCAP_V 0xFF
#define RTC_CNTL_SCK_DCAP_S 14
/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
/*description: DIG_REG_DBIAS during wakeup*/
#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007
#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V) << (RTC_CNTL_DIG_DBIAS_WAK_S))
#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7
#define RTC_CNTL_DIG_DBIAS_WAK_S 11
/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */
/*description: DIG_REG_DBIAS during sleep*/
#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007
#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V) << (RTC_CNTL_DIG_DBIAS_SLP_S))
#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7
#define RTC_CNTL_DIG_DBIAS_SLP_S 8
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_DIG_CAL_EN (BIT(7))
#define RTC_CNTL_DIG_CAL_EN_M (BIT(7))
#define RTC_CNTL_DIG_CAL_EN_V 0x1
#define RTC_CNTL_DIG_CAL_EN_S 7
#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088)
/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
@ -1755,6 +1754,23 @@ extern "C" {
#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0))
#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1
#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0
/* Useful groups of RTC_CNTL_PWC_REG bits */
#define RTC_CNTL_MEM_FORCE_ISO \
(RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO)
#define RTC_CNTL_MEM_FORCE_NOISO \
(RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
#define RTC_CNTL_MEM_PD_EN \
(RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN)
#define RTC_CNTL_MEM_FORCE_PU \
(RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
#define RTC_CNTL_MEM_FORCE_PD \
(RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD)
#define RTC_CNTL_MEM_FOLW_CPU \
(RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
#define RTC_CNTL_MEM_FORCE_LPU \
(RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU)
#define RTC_CNTL_MEM_FORCE_LPD \
(RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD)
#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C)
/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
@ -2077,7 +2093,7 @@ extern "C" {
#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8))
#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1
#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */
/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */
/*description: */
#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7))
@ -2251,6 +2267,12 @@ extern "C" {
#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V) << (RTC_CNTL_SWD_SIGNAL_WIDTH_S))
#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF
#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18
/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_SWD_BYPASS_RST (BIT(17))
#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17))
#define RTC_CNTL_SWD_BYPASS_RST_V 0x1
#define RTC_CNTL_SWD_BYPASS_RST_S 17
/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: swd interrupt for feeding*/
#define RTC_CNTL_SWD_FEED_INT (BIT(1))
@ -2679,6 +2701,12 @@ extern "C" {
#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29))
#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1
#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29
/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28))
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28))
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1
#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28
/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: 1: 4-pos reset*/
#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27))
@ -3568,8 +3596,30 @@ extern "C" {
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1
#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0
#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x013c)
/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1910211 ; */
#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x013c)
/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */
/*description: wait cycles for rention operation*/
#define RTC_CNTL_RETENTION_WAIT 0x0000001F
#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
#define RTC_CNTL_RETENTION_WAIT_V 0x1F
#define RTC_CNTL_RETENTION_WAIT_S 27
/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
/*description: */
#define RTC_CNTL_RETENTION_EN (BIT(26))
#define RTC_CNTL_RETENTION_EN_M (BIT(26))
#define RTC_CNTL_RETENTION_EN_V 0x1
#define RTC_CNTL_RETENTION_EN_S 26
#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140)
/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: select use analog fib signal*/
#define RTC_CNTL_FIB_SEL 0x00000007
#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
#define RTC_CNTL_FIB_SEL_V 0x7
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0144)
/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003251 ; */
/*description: */
#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF
#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V) << (RTC_CNTL_CNTL_DATE_S))