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Merge branch 'feature/c3_IDF-2554' into 'master'

Browse Source 
global: Uses CCOUNT API instead of XTHAL macro

Closes IDF-2554

See merge request espressif/esp-idf!11954
This commit is contained in:
Angus Gratton 2021-01-13 12:55:21 +08:00
commit f683db7aea
27 changed files with 78 additions and 47 deletions
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4
components/driver/sdio_slave.c
View File

@ -93,8 +93,8 @@ The driver of FIFOs works as below:
#include "freertos/FreeRTOS.h"
#include "soc/soc_memory_layout.h"
#include "soc/gpio_periph.h"
#include "hal/cpu_hal.h"
#include "freertos/semphr.h"
#include "xtensa/core-macros.h"
#include "driver/periph_ctrl.h"
#include "driver/gpio.h"
#include "hal/sdio_slave_hal.h"
@ -587,7 +587,7 @@ esp_err_t sdio_slave_send_get_finished(void** out_arg, TickType_t wait)
esp_err_t sdio_slave_transmit(uint8_t* addr, size_t len)
{
uint32_t timestamp = XTHAL_GET_CCOUNT();
uint32_t timestamp = cpu_hal_get_cycle_count();
uint32_t ret_stamp;
esp_err_t err = sdio_slave_send_queue(addr, len, (void*)timestamp, portMAX_DELAY);

5
components/driver/test/test_rmt.c
View File

@ -2,6 +2,7 @@
#include <stdio.h>
#include <string.h>
#include "sdkconfig.h"
#include "hal/cpu_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_log.h"
@ -429,9 +430,9 @@ static uint32_t tx_end_time0, tx_end_time1;
static void rmt_tx_end_cb(rmt_channel_t channel, void *arg)
{
if (channel == 0) {
tx_end_time0 = esp_cpu_get_ccount();
tx_end_time0 = cpu_hal_get_cycle_count();
} else {
tx_end_time1 = esp_cpu_get_ccount();
tx_end_time1 = cpu_hal_get_cycle_count();
}
}
TEST_CASE("RMT TX simultaneously", "[rmt]")

7
components/esp32/dport_access.c
View File

@ -29,14 +29,13 @@
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/spi_periph.h"
#include "hal/cpu_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "xtensa/core-macros.h"
#include "sdkconfig.h"
#ifndef CONFIG_FREERTOS_UNICORE
@ -78,7 +77,7 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
int cpu_id = xPortGetCoreID();
#ifdef DPORT_ACCESS_BENCHMARK
ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
ccount_start[cpu_id] = cpu_hal_get_cycle_count();
#endif
if (dport_access_ref[cpu_id] == 0) {
@ -135,7 +134,7 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
}
#ifdef DPORT_ACCESS_BENCHMARK
ccount_end[cpu_id] = XTHAL_GET_CCOUNT();
ccount_end[cpu_id] = cpu_hal_get_cycle_count();
ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
#endif

4
components/esp32/hw_random.c
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@ -18,9 +18,9 @@
#include <string.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "hal/cpu_hal.h"
#include "esp32/clk.h"
#include "soc/wdev_reg.h"
#include "xtensa/core-macros.h"
uint32_t IRAM_ATTR esp_random(void)
{
@ -48,7 +48,7 @@ uint32_t IRAM_ATTR esp_random(void)
uint32_t ccount;
uint32_t result = 0;
do {
ccount = XTHAL_GET_CCOUNT();
ccount = cpu_hal_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;

7
components/esp32/test/test_dport.c
View File

@ -17,6 +17,7 @@
#include "hal/uart_ll.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "hal/cpu_hal.h"
#include "esp_intr_alloc.h"
#include "driver/timer.h"
@ -356,7 +357,7 @@ static void accessDPORT2_stall_other_cpu(void *pvParameters)
dport_test_result = true;
while (exit_flag == false) {
DPORT_STALL_OTHER_CPU_START();
XTHAL_SET_CCOMPARE(2, XTHAL_GET_CCOUNT());
XTHAL_SET_CCOMPARE(2, cpu_hal_get_cycle_count());
xt_highint5_read_apb = 1;
for (int i = 0; i < 200; ++i) {
if (_DPORT_REG_READ(DPORT_DATE_REG) != _DPORT_REG_READ(DPORT_DATE_REG)) {
@ -393,7 +394,7 @@ static void accessDPORT2(void *pvParameters)
TEST_ESP_OK(esp_intr_alloc(ETS_INTERNAL_TIMER2_INTR_SOURCE, ESP_INTR_FLAG_LEVEL5 | ESP_INTR_FLAG_IRAM, NULL, NULL, &inth));
while (exit_flag == false) {
XTHAL_SET_CCOMPARE(2, XTHAL_GET_CCOUNT() + 21);
XTHAL_SET_CCOMPARE(2, cpu_hal_get_cycle_count() + 21);
for (int i = 0; i < 200; ++i) {
if (DPORT_REG_READ(DPORT_DATE_REG) != DPORT_REG_READ(DPORT_DATE_REG)) {
dport_test_result = false;
@ -441,7 +442,7 @@ static uint32_t IRAM_ATTR test_dport_access_reg_read(uint32_t reg)
#else
uint32_t apb;
unsigned int intLvl;
XTHAL_SET_CCOMPARE(2, XTHAL_GET_CCOUNT() + s_shift_counter);
XTHAL_SET_CCOMPARE(2, cpu_hal_get_cycle_count() + s_shift_counter);
__asm__ __volatile__ (\
/* "movi %[APB], "XTSTR(0x3ff40078)"\n" */ /* (1) uncomment for reproduce issue */ \
"bnez %[APB], kl1\n" /* this branch command helps get good reproducing */ \

4
components/esp32s2/hw_random.c
View File

@ -18,9 +18,9 @@
#include <string.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "hal/cpu_hal.h"
#include "esp32s2/clk.h"
#include "soc/wdev_reg.h"
#include "xtensa/core-macros.h"
uint32_t IRAM_ATTR esp_random(void)
{
@ -48,7 +48,7 @@ uint32_t IRAM_ATTR esp_random(void)
uint32_t ccount;
uint32_t result = 0;
do {
ccount = XTHAL_GET_CCOUNT();
ccount = cpu_hal_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;

4
components/esp32s3/hw_random.c
View File

@ -18,9 +18,9 @@
#include <string.h>
#include <sys/param.h>
#include "esp_attr.h"
#include "hal/cpu_hal.h"
#include "esp32s3/clk.h"
#include "soc/wdev_reg.h"
#include "xtensa/core-macros.h"
uint32_t IRAM_ATTR esp_random(void)
{
@ -48,7 +48,7 @@ uint32_t IRAM_ATTR esp_random(void)
uint32_t ccount;
uint32_t result = 0;
do {
ccount = XTHAL_GET_CCOUNT();
ccount = cpu_hal_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
last_ccount = ccount;

5
components/esp_hw_support/include/soc/cpu.h
View File

@ -99,6 +99,11 @@ static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
return cpu_hal_get_cycle_count();
}
static inline void esp_cpu_set_ccount(esp_cpu_ccount_t val)
{
cpu_hal_set_cycle_count(val);
}
/**
* @brief Configure CPU to disable access to invalid memory regions
*

2
components/esp_hw_support/port/esp32/rtc_clk.c
View File

@ -27,11 +27,11 @@
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/gpio_struct.h"
#include "hal/cpu_hal.h"
#include "hal/gpio_ll.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "sdkconfig.h"
#include "xtensa/core-macros.h"
#include "rtc_clk_common.h"
/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */

4
components/esp_hw_support/port/esp32/rtc_clk_init.c
View File

@ -23,10 +23,10 @@
#include "soc/sens_periph.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "sdkconfig.h"
#include "xtensa/core-macros.h"
#include "rtc_clk_common.h"
/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
@ -124,7 +124,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */
/* Re-calculate the ccount to make time calculation correct. */
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {

4
components/esp_hw_support/port/esp32c3/rtc_clk_init.c
View File

@ -24,6 +24,7 @@
#include "soc/sens_periph.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "sdkconfig.h"
@ -64,6 +65,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
/* Set CPU frequency */
rtc_clk_cpu_freq_get_config(&old_config);
uint32_t freq_before = old_config.freq_mhz;
bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
if (!res) {
SOC_LOGE(TAG, "invalid CPU frequency value");
@ -72,7 +74,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
rtc_clk_cpu_freq_set_config(&new_config);
/* Re-calculate the ccount to make time calculation correct. */
//XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {

1
components/esp_hw_support/port/esp32s2/rtc_clk.c
View File

@ -31,7 +31,6 @@
#include "soc_log.h"
#include "rtc_clk_common.h"
#include "sdkconfig.h"
#include "xtensa/core-macros.h"
static const char *TAG = "rtc_clk";

4
components/esp_hw_support/port/esp32s2/rtc_clk_init.c
View File

@ -23,10 +23,10 @@
#include "soc/sens_periph.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "sdkconfig.h"
#include "xtensa/core-macros.h"
#include "rtc_clk_common.h"
static const char* TAG = "rtc_clk_init";
@ -72,7 +72,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
rtc_clk_cpu_freq_set_config(&new_config);
/* Re-calculate the ccount to make time calculation correct. */
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {

1
components/esp_hw_support/port/esp32s3/rtc_clk.c
View File

@ -32,7 +32,6 @@
#include "soc_log.h"
#include "rtc_clk_common.h"
#include "sdkconfig.h"
#include "xtensa/core-macros.h"
static const char *TAG = "rtc_clk";

4
components/esp_hw_support/port/esp32s3/rtc_clk_init.c
View File

@ -21,9 +21,9 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "hal/cpu_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "xtensa/core-macros.h"
#include "rtc_clk_common.h"
static const char *TAG = "rtc_clk_init";
@ -69,7 +69,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
rtc_clk_cpu_freq_set_config(&new_config);
/* Re-calculate the ccount to make time calculation correct. */
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {

6
components/esp_pm/pm_impl.c
View File

@ -25,7 +25,7 @@
#include "esp_private/crosscore_int.h"
#include "soc/rtc.h"
#include "hal/cpu_hal.h"
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
@ -460,7 +460,7 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
*/
static void IRAM_ATTR update_ccompare(void)
{
uint32_t ccount = XTHAL_GET_CCOUNT();
uint32_t ccount = cpu_hal_get_cycle_count();
uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
if ((ccompare - CCOMPARE_MIN_CYCLES_IN_FUTURE) - ccount < UINT32_MAX / 2) {
uint32_t diff = ccompare - ccount;
@ -636,7 +636,7 @@ void IRAM_ATTR vApplicationSleep( TickType_t xExpectedIdleTime )
* work for timer interrupt, and changing CCOMPARE would clear
* the interrupt flag.
*/
XTHAL_SET_CCOUNT(XTHAL_GET_CCOMPARE(XT_TIMER_INDEX) - 16);
cpu_hal_set_cycle_count(XTHAL_GET_CCOMPARE(XT_TIMER_INDEX) - 16);
while (!(XTHAL_GET_INTERRUPT() & BIT(XT_TIMER_INTNUM))) {
;
}

4
components/esp_system/port/soc/esp32/clk.c
View File

@ -16,8 +16,8 @@
#include "soc/rtc.h"
#include "soc/dport_reg.h"
#include "soc/dport_access.h"
#include "xtensa/core-macros.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "driver/periph_ctrl.h"
#include "bootloader_clock.h"
#include "hal/wdt_hal.h"
@ -195,7 +195,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
/* This function is not exposed as an API at this point.

7
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -30,9 +30,9 @@
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "hal/wdt_hal.h"
#include "driver/periph_ctrl.h"
//#include "xtensa/core-macros.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
#include "esp_rom_uart.h"
@ -118,7 +118,7 @@ static const char *TAG = "clk";
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
//const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t old_freq_mhz = old_config.freq_mhz;
const uint32_t new_freq_mhz = CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ;
bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
@ -131,8 +131,7 @@ static const char *TAG = "clk";
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
// TODO ESP32-C3 IDF-2554 apply same adjustment
//XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)

6
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -28,11 +28,11 @@
#include "soc/dport_access.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "hal/wdt_hal.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "hal/wdt_hal.h"
#include "driver/periph_ctrl.h"
#include "xtensa/core-macros.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
@ -138,7 +138,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)

6
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -29,11 +29,11 @@
#include "soc/dport_access.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "hal/wdt_hal.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/cpu_hal.h"
#include "hal/wdt_hal.h"
#include "driver/periph_ctrl.h"
#include "xtensa/core-macros.h"
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
@ -134,7 +134,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
rtc_clk_cpu_freq_set_config(&new_config);
// Re calculate the ccount to make time calculation correct.
XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz );
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)

5
components/hal/esp32/include/hal/cpu_ll.h
View File

@ -46,6 +46,11 @@ static inline uint32_t cpu_ll_get_cycle_count(void)
return result;
}
static inline void IRAM_ATTR cpu_ll_set_cycle_count(uint32_t val)
{
WSR(CCOUNT, val);
}
static inline void* cpu_ll_get_sp(void)
{
void *sp;

5
components/hal/esp32c3/include/hal/cpu_ll.h
View File

@ -55,6 +55,11 @@ static inline uint32_t IRAM_ATTR cpu_ll_get_cycle_count(void)
return result;
}
static inline void IRAM_ATTR cpu_ll_set_cycle_count(uint32_t val)
{
RV_WRITE_CSR(CSR_PCCR_MACHINE, val);
}
static inline void* cpu_ll_get_sp(void)
{
void *sp;

5
components/hal/esp32s2/include/hal/cpu_ll.h
View File

@ -40,6 +40,11 @@ static inline uint32_t cpu_ll_get_cycle_count(void)
return result;
}
static inline void IRAM_ATTR cpu_ll_set_cycle_count(uint32_t val)
{
WSR(CCOUNT, val);
}
static inline void* cpu_ll_get_sp(void)
{
void *sp;

5
components/hal/esp32s3/include/hal/cpu_ll.h
View File

@ -45,6 +45,11 @@ static inline uint32_t cpu_ll_get_cycle_count(void)
return result;
}
static inline void IRAM_ATTR cpu_ll_set_cycle_count(uint32_t val)
{
WSR(CCOUNT, val);
}
static inline void *cpu_ll_get_sp(void)
{
void *sp;

6
components/hal/include/hal/cpu_hal.h
View File

@ -49,6 +49,12 @@ extern "C" {
*/
#define cpu_hal_get_cycle_count() cpu_ll_get_cycle_count()
/**
* Set the given value into the internal counter that increments
* every processor-clock cycle.
*/
#define cpu_hal_set_cycle_count(val) cpu_ll_set_cycle_count(val)
/**
* Check if some form of debugger is attached to CPU.
*

6
components/log/log_freertos.c
View File

@ -18,7 +18,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "soc/cpu.h" // for esp_cpu_get_ccount()
#include "hal/cpu_hal.h" // for cpu_hal_get_cycle_count()
#include "esp_log.h"
#include "esp_log_private.h"
@ -109,8 +109,8 @@ uint32_t esp_log_early_timestamp(void)
#if CONFIG_IDF_TARGET_ESP32
/* ESP32 ROM stores separate clock rate values for each CPU, but we want the PRO CPU value always */
extern uint32_t g_ticks_per_us_pro;
return esp_cpu_get_ccount() / (g_ticks_per_us_pro * 1000);
return cpu_hal_get_cycle_count() / (g_ticks_per_us_pro * 1000);
#else
return esp_cpu_get_ccount() / (ets_get_cpu_frequency() * 1000);
return cpu_hal_get_cycle_count() / (ets_get_cpu_frequency() * 1000);
#endif
}

4
components/log/log_noos.c
View File

@ -14,7 +14,7 @@
#include <assert.h>
#include "esp_log_private.h"
#include "soc/cpu.h" // for esp_cpu_get_ccount()
#include "hal/cpu_hal.h" // for cpu_hal_get_cycle_count()
static int s_lock = 0;
@ -40,7 +40,7 @@ void esp_log_impl_unlock(void)
uint32_t esp_log_early_timestamp(void)
{
extern uint32_t ets_get_cpu_frequency(void);
return esp_cpu_get_ccount() / (ets_get_cpu_frequency() * 1000);
return cpu_hal_get_cycle_count() / (ets_get_cpu_frequency() * 1000);
}
uint32_t esp_log_timestamp(void) __attribute__((alias("esp_log_early_timestamp")));