alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

fix unit test and examples for s2beta

Browse Source
This commit is contained in:
Michael (XIAO Xufeng) 2019-08-06 17:59:26 +08:00 committed by Angus Gratton
parent 5b6bd40bc6
commit 9baa7826be
55 changed files with 1782 additions and 487 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
components/app_update/test/test_switch_ota.c
View File

@ -7,9 +7,13 @@
#include "string.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/spi_flash.h"
#include "esp32s2beta/rom/rtc.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

1
components/bootloader_support/test/test_verify_image.c
View File

@ -5,7 +5,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "string.h"
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

12
components/driver/test/CMakeLists.txt
View File

@ -1,3 +1,9 @@
idf_component_register(SRC_DIRS "." "param_test"
INCLUDE_DIRS "include" "param_test/include"
REQUIRES unity test_utils driver nvs_flash)
set(srcdirs . param_test)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS include param_test/include
REQUIRES unity test_utils driver nvs_flash
)

1
components/driver/test/component.mk
View File

@ -2,6 +2,7 @@
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_SRCDIRS += param_test
COMPONENT_PRIV_INCLUDEDIRS += param_test/include

9
components/driver/test/test_gpio.c → components/driver/test/esp32/test_gpio.c
View File

@ -4,7 +4,7 @@
*/
#include <stdio.h>
#include <string.h>
#include "esp32/rom/uart.h"
#include "esp_system.h"
#include "esp_sleep.h"
#include "unity.h"
@ -12,6 +12,13 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/uart.h"
#endif
#define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated.
#define GPIO_OUTPUT_IO 18 // default output GPIO

187
components/driver/test/esp32/test_i2s.c Normal file
View File

@ -0,0 +1,187 @@
/**
* I2S test environment UT_T1_I2S:
* connect GPIO18 and GPIO19, GPIO25 and GPIO26, GPIO21 and GPIO22
*/
#include <stdio.h>
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/i2s.h"
#include "unity.h"
#define SAMPLE_RATE (36000)
#define SAMPLE_BITS (16)
#define MASTER_BCK_IO 18
#define MASTER_WS_IO 25
#define SLAVE_BCK_IO 19
#define SLAVE_WS_IO 26
#define DATA_IN_IO 21
#define DATA_OUT_IO 22
TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t master_pin_config = {
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
i2s_config_t slave_i2s_config = {
.mode = I2S_MODE_SLAVE | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t slave_pin_config = {
.bck_io_num = SLAVE_BCK_IO,
.ws_io_num = SLAVE_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO,
};
// slave driver installed and receive data
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
uint8_t* data_wr = (uint8_t*)malloc(sizeof(uint8_t)*400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t*)malloc(sizeof(uint8_t)*10000);
for(int i=0; i<100; i++) {
data_wr[i] = i+1;
}
int flag=0; // break loop flag
int end_position = 0;
// write data to slave
i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t)*400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
while(!flag){
i2s_read(I2S_NUM_1, i2s_read_buff + length, sizeof(uint8_t)*500, &bytes_read, 1000/portMAX_DELAY);
if(bytes_read>0) {
printf("read data size: %d\n", bytes_read);
for(int i=length; i<length + bytes_read; i++) {
if(i2s_read_buff[i] == 100) {
flag=1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the readed data right or not
for(int i=end_position-99; i<=end_position; i++) {
TEST_ASSERT(*(i2s_read_buff + i) == (i-end_position+100));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
i2s_driver_uninstall(I2S_NUM_1);
}
TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s][test_env=UT_T1_I2S]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t master_pin_config = {
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO,
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
i2s_config_t slave_i2s_config = {
.mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t slave_pin_config = {
.bck_io_num = SLAVE_BCK_IO,
.ws_io_num = SLAVE_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
// slave driver installed and receive data
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
uint8_t* data_wr = (uint8_t*)malloc(sizeof(uint8_t)*400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t*)malloc(sizeof(uint8_t)*100000);
for(int i=0; i<100; i++) {
data_wr[i] = i+1;
}
// slave write data to master
i2s_write(I2S_NUM_1, data_wr, sizeof(uint8_t)*400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
int flag=0; // break loop flag
int end_position = 0;
// write data to slave
while(!flag){
TEST_ESP_OK(i2s_read(I2S_NUM_0, i2s_read_buff + length, 10000-length, &bytes_read, 1000/portMAX_DELAY));
if(bytes_read > 0) {
for(int i=length; i<length+bytes_read; i++) {
if(i2s_read_buff[i] == 100) {
flag=1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the readed data right or not
for(int i=end_position-99; i<=end_position; i++) {
TEST_ASSERT(*(i2s_read_buff + i) == (i-end_position+100));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
i2s_driver_uninstall(I2S_NUM_1);
}

1
components/driver/test/test_ledc.c → components/driver/test/esp32/test_ledc.c
View File

@ -13,7 +13,6 @@
#include <stdlib.h>
#include <malloc.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

1
components/driver/test/test_pcnt.c → components/driver/test/esp32/test_pcnt.c
View File

@ -22,7 +22,6 @@
#include "esp_log.h"
#include "soc/gpio_periph.h"
#include "unity.h"
#include "esp32/rom/ets_sys.h"
#define PULSE_IO 18
#define PCNT_INPUT_IO 4

1
components/driver/test/test_pwm.c → components/driver/test/esp32/test_pwm.c
View File

@ -25,7 +25,6 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/rtc.h"
#include "esp32/rom/ets_sys.h"
#define GPIO_PWMA_OUT 4
#define GPIO_PWMB_OUT 13

39
components/driver/test/include/test/test_common_spi.h
View File

@ -13,9 +13,43 @@
// All the tests using the header should use this definition as much as possible,
// so that the working host can be changed easily in the future.
#if CONFIG_IDF_TARGET_ESP32
#define TEST_SPI_HOST HSPI_HOST
#define TEST_SLAVE_HOST VSPI_HOST
#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
#define SLAVE_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#define TEST_SPI_HOST FSPI_HOST
#define TEST_SLAVE_HOST HSPI_HOST
#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define SLAVE_PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#endif
#define FUNC_SPI 1
#define FUNC_GPIO 2
@ -52,11 +86,6 @@
0,\
}
#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
//default bus config for tests
#define SPI_BUS_TEST_DEFAULT_CONFIG() {\
.miso_io_num=PIN_NUM_MISO, \

166
components/driver/test/test_i2s.c
View File

@ -69,172 +69,6 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
}
TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t master_pin_config = {
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
i2s_config_t slave_i2s_config = {
.mode = I2S_MODE_SLAVE | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t slave_pin_config = {
.bck_io_num = SLAVE_BCK_IO,
.ws_io_num = SLAVE_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO,
};
// slave driver installed and receive data
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
uint8_t* data_wr = (uint8_t*)malloc(sizeof(uint8_t)*400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t*)malloc(sizeof(uint8_t)*10000);
for(int i=0; i<100; i++) {
data_wr[i] = i+1;
}
int flag=0; // break loop flag
int end_position = 0;
// write data to slave
i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t)*400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
while(!flag){
i2s_read(I2S_NUM_1, i2s_read_buff + length, sizeof(uint8_t)*500, &bytes_read, 1000/portMAX_DELAY);
if(bytes_read>0) {
printf("read data size: %d\n", bytes_read);
for(int i=length; i<length + bytes_read; i++) {
if(i2s_read_buff[i] == 100) {
flag=1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the readed data right or not
for(int i=end_position-99; i<=end_position; i++) {
TEST_ASSERT(*(i2s_read_buff + i) == (i-end_position+100));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
i2s_driver_uninstall(I2S_NUM_1);
}
TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s][test_env=UT_T1_I2S]")
{
// master driver installed and send data
i2s_config_t master_i2s_config = {
.mode = I2S_MODE_MASTER | I2S_MODE_RX,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t master_pin_config = {
.bck_io_num = MASTER_BCK_IO,
.ws_io_num = MASTER_WS_IO,
.data_out_num = -1,
.data_in_num = DATA_IN_IO,
};
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
i2s_config_t slave_i2s_config = {
.mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1 ,
};
i2s_pin_config_t slave_pin_config = {
.bck_io_num = SLAVE_BCK_IO,
.ws_io_num = SLAVE_WS_IO,
.data_out_num = DATA_OUT_IO,
.data_in_num = -1
};
// slave driver installed and receive data
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
uint8_t* data_wr = (uint8_t*)malloc(sizeof(uint8_t)*400);
size_t i2s_bytes_write = 0;
size_t bytes_read = 0;
int length = 0;
uint8_t *i2s_read_buff = (uint8_t*)malloc(sizeof(uint8_t)*100000);
for(int i=0; i<100; i++) {
data_wr[i] = i+1;
}
// slave write data to master
i2s_write(I2S_NUM_1, data_wr, sizeof(uint8_t)*400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
int flag=0; // break loop flag
int end_position = 0;
// write data to slave
while(!flag){
TEST_ESP_OK(i2s_read(I2S_NUM_0, i2s_read_buff + length, 10000-length, &bytes_read, 1000/portMAX_DELAY));
if(bytes_read > 0) {
for(int i=length; i<length+bytes_read; i++) {
if(i2s_read_buff[i] == 100) {
flag=1;
end_position = i;
break;
}
}
}
length = length + bytes_read;
}
// test the readed data right or not
for(int i=end_position-99; i<=end_position; i++) {
TEST_ASSERT(*(i2s_read_buff + i) == (i-end_position+100));
}
free(data_wr);
free(i2s_read_buff);
i2s_driver_uninstall(I2S_NUM_0);
i2s_driver_uninstall(I2S_NUM_1);
}
TEST_CASE("I2S memory leaking test", "[i2s]")
{
i2s_config_t master_i2s_config = {

7
components/driver/test/test_sdmmc_sdspi_init.cpp
View File

@ -1,4 +1,9 @@
#include "soc/soc_caps.h"
#if SOC_SDMMC_HOST_SUPPORTED
#include "driver/sdmmc_host.h"
#endif
#include "driver/sdspi_host.h"
@ -9,10 +14,12 @@ static void test_initializers() __attribute__((unused));
static void test_initializers()
{
#if SOC_SDMMC_HOST_SUPPORTED
sdmmc_host_t sdmmc_host = SDMMC_HOST_DEFAULT();
(void) sdmmc_host;
sdmmc_slot_config_t sdmmc_slot = SDMMC_SLOT_CONFIG_DEFAULT();
(void) sdmmc_slot;
#endif
sdmmc_host_t sdspi_host = SDSPI_HOST_DEFAULT();
(void) sdspi_host;
sdspi_slot_config_t sdspi_slot = SDSPI_SLOT_CONFIG_DEFAULT();

47
components/driver/test/test_spi_master.c
View File

@ -7,7 +7,6 @@
#include <stdlib.h>
#include <malloc.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -54,10 +53,12 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
t.tx_buffer=sendbuf;
ret=spi_device_transmit(handle, &t);
printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, SPI2.clock.clkdiv_pre+1, SPI2.clock.clkcnt_n+1);
spi_dev_t* hw = spi_periph_signal[TEST_SPI_HOST].hw;
TEST_ASSERT(SPI2.clock.clkcnt_n+1==n);
TEST_ASSERT(SPI2.clock.clkdiv_pre+1==pre);
printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre+1, hw->clock.clkcnt_n+1);
TEST_ASSERT(hw->clock.clkcnt_n+1==n);
TEST_ASSERT(hw->clock.clkdiv_pre+1==pre);
ret=spi_bus_remove_device(handle);
TEST_ASSERT(ret==ESP_OK);
@ -330,7 +331,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 6 iomux output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@ -339,7 +340,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 4 iomux output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@ -349,7 +350,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 6 output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@ -359,7 +360,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 4 output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@ -368,14 +369,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD;
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@ -383,14 +384,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@ -398,7 +399,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "check native flag for 6 output pins...");
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@ -406,61 +407,61 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "check native flag for 4 output pins...");
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check sclk flag...");
flags_expected = SPICOMMON_BUSFLAG_SCLK;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = -1, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check mosi flag...");
flags_expected = SPICOMMON_BUSFLAG_MOSI;
cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check miso flag...");
flags_expected = SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = -1, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check quad flag...");
flags_expected = SPICOMMON_BUSFLAG_QUAD;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));

66
components/driver/test/test_spi_param.c
View File

@ -55,20 +55,20 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p
assert(!pset->master_iomux || !pset->slave_iomux);
if (pset->slave_iomux) {
//only in this case, use VSPI iomux pins
buscfg.miso_io_num = VSPI_IOMUX_PIN_NUM_MISO;
buscfg.mosi_io_num = VSPI_IOMUX_PIN_NUM_MOSI;
buscfg.sclk_io_num = VSPI_IOMUX_PIN_NUM_CLK;
devcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS;
slvcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS;
buscfg.miso_io_num = spi_periph_signal[VSPI_HOST].spiq_iomux_pin;
buscfg.mosi_io_num = spi_periph_signal[VSPI_HOST].spid_iomux_pin;
buscfg.sclk_io_num = spi_periph_signal[VSPI_HOST].spiclk_iomux_pin;
devcfg.spics_io_num = spi_periph_signal[VSPI_HOST].spics0_iomux_pin;
slvcfg.spics_io_num = spi_periph_signal[VSPI_HOST].spics0_iomux_pin;
} else {
buscfg.miso_io_num = HSPI_IOMUX_PIN_NUM_MISO;
buscfg.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI;
buscfg.sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK;
devcfg.spics_io_num = HSPI_IOMUX_PIN_NUM_CS;
slvcfg.spics_io_num = HSPI_IOMUX_PIN_NUM_CS;
buscfg.miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin;
buscfg.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin;
buscfg.sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin;
devcfg.spics_io_num = spi_periph_signal[HSPI_HOST].spics0_iomux_pin;
slvcfg.spics_io_num = spi_periph_signal[HSPI_HOST].spics0_iomux_pin;
}
//this does nothing, but avoid the driver from using iomux pins if required
buscfg.quadhd_io_num = (!pset->master_iomux && !pset->slave_iomux ? VSPI_IOMUX_PIN_NUM_MISO : -1);
buscfg.quadhd_io_num = (!pset->master_iomux && !pset->slave_iomux ? spi_periph_signal[VSPI_HOST].spiq_iomux_pin : -1);
devcfg.mode = pset->mode;
const int cs_pretrans_max = 15;
if (pset->dup == HALF_DUPLEX_MISO) {
@ -100,20 +100,20 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p
//initialize master and slave on the same pins break some of the output configs, fix them
if (pset->master_iomux) {
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_SPI, HSPID_OUT_IDX);
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX);
spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_SPI, HSPICS0_OUT_IDX);
spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_SPI, HSPICLK_OUT_IDX);
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_SPI, spi_periph_signal[HSPI_HOST].spid_out);
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[VSPI_HOST].spiq_out);
spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_SPI, spi_periph_signal[HSPI_HOST].spics_out[0]);
spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_SPI, spi_periph_signal[HSPI_HOST].spiclk_out);
} else if (pset->slave_iomux) {
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX);
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_SPI, VSPIQ_OUT_IDX);
spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX);
spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, HSPICLK_OUT_IDX);
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[HSPI_HOST].spid_out);
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_SPI, spi_periph_signal[VSPI_HOST].spiq_out);
spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, spi_periph_signal[HSPI_HOST].spics_out[0]);
spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[HSPI_HOST].spiclk_out);
} else {
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX);
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX);
spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX);
spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, HSPICLK_OUT_IDX);
spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[HSPI_HOST].spid_out);
spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[VSPI_HOST].spiq_out);
spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, spi_periph_signal[HSPI_HOST].spics_out[0]);
spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[HSPI_HOST].spiclk_out);
}
//prepare slave tx data
@ -491,13 +491,13 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_
{
//master config
spi_bus_config_t buspset=SPI_BUS_TEST_DEFAULT_CONFIG();
buspset.miso_io_num = HSPI_IOMUX_PIN_NUM_MISO;
buspset.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI;
buspset.sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK;
buspset.miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin;
buspset.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin;
buspset.sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin;
//this does nothing, but avoid the driver from using native pins
if (!pset->master_iomux) buspset.quadhd_io_num = VSPI_IOMUX_PIN_NUM_MISO;
if (!pset->master_iomux) buspset.quadhd_io_num = spi_periph_signal[VSPI_HOST].spiq_iomux_pin;
spi_device_interface_config_t devpset=SPI_DEVICE_TEST_DEFAULT_CONFIG();
devpset.spics_io_num = HSPI_IOMUX_PIN_NUM_CS;
devpset.spics_io_num = spi_periph_signal[HSPI_HOST].spics0_iomux_pin;
devpset.mode = pset->mode;
const int cs_pretrans_max = 15;
if (pset->dup==HALF_DUPLEX_MISO) {
@ -623,13 +623,13 @@ static void timing_slave_start(int speed, const spitest_param_set_t* pset, spite
{
//slave config
spi_bus_config_t slv_buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
slv_buscfg.miso_io_num = VSPI_IOMUX_PIN_NUM_MISO;
slv_buscfg.mosi_io_num = VSPI_IOMUX_PIN_NUM_MOSI;
slv_buscfg.sclk_io_num = VSPI_IOMUX_PIN_NUM_CLK;
slv_buscfg.miso_io_num = spi_periph_signal[VSPI_HOST].spiq_iomux_pin;
slv_buscfg.mosi_io_num = spi_periph_signal[VSPI_HOST].spid_iomux_pin;
slv_buscfg.sclk_io_num = spi_periph_signal[VSPI_HOST].spiclk_iomux_pin;
//this does nothing, but avoid the driver from using native pins
if (!pset->slave_iomux) slv_buscfg.quadhd_io_num = HSPI_IOMUX_PIN_NUM_CLK;
if (!pset->slave_iomux) slv_buscfg.quadhd_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin;
spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG();
slvcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS;
slvcfg.spics_io_num = spi_periph_signal[VSPI_HOST].spics0_iomux_pin;
slvcfg.mode = pset->mode;
//Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected.
slave_pull_up(&slv_buscfg, slvcfg.spics_io_num);

12
components/driver/test/test_spi_sio.c
View File

@ -7,7 +7,6 @@
#include <stdlib.h>
#include <malloc.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -23,6 +22,7 @@
#include "test/test_common_spi.h"
#include "soc/gpio_periph.h"
#include "sdkconfig.h"
#include "hal/spi_ll.h"
/********************************************************************************
@ -34,10 +34,12 @@ TEST_CASE("local test sio", "[spi]")
WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
for (int i = 0; i < 16; i++) {
SPI1.data_buf[0] = 0xcccccccc;
SPI2.data_buf[0] = 0xcccccccc;
}
uint32_t padding[16];
for (int i = 0; i < 16; i++)
padding[i] = 0xcccccccc;;
spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SPI_HOST), (uint8_t*)&padding, 8*64);
spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SLAVE_HOST), (uint8_t*)&padding, 8*64);
/* This test use a strange connection to test the SIO mode:
* master spid -> slave spid

8
components/driver/test/test_spi_slave.c
View File

@ -88,10 +88,10 @@ TEST_CASE("test slave send unaligned","[spi]")
slave_init();
//do internal connection
int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, VSPIQ_IN_IDX );
int_connect( PIN_NUM_MISO, VSPIQ_OUT_IDX, HSPID_IN_IDX );
int_connect( PIN_NUM_CS, HSPICS0_OUT_IDX, VSPICS0_IN_IDX );
int_connect( PIN_NUM_CLK, HSPICLK_OUT_IDX, VSPICLK_IN_IDX );
int_connect( PIN_NUM_MOSI, spi_periph_signal[TEST_SPI_HOST].spid_out, spi_periph_signal[TEST_SLAVE_HOST].spiq_in );
int_connect( PIN_NUM_MISO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out, spi_periph_signal[TEST_SPI_HOST].spid_in );
int_connect( PIN_NUM_CS, spi_periph_signal[TEST_SPI_HOST].spics_out[0], spi_periph_signal[TEST_SLAVE_HOST].spics_in );
int_connect( PIN_NUM_CLK, spi_periph_signal[TEST_SPI_HOST].spiclk_out, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in );
for ( int i = 0; i < 4; i ++ ) {
//slave send

9
components/efuse/test/CMakeLists.txt
View File

@ -1,3 +1,6 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "include"
REQUIRES unity test_utils efuse bootloader_support)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS . include
REQUIRES unity test_utils efuse bootloader_support
)
endif()

25
components/esp32/test/CMakeLists.txt
View File

@ -1,16 +1,19 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}"
REQUIRES unity test_utils nvs_flash ulp esp_common)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
REQUIRES unity test_utils nvs_flash ulp esp_common
)
add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
WORKING_DIRECTORY ${COMPONENT_DIR}
DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg")
add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
WORKING_DIRECTORY ${COMPONENT_DIR}
DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg")
add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h")
add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h")
add_dependencies(${COMPONENT_LIB} esp32_test_logo)
add_dependencies(${COMPONENT_LIB} esp32_test_logo)
idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND)
idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND)
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")
endif()
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")

1
components/esp32/test/test_aes_sha_rsa.c
View File

@ -2,7 +2,6 @@
#include <stdlib.h>
#include <string.h>
#include "esp_types.h"
#include "esp32/clk.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

5
components/esp32/test/test_intr_alloc.c
View File

@ -4,8 +4,11 @@
#include <esp_types.h>
#include <stdio.h>
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

25
components/esp32/test/test_sleep.c
View File

@ -18,6 +18,7 @@
#include "test_utils.h"
#include "sdkconfig.h"
#define ESP_EXT0_WAKEUP_LEVEL_LOW 0
#define ESP_EXT0_WAKEUP_LEVEL_HIGH 1
@ -330,7 +331,7 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][igno
static float get_time_ms(void)
{
gettimeofday(&tv_stop, NULL);
float dt = (tv_stop.tv_sec - tv_start.tv_sec) * 1e3f +
(tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
return fabs(dt);
@ -343,20 +344,20 @@ static uint32_t get_cause(void)
return wakeup_cause;
}
// This test case verifies deactivation of trigger for wake up sources
// This test case verifies deactivation of trigger for wake up sources
TEST_CASE("disable source trigger behavior", "[deepsleep]")
{
float dt = 0;
printf("Setup timer and ext0 to wake up immediately from GPIO_13 \n");
// Setup ext0 configuration to wake up almost immediately
// The wakeup time is proportional to input capacitance * pullup resistance
ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13));
ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(GPIO_NUM_13, ESP_EXT0_WAKEUP_LEVEL_HIGH));
// Setup timer to wakeup with timeout
esp_sleep_enable_timer_wakeup(2000000);
@ -367,22 +368,22 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
dt = get_time_ms();
printf("Ext0 sleep time = %d \n", (int) dt);
// Check wakeup from Ext0 using time measurement because wakeup cause is
// Check wakeup from Ext0 using time measurement because wakeup cause is
// not available in light sleep mode
TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt);
TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0);
// Disable Ext0 source. Timer source should be triggered
ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0));
printf("Disable ext0 trigger and leave timer active.\n");
gettimeofday(&tv_start, NULL);
esp_light_sleep_start();
dt = get_time_ms();
printf("Timer sleep time = %d \n", (int) dt);
TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt);
// Additionally check wakeup cause
@ -407,8 +408,8 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt);
TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0);
// Check error message when source is already disabled
// Check error message when source is already disabled
esp_err_t err_code = esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TIMER);
TEST_ASSERT(err_code == ESP_ERR_INVALID_STATE);
}
@ -429,7 +430,7 @@ static void trigger_deepsleep(void)
// Save start time. Deep sleep.
gettimeofday(&start, NULL);
esp_sleep_enable_timer_wakeup(1000);
// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
// to prevent a negative time after wake up.
esp_deep_sleep_start();
}

8
components/esp_eth/test/CMakeLists.txt
View File

@ -1,3 +1,5 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
PRIV_REQUIRES "unity" "test_utils" "esp_eth")
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS .
PRIV_REQUIRES unity test_utils esp_eth)
endif()

11
components/esp_event/test/CMakeLists.txt
View File

@ -1,3 +1,8 @@
idf_component_register(SRC_DIRS "."
PRIV_INCLUDE_DIRS "../private_include" "."
REQUIRES unity test_utils esp_event driver)
set(srcdirs .)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
PRIV_INCLUDE_DIRS . ../private_include
PRIV_REQUIRES unity test_utils esp_event driver)

2
components/esp_event/test/component.mk
View File

@ -1,5 +1,7 @@
#
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_PRIV_INCLUDEDIRS := ../private_include .
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

1220
components/esp_event/test/esp32/test_event.c Normal file
View File

File diff suppressed because it is too large Load Diff

77
components/esp_event/test/test_event.c
View File

@ -278,44 +278,6 @@ static void test_teardown(void)
#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds
#define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer
#if CONFIG_ESP_EVENT_POST_FROM_ISR
static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data)
{
SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg;
// Event data is just the address value (maybe have been truncated due to casting).
int *data = (int*) event_data;
TEST_ASSERT_EQUAL(*data, (int) (*sem));
xSemaphoreGive(*sem);
}
#endif
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "test_event_on_timer_alarm not ported to esp32s2beta"
#else
#if CONFIG_ESP_EVENT_POST_FROM_ISR
void IRAM_ATTR test_event_on_timer_alarm(void* para)
{
/* Retrieve the interrupt status and the counter value
from the timer that reported the interrupt */
uint64_t timer_counter_value =
timer_group_get_counter_value_in_isr(TIMER_GROUP_0, TIMER_0);
timer_group_intr_clr_in_isr(TIMER_GROUP_0, TIMER_0);
timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE);
timer_group_set_alarm_value_in_isr(TIMER_GROUP_0, TIMER_0, timer_counter_value);
int data = (int) para;
// Posting events with data more than 4 bytes should fail.
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, 5, NULL));
// This should succeedd, as data is int-sized. The handler for the event checks that the passed event data
// is correct.
BaseType_t task_unblocked;
TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, sizeof(data), &task_unblocked));
if (task_unblocked == pdTRUE) {
portYIELD_FROM_ISR();
}
}
#endif //CONFIG_ESP_EVENT_POST_FROM_ISR
#endif //CONFIG_IDF_TARGET_ESP32S2BETA
TEST_CASE("can create and delete event loops", "[event]")
{
@ -1188,45 +1150,6 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]")
TEST_TEARDOWN();
}
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "can post events from interrupt handler not ported to esp32s2beta"
#else
TEST_CASE("can post events from interrupt handler", "[event]")
{
SemaphoreHandle_t sem = xSemaphoreCreateBinary();
/* Select and initialize basic parameters of the timer */
timer_config_t config;
config.divider = TIMER_DIVIDER;
config.counter_dir = TIMER_COUNT_UP;
config.counter_en = TIMER_PAUSE;
config.alarm_en = TIMER_ALARM_EN;
config.intr_type = TIMER_INTR_LEVEL;
config.auto_reload = false;
timer_init(TIMER_GROUP_0, TIMER_0, &config);
/* Timer's counter will initially start from value below.
Also, if auto_reload is set, this value will be automatically reload on alarm */
timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL);
/* Configure the alarm value and the interrupt on alarm. */
timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, TIMER_INTERVAL0_SEC * TIMER_SCALE);
timer_enable_intr(TIMER_GROUP_0, TIMER_0);
timer_isr_register(TIMER_GROUP_0, TIMER_0, test_event_on_timer_alarm,
(void *) sem, ESP_INTR_FLAG_IRAM, NULL);
timer_start(TIMER_GROUP_0, TIMER_0);
TEST_SETUP();
TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register(s_test_base1, TEST_EVENT_BASE1_EV1,
test_handler_post_from_isr, &sem));
xSemaphoreTake(sem, portMAX_DELAY);
TEST_TEARDOWN();
}
#endif // CONFIG_IDF_TARGET_ESP32S2BETA
#endif // CONFIG_ESP_EVENT_POST_FROM_ISR
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING

12
components/esp_wifi/test/CMakeLists.txt
View File

@ -1,6 +1,12 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}"
REQUIRES unity test_utils nvs_flash ulp esp_common)
set(srcdirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
REQUIRES unity test_utils nvs_flash ulp esp_common
)
idf_component_get_property(esp_wifi_dir esp_wifi COMPONENT_DIR)

1
components/esp_wifi/test/component.mk
View File

@ -5,6 +5,7 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_SRCDIRS := .
COMPONENT_SRCDIRS += esp32
# Calculate MD5 value of header file esp_wifi_os_adapter.h
WIFI_OS_ADAPTER_MD5_VAL=\"$(shell md5sum $(IDF_PATH)/components/esp_wifi/include/esp_private/wifi_os_adapter.h | cut -c 1-7)\"

21
components/esp_wifi/test/test_phy_rtc.c → components/esp_wifi/test/esp32/test_phy_rtc.c
View File

@ -11,18 +11,23 @@
#include <freertos/FreeRTOS.h>
#include <freertos/task.h>
#include <freertos/semphr.h>
#include "soc/soc_caps.h"
//Function just extern, need not test
#ifdef SOC_BT_SUPPORTED
extern void bt_bb_init_cmplx(void);
#endif
extern void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void);
extern void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void);
//Functions in librtc.a called by WIFI or Blutooth directly in ISR
#ifdef SOC_BT_SUPPORTED
extern void bt_bb_init_cmplx_reg(void);
extern void bt_track_pll_cap(void);
#endif
extern void force_wifi_mode(int);
extern void unforce_wifi_mode(void);
extern void bt_track_pll_cap(void);
static const char* TAG = "test_phy_rtc";
@ -39,7 +44,9 @@ static void test_phy_rtc_init(void)
}
TEST_ESP_OK(ret);
#ifdef SOC_BT_SUPPORTED
esp_phy_load_cal_and_init(PHY_BT_MODULE);
#endif
esp_phy_load_cal_and_init(PHY_WIFI_MODULE);
//must run here, not blocking in above code
@ -51,11 +58,6 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
{
test_phy_rtc_init();
ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()...");
spi_flash_disable_interrupts_caches_and_other_cpu();
bt_bb_init_cmplx_reg();
spi_flash_enable_interrupts_caches_and_other_cpu();
for (int i = 0; i < 2; i++) {
ESP_LOGI(TAG, "Test force_wifi_mode(%d)...", i);
spi_flash_disable_interrupts_caches_and_other_cpu();
@ -68,10 +70,17 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
spi_flash_enable_interrupts_caches_and_other_cpu();
}
#ifdef SOC_BT_SUPPORTED
ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()...");
spi_flash_disable_interrupts_caches_and_other_cpu();
bt_bb_init_cmplx_reg();
spi_flash_enable_interrupts_caches_and_other_cpu();
ESP_LOGI(TAG, "Test bt_track_pll_cap()...");
spi_flash_disable_interrupts_caches_and_other_cpu();
bt_track_pll_cap();
spi_flash_enable_interrupts_caches_and_other_cpu();
#endif
TEST_ASSERT( xSemaphoreGive(semphr_done) );

14
components/fatfs/test/CMakeLists.txt
View File

@ -1,4 +1,10 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils vfs fatfs
EMBED_TXTFILES fatfs.img)
set(srcdirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS .
REQUIRES unity test_utils vfs fatfs
EMBED_TXTFILES fatfs.img
)

1
components/fatfs/test/component.mk
View File

@ -1,2 +1,3 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_EMBED_TXTFILES := fatfs.img
COMPONENT_SRCDIRS += esp32

2
components/fatfs/test/test_fatfs_sdmmc.c → components/fatfs/test/esp32/test_fatfs_sdmmc.c
View File

@ -29,7 +29,7 @@
#include "driver/sdmmc_defs.h"
#include "sdmmc_cmd.h"
#include "ff.h"
#include "test_fatfs_common.h"
#include "../test_fatfs_common.h"
static void test_setup(void)

14
components/freertos/test/CMakeLists.txt
View File

@ -1,3 +1,11 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils)
set(srcdirs .)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs esp32)
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS .
REQUIRES unity test_utils
)

1
components/freertos/test/component.mk
View File

@ -2,4 +2,5 @@
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

6
components/freertos/test/test_freertos_task_delay_until.c → components/freertos/test/esp32/test_freertos_task_delay_until.c
View File

@ -27,10 +27,6 @@
static SemaphoreHandle_t task_delete_semphr;
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "Test not ported to esp32s2beta"
#else
static void delaying_task(void* arg)
{
uint64_t ref_prev, ref_current;
@ -76,5 +72,3 @@ TEST_CASE("Test vTaskDelayUntil", "[freertos]")
vSemaphoreDelete(task_delete_semphr);
ref_clock_deinit();
}
#endif // CONFIG_IDF_TARGET_ESP32S2BETA

1
components/heap/test/test_malloc.c
View File

@ -4,7 +4,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

1
components/newlib/test/test_time.c
View File

@ -9,7 +9,6 @@
#include "freertos/semphr.h"
#include "sdkconfig.h"
#include "soc/rtc.h"
#include "esp32/clk.h"
#include "esp_system.h"
#include "test_utils.h"

8
components/sdmmc/test/CMakeLists.txt
View File

@ -1,3 +1,5 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity sdmmc)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity sdmmc)
endif()

2
components/sdmmc/test/test_sdio.c
View File

@ -40,7 +40,6 @@
/* TODO: add SDIO slave header files, remove these definitions */
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_SLC_MASK 0xfffffc00
#define SLCCONF1 (DR_REG_SLC_BASE + 0x60)
@ -52,7 +51,6 @@
#define SLC_SLC0_TXLINK_RESTART (BIT(30))
#define SLC_SLC0_TXLINK_START (BIT(29))
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_SLCHOST_MASK 0xfffffc00
#define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64)
#define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C)

6
components/spi_flash/test/CMakeLists.txt
View File

@ -1,3 +1,7 @@
idf_component_register(SRC_DIRS "."
set(src_dirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND src_dirs "esp32")
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS "."
REQUIRES unity test_utils spi_flash bootloader_support app_update)

1
components/spi_flash/test/component.mk
View File

@ -2,4 +2,5 @@
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

0
components/spi_flash/test/test_esp_flash.c → components/spi_flash/test/esp32/test_esp_flash.c
View File

16
components/ulp/test/CMakeLists.txt
View File

@ -1,8 +1,10 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity ulp soc esp_common)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS esp32
INCLUDE_DIRS .
REQUIRES unity ulp soc esp_common)
set(ulp_app_name ulp_test_app)
set(ulp_s_sources "ulp/test_jumps.S")
set(ulp_exp_dep_srcs "test_ulp_as.c")
ulp_embed_binary(${ulp_app_name} ${ulp_s_sources} ${ulp_exp_dep_srcs})
set(ulp_app_name ulp_test_app)
set(ulp_s_sources "ulp/test_jumps_esp32.S")
set(ulp_exp_dep_srcs "esp32/test_ulp_as.c")
ulp_embed_binary(${ulp_app_name} ${ulp_s_sources} ${ulp_exp_dep_srcs})
endif()

8
components/ulp/test/component.mk
View File

@ -1,11 +1,13 @@
ULP_APP_NAME = ulp_test_app
COMPONENT_SRCDIRS += esp32
ULP_S_SOURCES = $(addprefix $(COMPONENT_PATH)/ulp/, \
test_jumps.S \
test_jumps_esp32.S \
)
ULP_EXP_DEP_OBJECTS := test_ulp_as.o
ULP_EXP_DEP_OBJECTS := esp32/test_ulp_as.o
include $(IDF_PATH)/components/ulp/component_ulp_common.mk
COMPONENT_ADD_LDFLAGS += -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

0
components/ulp/test/test_ulp.c → components/ulp/test/esp32/test_ulp.c
View File

0
components/ulp/test/test_ulp_as.c → components/ulp/test/esp32/test_ulp_as.c
View File

0
components/ulp/test/ulp/test_jumps.S → components/ulp/test/ulp/test_jumps_esp32.S
View File

14
components/vfs/test/CMakeLists.txt
View File

@ -1,4 +1,10 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils vfs fatfs spiffs
LDFRAGMENTS linker.lf)
set(srcdirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS .
REQUIRES unity test_utils vfs fatfs spiffs
LDFRAGMENTS linker.lf
)

1
components/vfs/test/component.mk
View File

@ -1,3 +1,4 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFRAGMENTS += linker.lf

0
components/vfs/test/test_vfs_uart.c → components/vfs/test/esp32/test_vfs_uart.c
View File

15
components/wear_levelling/test/CMakeLists.txt
View File

@ -1,4 +1,11 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils wear_levelling
EMBED_FILES test_partition_v1.bin)
set(srcdirs .)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs esp32)
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS .
REQUIRES unity test_utils wear_levelling
EMBED_FILES test_partition_v1.bin
)

1
components/wear_levelling/test/component.mk
View File

@ -1,2 +1,3 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_EMBED_FILES := test_partition_v1.bin
COMPONENT_SRCDIRS += esp32

88
components/wear_levelling/test/esp32/test_wl.c Normal file
View File

@ -0,0 +1,88 @@
#include <string.h>
#include "unity.h"
#include "wear_levelling.h"
#include "test_utils.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portable.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "soc/cpu.h"
#include "esp32/clk.h"
#define TEST_SECTORS_COUNT 8
static void check_mem_data(wl_handle_t handle, uint32_t init_val, uint32_t* buff)
{
size_t sector_size = wl_sector_size(handle);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
TEST_ESP_OK(wl_read(handle, sector_size * m, buff, sector_size));
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
uint32_t compare_val = init_val + i + m*sector_size;
TEST_ASSERT_EQUAL( buff[i], compare_val);
}
}
}
// We write complete memory with defined data
// And then write one sector many times.
// A data in other secors should be the same.
// We do this also with unmount
TEST_CASE("multiple write is correct", "[wear_levelling]")
{
const esp_partition_t *partition = get_test_data_partition();
esp_partition_t fake_partition;
memcpy(&fake_partition, partition, sizeof(fake_partition));
fake_partition.size = SPI_FLASH_SEC_SIZE*(4 + TEST_SECTORS_COUNT);
wl_handle_t handle;
TEST_ESP_OK(wl_mount(&fake_partition, &handle));
size_t sector_size = wl_sector_size(handle);
// Erase 8 sectors
TEST_ESP_OK(wl_erase_range(handle, 0, sector_size * TEST_SECTORS_COUNT));
// Write data to all sectors
printf("Check 1 sector_size=0x%08x\n", sector_size);
// Set initial random value
uint32_t init_val = rand();
uint32_t* buff = (uint32_t*)malloc(sector_size);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + m*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*m, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*m, buff, sector_size));
}
check_mem_data(handle, init_val, buff);
uint32_t start;
RSR(CCOUNT, start);
for (int m=0 ; m< 100000 ; m++) {
uint32_t sector = m % TEST_SECTORS_COUNT;
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + sector*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*sector, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*sector, buff, sector_size));
check_mem_data(handle, init_val, buff);
uint32_t end;
RSR(CCOUNT, end);
uint32_t ms = (end - start) / (esp_clk_cpu_freq() / 1000);
printf("loop %4i pass, time= %ims\n", m, ms);
if (ms > 10000) {
break;
}
}
free(buff);
wl_unmount(handle);
}

86
components/wear_levelling/test/test_wl.c
View File

@ -6,7 +6,6 @@
#include "freertos/portable.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp32/clk.h"
#include "soc/cpu.h"
TEST_CASE("wl_unmount doesn't leak memory", "[wear_levelling]")
@ -23,7 +22,7 @@ TEST_CASE("wl_unmount doesn't leak memory", "[wear_levelling]")
// Original code:
//TEST_ASSERT_EQUAL_HEX32(size_before, size_after);
// Workaround for problem with heap size calculation:
ptrdiff_t stack_diff = size_before - size_after;
ptrdiff_t stack_diff = size_before - size_after;
stack_diff = abs(stack_diff);
if (stack_diff > 8) TEST_ASSERT_EQUAL(0, stack_diff);
}
@ -49,7 +48,7 @@ TEST_CASE("wl_mount check partition parameters", "[wear_levelling][ignore]")
// Original code:
//TEST_ASSERT_EQUAL_HEX32(size_before, size_after);
// Workaround for problem with heap size calculation:
ptrdiff_t stack_diff = size_before - size_after;
ptrdiff_t stack_diff = size_before - size_after;
stack_diff = abs(stack_diff);
if (stack_diff > 8) TEST_ASSERT_EQUAL(0, stack_diff);
}
@ -65,7 +64,7 @@ TEST_CASE("wl_mount check partition parameters", "[wear_levelling][ignore]")
// Original code:
//TEST_ASSERT_EQUAL_HEX32(size_before, size_after);
// Workaround for problem with heap size calculation:
ptrdiff_t stack_diff = size_before - size_after;
ptrdiff_t stack_diff = size_before - size_after;
stack_diff = abs(stack_diff);
if (stack_diff > 8) TEST_ASSERT_EQUAL(0, stack_diff);
}
@ -177,81 +176,6 @@ TEST_CASE("multiple tasks can access wl handle simultaneously", "[wear_levelling
wl_unmount(handle);
}
#define TEST_SECTORS_COUNT 8
static void check_mem_data(wl_handle_t handle, uint32_t init_val, uint32_t* buff)
{
size_t sector_size = wl_sector_size(handle);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
TEST_ESP_OK(wl_read(handle, sector_size * m, buff, sector_size));
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
uint32_t compare_val = init_val + i + m*sector_size;
TEST_ASSERT_EQUAL( buff[i], compare_val);
}
}
}
// We write complete memory with defined data
// And then write one sector many times.
// A data in other secors should be the same.
// We do this also with unmount
TEST_CASE("multiple write is correct", "[wear_levelling]")
{
const esp_partition_t *partition = get_test_data_partition();
esp_partition_t fake_partition;
memcpy(&fake_partition, partition, sizeof(fake_partition));
fake_partition.size = SPI_FLASH_SEC_SIZE*(4 + TEST_SECTORS_COUNT);
wl_handle_t handle;
TEST_ESP_OK(wl_mount(&fake_partition, &handle));
size_t sector_size = wl_sector_size(handle);
// Erase 8 sectors
TEST_ESP_OK(wl_erase_range(handle, 0, sector_size * TEST_SECTORS_COUNT));
// Write data to all sectors
printf("Check 1 sector_size=0x%08x\n", sector_size);
// Set initial random value
uint32_t init_val = rand();
uint32_t* buff = (uint32_t*)malloc(sector_size);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + m*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*m, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*m, buff, sector_size));
}
check_mem_data(handle, init_val, buff);
uint32_t start;
RSR(CCOUNT, start);
for (int m=0 ; m< 100000 ; m++) {
uint32_t sector = m % TEST_SECTORS_COUNT;
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + sector*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*sector, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*sector, buff, sector_size));
check_mem_data(handle, init_val, buff);
uint32_t end;
RSR(CCOUNT, end);
uint32_t ms = (end - start) / (esp_clk_cpu_freq() / 1000);
printf("loop %4i pass, time= %ims\n", m, ms);
if (ms > 10000) {
break;
}
}
free(buff);
wl_unmount(handle);
}
extern const uint8_t test_partition_v1_bin_start[] asm("_binary_test_partition_v1_bin_start");
extern const uint8_t test_partition_v1_bin_end[] asm("_binary_test_partition_v1_bin_end");
@ -259,7 +183,7 @@ extern const uint8_t test_partition_v1_bin_end[] asm("_binary_test_partition_v
#define COMPARE_START_CONST 0x12340000
// We write to partition prepared image with V1
// Then we convert image to new version and verifying the data
// Then we convert image to new version and verifying the data
TEST_CASE("Version update test", "[wear_levelling]")
{
@ -269,7 +193,7 @@ TEST_CASE("Version update test", "[wear_levelling]")
if (partition->encrypted)
{
printf("Update from V1 to V2 will not work.\n");
printf("Update from V1 to V2 will not work.\n");
return;
}
fake_partition.size = (size_t)(test_partition_v1_bin_end - test_partition_v1_bin_start);

2
examples/peripherals/spi_master/main/CMakeLists.txt
View File

@ -3,7 +3,7 @@ set(srcs "pretty_effect.c"
)
# Only ESP32 has enough memory to do jpeg decoding
if (CONFIG_IDF_TARGET_ESP32)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcs "decode_image.c")
endif()