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esp_common: move some headers
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c16ceafa5c
commit
5e8799bbfe
@ -19,6 +19,7 @@ set(COMPONENTS
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bootloader
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esptool_py
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esp_hw_support
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esp_system
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hal
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partition_table
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soc
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@ -75,8 +75,8 @@ endif()
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idf_component_register(SRCS "${srcs}"
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INCLUDE_DIRS ${includes}
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PRIV_INCLUDE_DIRS "include/driver"
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PRIV_REQUIRES efuse esp_pm esp_timer esp_ipc
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REQUIRES esp_ringbuf freertos soc hal esp_hw_support)
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PRIV_REQUIRES efuse esp_timer esp_ipc
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REQUIRES esp_pm esp_ringbuf freertos soc hal esp_hw_support)
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# (REQUIRES cannot hide soc headers, since many arguments in the driver headers are chip-dependent)
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# uses C11 atomic feature
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@ -30,7 +30,7 @@ else()
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# app_update is added here because cpu_start.c uses esp_ota_get_app_description() function.
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# esp_timer is added here because cpu_start.c uses esp_timer
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set(priv_requires app_trace app_update bootloader_support esp_system log mbedtls nvs_flash pthread
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spi_flash vfs espcoredump esp_common perfmon esp_timer esp_ipc)
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spi_flash vfs espcoredump esp_common perfmon esp_timer esp_ipc esp_pm)
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set(fragments linker.lf ld/esp32_fragments.lf)
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idf_component_register(SRCS "${srcs}"
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@ -14,6 +14,9 @@
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#ifndef __ESP_CROSSCORE_INT_H
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#define __ESP_CROSSCORE_INT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Initialize the crosscore interrupt system for this CPU.
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@ -61,4 +64,8 @@ void esp_crosscore_int_send_freq_switch(int core_id);
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*/
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void esp_crosscore_int_send_print_backtrace(int core_id);
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#ifdef __cplusplus
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}
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#endif
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#endif
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