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e55f9c1e98
I am stealing this delay coding from @jeremyherbert #2493 pr. 2. Change Bus Reset to handle interrupted READ sequences. The current code does not handle interrupted READ cycles. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA. The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period. If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit. 3. fix typo correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it. This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!