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93166f8756 |
@ -31,4 +31,5 @@ include:
|
|||||||
- '.gitlab/ci/host-test.yml'
|
- '.gitlab/ci/host-test.yml'
|
||||||
- '.gitlab/ci/deploy.yml'
|
- '.gitlab/ci/deploy.yml'
|
||||||
- '.gitlab/ci/post_deploy.yml'
|
- '.gitlab/ci/post_deploy.yml'
|
||||||
|
- '.gitlab/ci/retry_failed_jobs.yml'
|
||||||
- '.gitlab/ci/test-win.yml'
|
- '.gitlab/ci/test-win.yml'
|
||||||
|
@ -108,6 +108,7 @@
|
|||||||
/components/esp_psram/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
|
/components/esp_psram/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
|
||||||
/components/esp_ringbuf/ @esp-idf-codeowners/system
|
/components/esp_ringbuf/ @esp-idf-codeowners/system
|
||||||
/components/esp_rom/ @esp-idf-codeowners/system @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi
|
/components/esp_rom/ @esp-idf-codeowners/system @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi
|
||||||
|
/components/esp_security/ @esp-idf-codeowners/security
|
||||||
/components/esp_system/ @esp-idf-codeowners/system
|
/components/esp_system/ @esp-idf-codeowners/system
|
||||||
/components/esp_timer/ @esp-idf-codeowners/system
|
/components/esp_timer/ @esp-idf-codeowners/system
|
||||||
/components/esp-tls/ @esp-idf-codeowners/app-utilities
|
/components/esp-tls/ @esp-idf-codeowners/app-utilities
|
||||||
|
@ -323,6 +323,7 @@ build_child_pipeline:
|
|||||||
MR_MODIFIED_FILES: $MR_MODIFIED_FILES
|
MR_MODIFIED_FILES: $MR_MODIFIED_FILES
|
||||||
PARENT_PIPELINE_ID: $CI_PIPELINE_ID
|
PARENT_PIPELINE_ID: $CI_PIPELINE_ID
|
||||||
BUILD_AND_TEST_ALL_APPS: $BUILD_AND_TEST_ALL_APPS
|
BUILD_AND_TEST_ALL_APPS: $BUILD_AND_TEST_ALL_APPS
|
||||||
|
REPORT_EXIT_CODE: $REPORT_EXIT_CODE
|
||||||
# https://gitlab.com/gitlab-org/gitlab/-/issues/214340
|
# https://gitlab.com/gitlab-org/gitlab/-/issues/214340
|
||||||
inherit:
|
inherit:
|
||||||
variables: false
|
variables: false
|
||||||
|
@ -12,6 +12,7 @@ stages:
|
|||||||
- test_deploy
|
- test_deploy
|
||||||
- deploy
|
- deploy
|
||||||
- post_deploy
|
- post_deploy
|
||||||
|
- retry_failed_jobs
|
||||||
|
|
||||||
variables:
|
variables:
|
||||||
# System environment
|
# System environment
|
||||||
@ -102,6 +103,8 @@ variables:
|
|||||||
CCACHE_DIR: "/cache/idf_ccache"
|
CCACHE_DIR: "/cache/idf_ccache"
|
||||||
CCACHE_MAXSIZE: "50G"
|
CCACHE_MAXSIZE: "50G"
|
||||||
|
|
||||||
|
FF_USE_NEW_BASH_EVAL_STRATEGY: "true"
|
||||||
|
|
||||||
################################################
|
################################################
|
||||||
# `before_script` and `after_script` Templates #
|
# `before_script` and `after_script` Templates #
|
||||||
################################################
|
################################################
|
||||||
@ -285,8 +288,8 @@ variables:
|
|||||||
git remote add origin "${CI_REPOSITORY_URL}"
|
git remote add origin "${CI_REPOSITORY_URL}"
|
||||||
fi
|
fi
|
||||||
|
|
||||||
.git_checkout_fetch_head: &git_checkout_fetch_head |
|
.git_checkout_ci_commit_sha: &git_checkout_ci_commit_sha |
|
||||||
git checkout FETCH_HEAD
|
git checkout $CI_COMMIT_SHA
|
||||||
git clean ${GIT_CLEAN_FLAGS}
|
git clean ${GIT_CLEAN_FLAGS}
|
||||||
|
|
||||||
# git diff requires two commits, with different CI env var
|
# git diff requires two commits, with different CI env var
|
||||||
@ -310,6 +313,7 @@ variables:
|
|||||||
git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||||
git fetch origin $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
git fetch origin $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||||
export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_MERGE_REQUEST_DIFF_BASE_SHA $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA)
|
export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_MERGE_REQUEST_DIFF_BASE_SHA $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA)
|
||||||
|
git fetch origin $CI_COMMIT_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||||
# merge request pipelines, when the mr got conflicts
|
# merge request pipelines, when the mr got conflicts
|
||||||
elif [[ -n $CI_MERGE_REQUEST_DIFF_BASE_SHA ]]; then
|
elif [[ -n $CI_MERGE_REQUEST_DIFF_BASE_SHA ]]; then
|
||||||
git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||||
@ -325,7 +329,7 @@ variables:
|
|||||||
git fetch origin $CI_COMMIT_SHA --depth=2 ${GIT_FETCH_EXTRA_FLAGS}
|
git fetch origin $CI_COMMIT_SHA --depth=2 ${GIT_FETCH_EXTRA_FLAGS}
|
||||||
export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_COMMIT_SHA~1 $CI_COMMIT_SHA)
|
export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_COMMIT_SHA~1 $CI_COMMIT_SHA)
|
||||||
fi
|
fi
|
||||||
- *git_checkout_fetch_head
|
- *git_checkout_ci_commit_sha
|
||||||
- *common-before_scripts
|
- *common-before_scripts
|
||||||
- *setup_tools_and_idf_python_venv
|
- *setup_tools_and_idf_python_venv
|
||||||
- add_gitlab_ssh_keys
|
- add_gitlab_ssh_keys
|
||||||
@ -339,7 +343,7 @@ variables:
|
|||||||
- *git_init
|
- *git_init
|
||||||
- *git_fetch_from_mirror_url_if_exists
|
- *git_fetch_from_mirror_url_if_exists
|
||||||
- git fetch origin "${CI_COMMIT_SHA}" --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
- git fetch origin "${CI_COMMIT_SHA}" --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||||
- *git_checkout_fetch_head
|
- *git_checkout_ci_commit_sha
|
||||||
- *common-before_scripts
|
- *common-before_scripts
|
||||||
- *setup_tools_and_idf_python_venv
|
- *setup_tools_and_idf_python_venv
|
||||||
- add_gitlab_ssh_keys
|
- add_gitlab_ssh_keys
|
||||||
|
@ -1,4 +1,4 @@
|
|||||||
# Extenal DangerJS
|
# External DangerJS
|
||||||
include:
|
include:
|
||||||
- project: espressif/shared-ci-dangerjs
|
- project: espressif/shared-ci-dangerjs
|
||||||
ref: master
|
ref: master
|
||||||
@ -10,7 +10,6 @@ run-danger-mr-linter:
|
|||||||
GIT_STRATEGY: none # no repo checkout
|
GIT_STRATEGY: none # no repo checkout
|
||||||
ENABLE_CHECK_AREA_LABELS: 'true'
|
ENABLE_CHECK_AREA_LABELS: 'true'
|
||||||
ENABLE_CHECK_DOCS_TRANSLATION: 'true'
|
ENABLE_CHECK_DOCS_TRANSLATION: 'true'
|
||||||
ENABLE_CHECK_RELEASE_NOTES_DESCRIPTION: 'true'
|
|
||||||
ENABLE_CHECK_UPDATED_CHANGELOG: 'false'
|
ENABLE_CHECK_UPDATED_CHANGELOG: 'false'
|
||||||
before_script: []
|
before_script: []
|
||||||
cache: []
|
cache: []
|
||||||
|
@ -11,7 +11,7 @@ extra_default_build_targets:
|
|||||||
- esp32c61
|
- esp32c61
|
||||||
|
|
||||||
bypass_check_test_targets:
|
bypass_check_test_targets:
|
||||||
- esp32c61
|
|
||||||
#
|
#
|
||||||
# These lines would
|
# These lines would
|
||||||
# - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
|
# - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
|
||||||
|
@ -68,22 +68,6 @@ test_ldgen_on_host:
|
|||||||
variables:
|
variables:
|
||||||
LC_ALL: C.UTF-8
|
LC_ALL: C.UTF-8
|
||||||
|
|
||||||
test_reproducible_build:
|
|
||||||
extends: .host_test_template
|
|
||||||
script:
|
|
||||||
- ./tools/ci/test_reproducible_build.sh
|
|
||||||
artifacts:
|
|
||||||
when: on_failure
|
|
||||||
paths:
|
|
||||||
- "**/sdkconfig"
|
|
||||||
- "**/build*/*.bin"
|
|
||||||
- "**/build*/*.elf"
|
|
||||||
- "**/build*/*.map"
|
|
||||||
- "**/build*/flasher_args.json"
|
|
||||||
- "**/build*/*.bin"
|
|
||||||
- "**/build*/bootloader/*.bin"
|
|
||||||
- "**/build*/partition_table/*.bin"
|
|
||||||
|
|
||||||
test_spiffs_on_host:
|
test_spiffs_on_host:
|
||||||
extends: .host_test_template
|
extends: .host_test_template
|
||||||
script:
|
script:
|
||||||
@ -385,7 +369,6 @@ test_pytest_macos:
|
|||||||
--ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
|
--ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
|
||||||
--app-info-filepattern \"list_job_*.txt\"
|
--app-info-filepattern \"list_job_*.txt\"
|
||||||
|
|
||||||
|
|
||||||
test_idf_pytest_plugin:
|
test_idf_pytest_plugin:
|
||||||
extends:
|
extends:
|
||||||
- .host_test_template
|
- .host_test_template
|
||||||
@ -400,3 +383,22 @@ test_idf_pytest_plugin:
|
|||||||
- python -m unittest test_report_generator.py
|
- python -m unittest test_report_generator.py
|
||||||
- cd ${IDF_PATH}/tools/ci/idf_pytest
|
- cd ${IDF_PATH}/tools/ci/idf_pytest
|
||||||
- pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
|
- pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
|
||||||
|
|
||||||
|
test_idf_build_apps_load_soc_caps:
|
||||||
|
extends: .host_test_template
|
||||||
|
script:
|
||||||
|
- python tools/ci/check_soc_headers_load_in_idf_build_apps.py
|
||||||
|
|
||||||
|
test_nvs_gen_check:
|
||||||
|
extends: .host_test_template
|
||||||
|
artifacts:
|
||||||
|
paths:
|
||||||
|
- XUNIT_RESULT.xml
|
||||||
|
- components/nvs_flash/nvs_partition_tool
|
||||||
|
reports:
|
||||||
|
junit: XUNIT_RESULT.xml
|
||||||
|
variables:
|
||||||
|
LC_ALL: C.UTF-8
|
||||||
|
script:
|
||||||
|
- cd ${IDF_PATH}/components/nvs_flash/nvs_partition_tool
|
||||||
|
- pytest --noconftest test_nvs_gen_check.py --junitxml=XUNIT_RESULT.xml
|
||||||
|
@ -135,6 +135,7 @@ pipeline_variables:
|
|||||||
# MODIFIED_FILES is a list of files that changed, could be used everywhere
|
# MODIFIED_FILES is a list of files that changed, could be used everywhere
|
||||||
- MODIFIED_FILES=$(echo "$GIT_DIFF_OUTPUT" | xargs)
|
- MODIFIED_FILES=$(echo "$GIT_DIFF_OUTPUT" | xargs)
|
||||||
- echo "MODIFIED_FILES=$MODIFIED_FILES" >> pipeline.env
|
- echo "MODIFIED_FILES=$MODIFIED_FILES" >> pipeline.env
|
||||||
|
- echo "REPORT_EXIT_CODE=0" >> pipeline.env
|
||||||
# MR_MODIFIED_FILES and MR_MODIFIED_COMPONENTS are semicolon separated lists that is used in MR only
|
# MR_MODIFIED_FILES and MR_MODIFIED_COMPONENTS are semicolon separated lists that is used in MR only
|
||||||
# for non MR pipeline, these are empty lists
|
# for non MR pipeline, these are empty lists
|
||||||
- |
|
- |
|
||||||
@ -157,6 +158,7 @@ pipeline_variables:
|
|||||||
if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
|
if [ -n "$CI_PYTHON_CONSTRAINT_BRANCH" ]; then
|
||||||
echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
|
echo "BUILD_AND_TEST_ALL_APPS=1" >> pipeline.env
|
||||||
fi
|
fi
|
||||||
|
- python tools/ci/ci_process_description.py
|
||||||
- cat pipeline.env
|
- cat pipeline.env
|
||||||
- python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report
|
- python tools/ci/artifacts_handler.py upload --type modified_files_and_components_report
|
||||||
artifacts:
|
artifacts:
|
||||||
@ -166,3 +168,15 @@ pipeline_variables:
|
|||||||
- pipeline.env
|
- pipeline.env
|
||||||
expire_in: 1 week
|
expire_in: 1 week
|
||||||
when: always
|
when: always
|
||||||
|
|
||||||
|
redundant_pass_job:
|
||||||
|
stage: pre_check
|
||||||
|
tags: [shiny, fast_run]
|
||||||
|
image: $ESP_ENV_IMAGE
|
||||||
|
dependencies: null
|
||||||
|
before_script: []
|
||||||
|
cache: []
|
||||||
|
extends: []
|
||||||
|
script:
|
||||||
|
- echo "This job is redundant to ensure the 'retry_failed_jobs' job can exist and not be skipped"
|
||||||
|
when: always
|
||||||
|
15
.gitlab/ci/retry_failed_jobs.yml
Normal file
15
.gitlab/ci/retry_failed_jobs.yml
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
retry_failed_jobs:
|
||||||
|
stage: retry_failed_jobs
|
||||||
|
tags: [shiny, fast_run]
|
||||||
|
allow_failure: true
|
||||||
|
image: $ESP_ENV_IMAGE
|
||||||
|
dependencies: null
|
||||||
|
before_script: []
|
||||||
|
cache: []
|
||||||
|
extends: []
|
||||||
|
script:
|
||||||
|
- echo "Retrieving and retrying all failed jobs for the pipeline..."
|
||||||
|
- python tools/ci/python_packages/gitlab_api.py retry_failed_jobs $CI_MERGE_REQUEST_PROJECT_ID --pipeline_id $CI_PIPELINE_ID
|
||||||
|
when: manual
|
||||||
|
needs:
|
||||||
|
- redundant_pass_job
|
@ -108,8 +108,6 @@
|
|||||||
- "tools/detect_python.sh"
|
- "tools/detect_python.sh"
|
||||||
- "tools/detect_python.fish"
|
- "tools/detect_python.fish"
|
||||||
|
|
||||||
- "tools/ci/test_reproducible_build.sh"
|
|
||||||
|
|
||||||
- "tools/gen_soc_caps_kconfig/*"
|
- "tools/gen_soc_caps_kconfig/*"
|
||||||
- "tools/gen_soc_caps_kconfig/test/test_gen_soc_caps_kconfig.py"
|
- "tools/gen_soc_caps_kconfig/test/test_gen_soc_caps_kconfig.py"
|
||||||
|
|
||||||
|
@ -13,3 +13,17 @@
|
|||||||
<!-- Either state release notes or write "No release notes" -->
|
<!-- Either state release notes or write "No release notes" -->
|
||||||
|
|
||||||
<!-- ## Breaking change notes --><!-- Optional -->
|
<!-- ## Breaking change notes --><!-- Optional -->
|
||||||
|
|
||||||
|
<!-- ## Dynamic Pipeline Configuration
|
||||||
|
```yaml
|
||||||
|
Test Case Filters:
|
||||||
|
# Only run tests that match the given substring expression (modified files/components will be ignored):
|
||||||
|
# Please use a list of strings.
|
||||||
|
# This will run the test cases filtered like `pytest -k "(<list_item_1>) or (<list_item_2>) or ...`
|
||||||
|
# The fast pipeline will fail at the final stage.
|
||||||
|
# For example:
|
||||||
|
- test_sdm and not sdmmc
|
||||||
|
- test_hello_world
|
||||||
|
# This example will include all tests containing 'test_hello_world' in the name,
|
||||||
|
# and include all tests containing 'test_sdm' but not 'sdmmc' in the name.
|
||||||
|
``` --><!-- Optional -->
|
||||||
|
1
.gitmodules
vendored
1
.gitmodules
vendored
@ -55,6 +55,7 @@
|
|||||||
sbom-url = https://github.com/DaveGamble/cJSON
|
sbom-url = https://github.com/DaveGamble/cJSON
|
||||||
sbom-description = Ultralightweight JSON parser in ANSI C
|
sbom-description = Ultralightweight JSON parser in ANSI C
|
||||||
sbom-hash = acc76239bee01d8e9c858ae2cab296704e52d916
|
sbom-hash = acc76239bee01d8e9c858ae2cab296704e52d916
|
||||||
|
sbom-cve-exclude-list = CVE-2024-31755 Resolved in v1.7.18
|
||||||
|
|
||||||
[submodule "components/mbedtls/mbedtls"]
|
[submodule "components/mbedtls/mbedtls"]
|
||||||
path = components/mbedtls/mbedtls
|
path = components/mbedtls/mbedtls
|
||||||
|
@ -241,6 +241,6 @@ repos:
|
|||||||
name: Lint rST files in docs folder using Sphinx Lint
|
name: Lint rST files in docs folder using Sphinx Lint
|
||||||
files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$
|
files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$
|
||||||
- repo: https://github.com/espressif/esp-idf-kconfig.git
|
- repo: https://github.com/espressif/esp-idf-kconfig.git
|
||||||
rev: v2.1.0
|
rev: v2.3.0
|
||||||
hooks:
|
hooks:
|
||||||
- id: check-kconfig-files
|
- id: check-kconfig-files
|
||||||
|
@ -16,7 +16,11 @@ endif()
|
|||||||
if(NOT BOOTLOADER_BUILD)
|
if(NOT BOOTLOADER_BUILD)
|
||||||
|
|
||||||
if(CONFIG_COMPILER_OPTIMIZATION_SIZE)
|
if(CONFIG_COMPILER_OPTIMIZATION_SIZE)
|
||||||
list(APPEND compile_options "-Os")
|
if(CMAKE_C_COMPILER_ID MATCHES "Clang")
|
||||||
|
list(APPEND compile_options "-Oz")
|
||||||
|
else()
|
||||||
|
list(APPEND compile_options "-Os")
|
||||||
|
endif()
|
||||||
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
||||||
list(APPEND compile_options "-freorder-blocks")
|
list(APPEND compile_options "-freorder-blocks")
|
||||||
endif()
|
endif()
|
||||||
@ -34,7 +38,11 @@ if(NOT BOOTLOADER_BUILD)
|
|||||||
else() # BOOTLOADER_BUILD
|
else() # BOOTLOADER_BUILD
|
||||||
|
|
||||||
if(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE)
|
if(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE)
|
||||||
list(APPEND compile_options "-Os")
|
if(CMAKE_C_COMPILER_ID MATCHES "Clang")
|
||||||
|
list(APPEND compile_options "-Oz")
|
||||||
|
else()
|
||||||
|
list(APPEND compile_options "-Os")
|
||||||
|
endif()
|
||||||
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
||||||
list(APPEND compile_options "-freorder-blocks")
|
list(APPEND compile_options "-freorder-blocks")
|
||||||
endif()
|
endif()
|
||||||
@ -152,46 +160,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
|
|||||||
list(APPEND compile_options "-fdump-rtl-expand")
|
list(APPEND compile_options "-fdump-rtl-expand")
|
||||||
endif()
|
endif()
|
||||||
|
|
||||||
if(NOT ${CMAKE_C_COMPILER_VERSION} VERSION_LESS 8.0.0)
|
__generate_prefix_map(prefix_map_compile_options)
|
||||||
if(CONFIG_COMPILER_HIDE_PATHS_MACROS)
|
list(APPEND compile_options ${prefix_map_compile_options})
|
||||||
list(APPEND compile_options "-fmacro-prefix-map=${CMAKE_SOURCE_DIR}=.")
|
|
||||||
list(APPEND compile_options "-fmacro-prefix-map=${IDF_PATH}=/IDF")
|
|
||||||
endif()
|
|
||||||
|
|
||||||
if(CONFIG_APP_REPRODUCIBLE_BUILD)
|
|
||||||
idf_build_set_property(DEBUG_PREFIX_MAP_GDBINIT "${BUILD_DIR}/prefix_map_gdbinit")
|
|
||||||
|
|
||||||
list(APPEND compile_options "-fdebug-prefix-map=${IDF_PATH}=/IDF")
|
|
||||||
list(APPEND compile_options "-fdebug-prefix-map=${PROJECT_DIR}=/IDF_PROJECT")
|
|
||||||
list(APPEND compile_options "-fdebug-prefix-map=${BUILD_DIR}=/IDF_BUILD")
|
|
||||||
|
|
||||||
# component dirs
|
|
||||||
idf_build_get_property(python PYTHON)
|
|
||||||
idf_build_get_property(idf_path IDF_PATH)
|
|
||||||
idf_build_get_property(component_dirs BUILD_COMPONENT_DIRS)
|
|
||||||
|
|
||||||
execute_process(
|
|
||||||
COMMAND ${python}
|
|
||||||
"${idf_path}/tools/generate_debug_prefix_map.py"
|
|
||||||
"${BUILD_DIR}"
|
|
||||||
"${component_dirs}"
|
|
||||||
OUTPUT_VARIABLE result
|
|
||||||
RESULT_VARIABLE ret
|
|
||||||
)
|
|
||||||
if(NOT ret EQUAL 0)
|
|
||||||
message(FATAL_ERROR "This is a bug. Please report to https://github.com/espressif/esp-idf/issues")
|
|
||||||
endif()
|
|
||||||
|
|
||||||
spaces2list(result)
|
|
||||||
list(LENGTH component_dirs length)
|
|
||||||
math(EXPR max_index "${length} - 1")
|
|
||||||
foreach(index RANGE ${max_index})
|
|
||||||
list(GET component_dirs ${index} folder)
|
|
||||||
list(GET result ${index} after)
|
|
||||||
list(APPEND compile_options "-fdebug-prefix-map=${folder}=${after}")
|
|
||||||
endforeach()
|
|
||||||
endif()
|
|
||||||
endif()
|
|
||||||
|
|
||||||
if(CONFIG_COMPILER_DISABLE_GCC12_WARNINGS)
|
if(CONFIG_COMPILER_DISABLE_GCC12_WARNINGS)
|
||||||
list(APPEND compile_options "-Wno-address"
|
list(APPEND compile_options "-Wno-address"
|
||||||
@ -227,8 +197,35 @@ endif()
|
|||||||
list(APPEND link_options "-fno-lto")
|
list(APPEND link_options "-fno-lto")
|
||||||
|
|
||||||
if(CONFIG_IDF_TARGET_LINUX AND CMAKE_HOST_SYSTEM_NAME STREQUAL "Darwin")
|
if(CONFIG_IDF_TARGET_LINUX AND CMAKE_HOST_SYSTEM_NAME STREQUAL "Darwin")
|
||||||
|
# Not all versions of the MacOS linker support the -warn_commons flag.
|
||||||
|
# ld version 1053.12 (and above) have been tested to support it.
|
||||||
|
# Hence, we extract the version string from the linker output
|
||||||
|
# before including the flag.
|
||||||
|
|
||||||
|
# Get the ld version, capturing both stdout and stderr
|
||||||
|
execute_process(
|
||||||
|
COMMAND ${CMAKE_LINKER} -v
|
||||||
|
OUTPUT_VARIABLE LD_VERSION_OUTPUT
|
||||||
|
ERROR_VARIABLE LD_VERSION_ERROR
|
||||||
|
OUTPUT_STRIP_TRAILING_WHITESPACE
|
||||||
|
ERROR_STRIP_TRAILING_WHITESPACE
|
||||||
|
)
|
||||||
|
|
||||||
|
# Combine stdout and stderr
|
||||||
|
set(LD_VERSION_OUTPUT "${LD_VERSION_OUTPUT}\n${LD_VERSION_ERROR}")
|
||||||
|
|
||||||
|
# Extract the version string
|
||||||
|
string(REGEX MATCH "PROJECT:(ld|dyld)-([0-9]+)\\.([0-9]+)" LD_VERSION_MATCH "${LD_VERSION_OUTPUT}")
|
||||||
|
set(LD_VERSION_MAJOR_MINOR "${CMAKE_MATCH_2}.${CMAKE_MATCH_3}")
|
||||||
|
|
||||||
|
message(STATUS "Linker Version: ${LD_VERSION_MAJOR_MINOR}")
|
||||||
|
|
||||||
|
# Compare the version with 1053.12
|
||||||
|
if(LD_VERSION_MAJOR_MINOR VERSION_GREATER_EQUAL "1053.12")
|
||||||
|
list(APPEND link_options "-Wl,-warn_commons")
|
||||||
|
endif()
|
||||||
|
|
||||||
list(APPEND link_options "-Wl,-dead_strip")
|
list(APPEND link_options "-Wl,-dead_strip")
|
||||||
list(APPEND link_options "-Wl,-warn_commons")
|
|
||||||
else()
|
else()
|
||||||
list(APPEND link_options "-Wl,--gc-sections")
|
list(APPEND link_options "-Wl,--gc-sections")
|
||||||
list(APPEND link_options "-Wl,--warn-common")
|
list(APPEND link_options "-Wl,--warn-common")
|
||||||
|
22
Kconfig
22
Kconfig
@ -135,7 +135,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
|||||||
default "y" if IDF_TARGET="esp32c61"
|
default "y" if IDF_TARGET="esp32c61"
|
||||||
select FREERTOS_UNICORE
|
select FREERTOS_UNICORE
|
||||||
select IDF_TARGET_ARCH_RISCV
|
select IDF_TARGET_ARCH_RISCV
|
||||||
select IDF_ENV_FPGA
|
|
||||||
|
|
||||||
config IDF_TARGET_LINUX
|
config IDF_TARGET_LINUX
|
||||||
bool
|
bool
|
||||||
@ -324,8 +323,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
|||||||
help
|
help
|
||||||
This option sets compiler optimization level (gcc -O argument) for the app.
|
This option sets compiler optimization level (gcc -O argument) for the app.
|
||||||
|
|
||||||
- The "Debug" setting will add the -0g flag to CFLAGS.
|
- The "Debug" setting will add the -Og flag to CFLAGS.
|
||||||
- The "Size" setting will add the -0s flag to CFLAGS.
|
- The "Size" setting will add the -Os flag to CFLAGS (-Oz with Clang).
|
||||||
- The "Performance" setting will add the -O2 flag to CFLAGS.
|
- The "Performance" setting will add the -O2 flag to CFLAGS.
|
||||||
- The "None" setting will add the -O0 flag to CFLAGS.
|
- The "None" setting will add the -O0 flag to CFLAGS.
|
||||||
|
|
||||||
@ -346,7 +345,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
|||||||
config COMPILER_OPTIMIZATION_DEBUG
|
config COMPILER_OPTIMIZATION_DEBUG
|
||||||
bool "Debug (-Og)"
|
bool "Debug (-Og)"
|
||||||
config COMPILER_OPTIMIZATION_SIZE
|
config COMPILER_OPTIMIZATION_SIZE
|
||||||
bool "Optimize for size (-Os)"
|
bool "Optimize for size (-Os with GCC, -Oz with Clang)"
|
||||||
config COMPILER_OPTIMIZATION_PERF
|
config COMPILER_OPTIMIZATION_PERF
|
||||||
bool "Optimize for performance (-O2)"
|
bool "Optimize for performance (-O2)"
|
||||||
config COMPILER_OPTIMIZATION_NONE
|
config COMPILER_OPTIMIZATION_NONE
|
||||||
@ -389,6 +388,21 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
|||||||
|
|
||||||
endchoice # assertions
|
endchoice # assertions
|
||||||
|
|
||||||
|
config COMPILER_ASSERT_NDEBUG_EVALUATE
|
||||||
|
bool "Enable the evaluation of the expression inside assert(X) when NDEBUG is set"
|
||||||
|
default y
|
||||||
|
help
|
||||||
|
When NDEBUG is set, assert(X) will not cause code to trigger an assertion.
|
||||||
|
With this option set, assert(X) will still evaluate the expression X, though
|
||||||
|
the result will never cause an assertion. This means that if X is a function
|
||||||
|
then the function will be called.
|
||||||
|
|
||||||
|
This is not according to the standard, which states that the assert(X) should
|
||||||
|
be replaced with ((void)0) if NDEBUG is defined.
|
||||||
|
|
||||||
|
In ESP-IDF v6.0 the default behavior will change to "no" to be in line with the
|
||||||
|
standard.
|
||||||
|
|
||||||
choice COMPILER_FLOAT_LIB_FROM
|
choice COMPILER_FLOAT_LIB_FROM
|
||||||
prompt "Compiler float lib source"
|
prompt "Compiler float lib source"
|
||||||
default COMPILER_FLOAT_LIB_FROM_RVFPLIB if ESP_ROM_HAS_RVFPLIB
|
default COMPILER_FLOAT_LIB_FROM_RVFPLIB if ESP_ROM_HAS_RVFPLIB
|
||||||
|
22
README.md
22
README.md
@ -15,17 +15,17 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li
|
|||||||
|
|
||||||
The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.
|
The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.
|
||||||
|
|
||||||
|Chip | v4.4 | v5.0 | v5.1 | v5.2 | v5.3 | |
|
|Chip | v5.0 | v5.1 | v5.2 | v5.3 | |
|
||||||
|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
|
|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
|
||||||
|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
||||||
|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
||||||
|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
||||||
|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
|
|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
|
||||||
|ESP32-C2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
|
|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
|
||||||
|ESP32-C6 | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
|
|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
|
||||||
|ESP32-H2 | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
|
|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
|
||||||
|ESP32-P4 | | | | | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
|
|ESP32-P4 | | | | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
|
||||||
|ESP32-C5 | | | | | ![alt text][preview] | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |
|
|ESP32-C5 | | | | ![alt text][preview] | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |
|
||||||
|
|
||||||
[supported]: https://img.shields.io/badge/-supported-green "supported"
|
[supported]: https://img.shields.io/badge/-supported-green "supported"
|
||||||
[preview]: https://img.shields.io/badge/-preview-orange "preview"
|
[preview]: https://img.shields.io/badge/-preview-orange "preview"
|
||||||
|
22
README_CN.md
22
README_CN.md
@ -15,17 +15,17 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架,支持 Windows、Linux
|
|||||||
|
|
||||||
下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态,其中 ![alt text][supported] 代表已支持,![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制,而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。
|
下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态,其中 ![alt text][supported] 代表已支持,![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制,而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。
|
||||||
|
|
||||||
|芯片 | v4.4 | v5.0 | v5.1 | v5.2 | v5.3 | |
|
|芯片 | v5.0 | v5.1 | v5.2 | v5.3 | |
|
||||||
|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
|
|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
|
||||||
|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
|ESP32 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
||||||
|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
|ESP32-S2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
||||||
|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
|ESP32-C3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | |
|
||||||
|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
|
|ESP32-S3 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
|
||||||
|ESP32-C2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
|
|ESP32-C2 | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
|
||||||
|ESP32-C6 | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
|
|ESP32-C6 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
|
||||||
|ESP32-H2 | | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
|
|ESP32-H2 | | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
|
||||||
|ESP32-P4 | | | | | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/en/news/ESP32-P4) |
|
|ESP32-P4 | | | | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) |
|
||||||
|ESP32-C5 | | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
|
|ESP32-C5 | | | | ![alt text][preview] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
|
||||||
|
|
||||||
[supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
|
[supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
|
||||||
[preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
|
[preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
|
||||||
|
@ -2,6 +2,6 @@
|
|||||||
|
|
||||||
components/app_update/test_apps:
|
components/app_update/test_apps:
|
||||||
disable:
|
disable:
|
||||||
- if: IDF_TARGET in ["esp32c5", "esp32c61"]
|
- if: IDF_TARGET in ["esp32c61"]
|
||||||
temporary: true
|
temporary: true
|
||||||
reason: target esp32c5 is not supported yet # TODO: [ESP32C5] IDF-8640, IDF-10317, [ESP32C61] IDF-9245
|
reason: target esp32c61 is not supported yet # TODO: [ESP32C61] IDF-9245
|
||||||
|
@ -1,2 +1,2 @@
|
|||||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||||
|
@ -1,4 +1,4 @@
|
|||||||
# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
# SPDX-License-Identifier: Unlicense OR CC0-1.0
|
# SPDX-License-Identifier: Unlicense OR CC0-1.0
|
||||||
import re
|
import re
|
||||||
|
|
||||||
@ -19,14 +19,8 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
|
|||||||
|
|
||||||
|
|
||||||
@pytest.mark.supported_targets
|
@pytest.mark.supported_targets
|
||||||
@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep') # TODO: [ESP32C5] IDF-8640, IDF-10317
|
# TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-10983
|
||||||
|
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
|
||||||
@pytest.mark.generic
|
@pytest.mark.generic
|
||||||
def test_app_update(dut: Dut) -> None:
|
def test_app_update(dut: Dut) -> None:
|
||||||
extra_data = dut.parse_test_menu()
|
dut.run_all_single_board_cases(timeout=90)
|
||||||
for test_case in extra_data:
|
|
||||||
if test_case.type != 'multi_stage':
|
|
||||||
dut.write(str(test_case.index))
|
|
||||||
else:
|
|
||||||
run_multiple_stages(dut, test_case.index, len(test_case.subcases))
|
|
||||||
dut.expect_unity_test_output(timeout=90)
|
|
||||||
dut.expect_exact("Enter next test, or 'enter' to see menu")
|
|
||||||
|
@ -20,14 +20,14 @@ menu "Bootloader config"
|
|||||||
This option sets compiler optimization level (gcc -O argument)
|
This option sets compiler optimization level (gcc -O argument)
|
||||||
for the bootloader.
|
for the bootloader.
|
||||||
|
|
||||||
- The default "Size" setting will add the -0s flag to CFLAGS.
|
- The default "Size" setting will add the -Os (-Oz with clang) flag to CFLAGS.
|
||||||
- The "Debug" setting will add the -Og flag to CFLAGS.
|
- The "Debug" setting will add the -Og flag to CFLAGS.
|
||||||
- The "Performance" setting will add the -O2 flag to CFLAGS.
|
- The "Performance" setting will add the -O2 flag to CFLAGS.
|
||||||
|
|
||||||
Note that custom optimization levels may be unsupported.
|
Note that custom optimization levels may be unsupported.
|
||||||
|
|
||||||
config BOOTLOADER_COMPILER_OPTIMIZATION_SIZE
|
config BOOTLOADER_COMPILER_OPTIMIZATION_SIZE
|
||||||
bool "Size (-Os)"
|
bool "Size (-Os with GCC, -Oz with Clang)"
|
||||||
config BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG
|
config BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG
|
||||||
bool "Debug (-Og)"
|
bool "Debug (-Og)"
|
||||||
config BOOTLOADER_COMPILER_OPTIMIZATION_PERF
|
config BOOTLOADER_COMPILER_OPTIMIZATION_PERF
|
||||||
@ -776,6 +776,33 @@ menu "Security features"
|
|||||||
This can lead to permanent bricking of the device, in case all keys are revoked
|
This can lead to permanent bricking of the device, in case all keys are revoked
|
||||||
because of signature verification failure.
|
because of signature verification failure.
|
||||||
|
|
||||||
|
config SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||||
|
bool "Do not disable the ability to further read protect eFuses"
|
||||||
|
depends on SECURE_BOOT_V2_ENABLED
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS
|
||||||
|
efuse when Secure Boot is enabled. This prevents any more efuses from being read protected.
|
||||||
|
|
||||||
|
If this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure
|
||||||
|
Boot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and
|
||||||
|
BLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the secure boot public key digest,
|
||||||
|
causing an immediate denial of service and possibly allowing an additional fault injection attack to
|
||||||
|
bypass the signature protection.
|
||||||
|
|
||||||
|
The option must be set when you need to program any read-protected key type into the efuses,
|
||||||
|
e.g., HMAC, ECDSA etc. after secure boot has already been enabled on the device.
|
||||||
|
Please refer to secure boot V2 documentation guide for more details.
|
||||||
|
|
||||||
|
NOTE: Once a BLOCK is read-protected, the application will read all zeros from that block
|
||||||
|
|
||||||
|
NOTE: If "UART ROM download mode (Permanently disabled (recommended))" or
|
||||||
|
"UART ROM download mode (Permanently switch to Secure mode (recommended))" is set,
|
||||||
|
then it is __NOT__ possible to read/write efuses using espefuse.py utility.
|
||||||
|
However, efuse can be read/written from the application
|
||||||
|
|
||||||
|
Please refer to the Secure Boot V2 documentation guide for more information.
|
||||||
|
|
||||||
config SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT
|
config SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT
|
||||||
bool "Flash bootloader along with other artifacts when using the default flash command"
|
bool "Flash bootloader along with other artifacts when using the default flash command"
|
||||||
depends on SECURE_BOOT_V2_ENABLED && SECURE_BOOT_BUILD_SIGNED_BINARIES
|
depends on SECURE_BOOT_V2_ENABLED && SECURE_BOOT_BUILD_SIGNED_BINARIES
|
||||||
@ -956,26 +983,6 @@ menu "Security features"
|
|||||||
image to this length. It is generally not recommended to set this option, unless you have a legacy
|
image to this length. It is generally not recommended to set this option, unless you have a legacy
|
||||||
partitioning scheme which doesn't support 64KB aligned partition lengths.
|
partitioning scheme which doesn't support 64KB aligned partition lengths.
|
||||||
|
|
||||||
config SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
|
||||||
bool "Allow additional read protecting of efuses"
|
|
||||||
depends on SECURE_BOOT_INSECURE && SECURE_BOOT_V2_ENABLED
|
|
||||||
help
|
|
||||||
If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS
|
|
||||||
efuse when Secure Boot is enabled. This prevents any more efuses from being read protected.
|
|
||||||
|
|
||||||
If this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure
|
|
||||||
Boot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and
|
|
||||||
BLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the public key digest, causing an
|
|
||||||
immediate denial of service and possibly allowing an additional fault injection attack to
|
|
||||||
bypass the signature protection.
|
|
||||||
|
|
||||||
NOTE: Once a BLOCK is read-protected, the application will read all zeros from that block
|
|
||||||
|
|
||||||
NOTE: If "UART ROM download mode (Permanently disabled (recommended))" or
|
|
||||||
"UART ROM download mode (Permanently switch to Secure mode (recommended))" is set,
|
|
||||||
then it is __NOT__ possible to read/write efuses using espefuse.py utility.
|
|
||||||
However, efuse can be read/written from the application
|
|
||||||
|
|
||||||
config SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS
|
config SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS
|
||||||
bool "Leave unused digest slots available (not revoke)"
|
bool "Leave unused digest slots available (not revoke)"
|
||||||
depends on SECURE_BOOT_INSECURE && SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
|
depends on SECURE_BOOT_INSECURE && SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
|
||||||
|
@ -59,7 +59,7 @@ if(CONFIG_SECURE_SIGNED_APPS)
|
|||||||
# If the signing key is not found, create a phony gen_secure_boot_signing_key target that
|
# If the signing key is not found, create a phony gen_secure_boot_signing_key target that
|
||||||
# fails the build. fail_at_build_time causes a cmake run next time
|
# fails the build. fail_at_build_time causes a cmake run next time
|
||||||
# (to pick up a new signing key if one exists, etc.)
|
# (to pick up a new signing key if one exists, etc.)
|
||||||
if(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME)
|
if(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
|
||||||
fail_at_build_time(gen_secure_boot_signing_key
|
fail_at_build_time(gen_secure_boot_signing_key
|
||||||
"Secure Boot Signing Key ${CONFIG_SECURE_BOOT_SIGNING_KEY} does not exist. Generate using:"
|
"Secure Boot Signing Key ${CONFIG_SECURE_BOOT_SIGNING_KEY} does not exist. Generate using:"
|
||||||
"\tidf.py secure-generate-signing-key ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
|
"\tidf.py secure-generate-signing-key ${CONFIG_SECURE_BOOT_SIGNING_KEY}")
|
||||||
|
@ -15,7 +15,7 @@ set(srcs
|
|||||||
"src/secure_boot.c"
|
"src/secure_boot.c"
|
||||||
)
|
)
|
||||||
|
|
||||||
if(NOT CONFIG_IDF_ENV_FPGA)
|
if(NOT CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING)
|
||||||
# For FPGA ENV, bootloader_random implementation is implemented in `bootloader_random.c`
|
# For FPGA ENV, bootloader_random implementation is implemented in `bootloader_random.c`
|
||||||
list(APPEND srcs "src/bootloader_random_${IDF_TARGET}.c")
|
list(APPEND srcs "src/bootloader_random_${IDF_TARGET}.c")
|
||||||
endif()
|
endif()
|
||||||
|
@ -18,19 +18,8 @@
|
|||||||
#endif
|
#endif
|
||||||
#include "hal/spi_flash_ll.h"
|
#include "hal/spi_flash_ll.h"
|
||||||
#include "rom/spi_flash.h"
|
#include "rom/spi_flash.h"
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
#if !CONFIG_IDF_TARGET_ESP32
|
||||||
# include "soc/spi_struct.h"
|
#include "hal/spimem_flash_ll.h"
|
||||||
# include "soc/spi_reg.h"
|
|
||||||
/* SPI flash controller */
|
|
||||||
# define SPIFLASH SPI1
|
|
||||||
# define SPI0 SPI0
|
|
||||||
#else
|
|
||||||
# include "hal/spimem_flash_ll.h"
|
|
||||||
# include "soc/spi_mem_struct.h"
|
|
||||||
# include "soc/spi_mem_reg.h"
|
|
||||||
/* SPI flash controller */
|
|
||||||
# define SPIFLASH SPIMEM1
|
|
||||||
# define SPI0 SPIMEM0
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// This dependency will be removed in the future. IDF-5025
|
// This dependency will be removed in the future. IDF-5025
|
||||||
@ -334,7 +323,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
|
|||||||
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
|
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
#if CONFIG_IDF_TARGET_ESP32
|
||||||
//Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
|
//Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
|
||||||
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
|
// Return value unused if asserts are disabled
|
||||||
|
int e __attribute__((unused)) = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
|
||||||
assert(e == 0);
|
assert(e == 0);
|
||||||
#else
|
#else
|
||||||
uint32_t actual_mapped_len = 0;
|
uint32_t actual_mapped_len = 0;
|
||||||
@ -587,61 +577,43 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
|
|||||||
{
|
{
|
||||||
assert(mosi_len <= 32);
|
assert(mosi_len <= 32);
|
||||||
assert(miso_len <= 32);
|
assert(miso_len <= 32);
|
||||||
uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
|
uint32_t old_ctrl_reg = 0;
|
||||||
uint32_t old_user_reg = SPIFLASH.user.val;
|
uint32_t old_user_reg = 0;
|
||||||
uint32_t old_user1_reg = SPIFLASH.user1.val;
|
uint32_t old_user1_reg = 0;
|
||||||
uint32_t old_user2_reg = SPIFLASH.user2.val;
|
uint32_t old_user2_reg = 0;
|
||||||
// Clear ctrl regs.
|
spi_flash_ll_get_common_command_register_info(&SPIMEM_LL_APB, &old_ctrl_reg, &old_user_reg, &old_user1_reg, &old_user2_reg);
|
||||||
SPIFLASH.ctrl.val = 0;
|
SPIMEM_LL_APB.ctrl.val = 0;
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
#if CONFIG_IDF_TARGET_ESP32
|
||||||
spi_flash_ll_set_wp_level(&SPIFLASH, true);
|
spi_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
|
||||||
#else
|
#else
|
||||||
spimem_flash_ll_set_wp_level(&SPIFLASH, true);
|
spimem_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
|
||||||
#endif
|
#endif
|
||||||
//command phase
|
//command phase
|
||||||
SPIFLASH.user.usr_command = 1;
|
spi_flash_ll_set_command(&SPIMEM_LL_APB, command, 8);
|
||||||
SPIFLASH.user2.usr_command_bitlen = 7;
|
|
||||||
SPIFLASH.user2.usr_command_value = command;
|
|
||||||
//addr phase
|
//addr phase
|
||||||
SPIFLASH.user.usr_addr = addr_len > 0;
|
spi_flash_ll_set_addr_bitlen(&SPIMEM_LL_APB, addr_len);
|
||||||
SPIFLASH.user1.usr_addr_bitlen = addr_len - 1;
|
spi_flash_ll_set_usr_address(&SPIMEM_LL_APB, address, addr_len);
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
|
||||||
SPIFLASH.addr = (addr_len > 0)? (address << (32-addr_len)) : 0;
|
|
||||||
#else
|
|
||||||
SPIFLASH.addr = address;
|
|
||||||
#endif
|
|
||||||
//dummy phase
|
//dummy phase
|
||||||
uint32_t total_dummy = dummy_len;
|
uint32_t total_dummy = dummy_len;
|
||||||
if (miso_len > 0) {
|
if (miso_len > 0) {
|
||||||
total_dummy += g_rom_spiflash_dummy_len_plus[1];
|
total_dummy += g_rom_spiflash_dummy_len_plus[1];
|
||||||
}
|
}
|
||||||
SPIFLASH.user.usr_dummy = total_dummy > 0;
|
spi_flash_ll_set_dummy(&SPIMEM_LL_APB, total_dummy);
|
||||||
SPIFLASH.user1.usr_dummy_cyclelen = total_dummy - 1;
|
|
||||||
//output data
|
//output data
|
||||||
SPIFLASH.user.usr_mosi = mosi_len > 0;
|
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
spi_flash_ll_set_mosi_bitlen(&SPIMEM_LL_APB, mosi_len);
|
||||||
SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
|
spi_flash_ll_set_buffer_data(&SPIMEM_LL_APB, &mosi_data, mosi_len / 8);
|
||||||
#else
|
|
||||||
SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
|
|
||||||
#endif
|
|
||||||
SPIFLASH.data_buf[0] = mosi_data;
|
|
||||||
//input data
|
//input data
|
||||||
SPIFLASH.user.usr_miso = miso_len > 0;
|
spi_flash_ll_set_miso_bitlen(&SPIMEM_LL_APB, miso_len);
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
|
||||||
SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
|
|
||||||
#else
|
|
||||||
SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
SPIFLASH.cmd.usr = 1;
|
spi_flash_ll_user_start(&SPIMEM_LL_APB, false);
|
||||||
while (SPIFLASH.cmd.usr != 0) {
|
while(!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
|
||||||
}
|
}
|
||||||
SPIFLASH.ctrl.val = old_ctrl_reg;
|
spi_flash_ll_set_common_command_register_info(&SPIMEM_LL_APB, old_ctrl_reg, old_user_reg, old_user1_reg, old_user2_reg);
|
||||||
SPIFLASH.user.val = old_user_reg;
|
|
||||||
SPIFLASH.user1.val = old_user1_reg;
|
|
||||||
SPIFLASH.user2.val = old_user2_reg;
|
|
||||||
|
|
||||||
uint32_t ret = SPIFLASH.data_buf[0];
|
uint32_t output_data = 0;
|
||||||
|
spi_flash_ll_get_buffer_data(&SPIMEM_LL_APB, &output_data, miso_len / 8);
|
||||||
|
uint32_t ret = output_data;
|
||||||
if (miso_len < 32) {
|
if (miso_len < 32) {
|
||||||
//set unused bits to 0
|
//set unused bits to 0
|
||||||
ret &= ~(UINT32_MAX << miso_len);
|
ret &= ~(UINT32_MAX << miso_len);
|
||||||
@ -793,28 +765,9 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
|
|||||||
|
|
||||||
#endif //XMC_SUPPORT
|
#endif //XMC_SUPPORT
|
||||||
|
|
||||||
FORCE_INLINE_ATTR void bootloader_mspi_reset(void)
|
|
||||||
{
|
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
|
||||||
SPI1.slave.sync_reset = 0;
|
|
||||||
SPI0.slave.sync_reset = 0;
|
|
||||||
SPI1.slave.sync_reset = 1;
|
|
||||||
SPI0.slave.sync_reset = 1;
|
|
||||||
SPI1.slave.sync_reset = 0;
|
|
||||||
SPI0.slave.sync_reset = 0;
|
|
||||||
#else
|
|
||||||
SPIMEM1.ctrl2.sync_reset = 0;
|
|
||||||
SPIMEM0.ctrl2.sync_reset = 0;
|
|
||||||
SPIMEM1.ctrl2.sync_reset = 1;
|
|
||||||
SPIMEM0.ctrl2.sync_reset = 1;
|
|
||||||
SPIMEM1.ctrl2.sync_reset = 0;
|
|
||||||
SPIMEM0.ctrl2.sync_reset = 0;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
|
esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
|
||||||
{
|
{
|
||||||
bootloader_mspi_reset();
|
spi_flash_ll_sync_reset();
|
||||||
// Seems that sync_reset cannot make host totally idle.'
|
// Seems that sync_reset cannot make host totally idle.'
|
||||||
// Sending an extra(useless) command to make the host idle in order to send reset command.
|
// Sending an extra(useless) command to make the host idle in order to send reset command.
|
||||||
bootloader_execute_flash_command(0x05, 0, 0, 0);
|
bootloader_execute_flash_command(0x05, 0, 0, 0);
|
||||||
@ -844,7 +797,7 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
|
|||||||
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
|
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
|
||||||
{
|
{
|
||||||
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
|
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
|
||||||
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
|
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPIMEM_LL_CACHE);
|
||||||
#if CONFIG_IDF_TARGET_ESP32
|
#if CONFIG_IDF_TARGET_ESP32
|
||||||
if (spi_ctrl & SPI_FREAD_QIO) {
|
if (spi_ctrl & SPI_FREAD_QIO) {
|
||||||
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
|
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -28,12 +28,12 @@
|
|||||||
#include "bootloader_flash_priv.h"
|
#include "bootloader_flash_priv.h"
|
||||||
#include "bootloader_init.h"
|
#include "bootloader_init.h"
|
||||||
|
|
||||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
|
||||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0
|
||||||
#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
|
#define FLASH_SPIQ_IO MSPI_IOMUX_PIN_NUM_MISO
|
||||||
#define FLASH_SPID_IO SPI_D_GPIO_NUM
|
#define FLASH_SPID_IO MSPI_IOMUX_PIN_NUM_MOSI
|
||||||
#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
|
#define FLASH_SPIWP_IO MSPI_IOMUX_PIN_NUM_WP
|
||||||
#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
|
#define FLASH_SPIHD_IO MSPI_IOMUX_PIN_NUM_HD
|
||||||
|
|
||||||
void bootloader_flash_update_id(void)
|
void bootloader_flash_update_id(void)
|
||||||
{
|
{
|
||||||
@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
|
|||||||
} else {
|
} else {
|
||||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||||
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
|
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
|
||||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
|
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
|
||||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
|
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
|
||||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
|
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
|
||||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
|
esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
|
||||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
|
esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
|
||||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
|
esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
|
||||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
|
esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
|
||||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
|
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
|
||||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
|
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
|
||||||
//select pin function gpio
|
//select pin function gpio
|
||||||
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
|
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
|
||||||
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
|
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
|
||||||
@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
|
|||||||
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
|
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
|
||||||
return ESP32_PICO_V3_GPIO;
|
return ESP32_PICO_V3_GPIO;
|
||||||
default:
|
default:
|
||||||
return SPI_WP_GPIO_NUM;
|
return MSPI_IOMUX_PIN_NUM_WP;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
|||||||
{
|
{
|
||||||
// IDF-4066
|
// IDF-4066
|
||||||
const uint32_t spiconfig = 0;
|
const uint32_t spiconfig = 0;
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
if (spiconfig == 0) {
|
if (spiconfig == 0) {
|
||||||
|
|
||||||
}
|
}
|
||||||
|
@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
|||||||
{
|
{
|
||||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
if (spiconfig == 0) {
|
if (spiconfig == 0) {
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
|
@ -74,12 +74,12 @@ static const char *TAG = "boot.esp32c5";
|
|||||||
|
|
||||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||||
{
|
{
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||||
|
@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6";
|
|||||||
|
|
||||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||||
{
|
{
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||||
|
@ -24,6 +24,7 @@
|
|||||||
#include "hal/mmu_ll.h"
|
#include "hal/mmu_ll.h"
|
||||||
#include "hal/cache_hal.h"
|
#include "hal/cache_hal.h"
|
||||||
#include "hal/cache_ll.h"
|
#include "hal/cache_ll.h"
|
||||||
|
#include "hal/mspi_timing_tuning_ll.h"
|
||||||
|
|
||||||
static const char *TAG __attribute__((unused)) = "boot.esp32c61";
|
static const char *TAG __attribute__((unused)) = "boot.esp32c61";
|
||||||
|
|
||||||
@ -69,12 +70,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
|
|||||||
|
|
||||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||||
{
|
{
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||||
@ -197,6 +198,13 @@ static void bootloader_spi_flash_resume(void)
|
|||||||
|
|
||||||
esp_err_t bootloader_init_spi_flash(void)
|
esp_err_t bootloader_init_spi_flash(void)
|
||||||
{
|
{
|
||||||
|
|
||||||
|
// Set source mspi pll clock as 80M in bootloader stage.
|
||||||
|
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
|
||||||
|
// in this stage, set divider as 6
|
||||||
|
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
|
||||||
|
mspi_ll_fast_set_hs_divider(6);
|
||||||
|
|
||||||
bootloader_init_flash_configure();
|
bootloader_init_flash_configure();
|
||||||
bootloader_spi_flash_resume();
|
bootloader_spi_flash_resume();
|
||||||
bootloader_flash_unlock();
|
bootloader_flash_unlock();
|
||||||
|
@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2";
|
|||||||
|
|
||||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||||
{
|
{
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||||
|
@ -66,12 +66,12 @@ static const char *TAG = "boot.esp32p4";
|
|||||||
|
|
||||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||||
{
|
{
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
|||||||
{
|
{
|
||||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
if (spiconfig == 0) {
|
if (spiconfig == 0) {
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
|
@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
|||||||
{
|
{
|
||||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||||
if (spiconfig == 0) {
|
if (spiconfig == 0) {
|
||||||
|
|
||||||
} else {
|
} else {
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -181,6 +181,20 @@ uint32_t bootloader_common_get_chip_ver_pkg(void);
|
|||||||
*/
|
*/
|
||||||
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type);
|
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type);
|
||||||
|
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32
|
||||||
|
/**
|
||||||
|
* @brief Check the eFuse block revision
|
||||||
|
*
|
||||||
|
* @param[in] min_rev_full The required minimum revision of the eFuse block
|
||||||
|
* @param[in] max_rev_full The required maximum revision of the eFuse block
|
||||||
|
* @return
|
||||||
|
* - ESP_OK: The eFuse block revision is in the required range.
|
||||||
|
* - ESP_OK: DISABLE_BLK_VERSION_MAJOR has been set in the eFuse of the SoC. No requirements shall be checked at this time.
|
||||||
|
* - ESP_FAIL: The eFuse block revision of this chip does not match the requirement of the current image.
|
||||||
|
*/
|
||||||
|
esp_err_t bootloader_common_check_efuse_blk_validity(uint32_t min_rev_full, uint32_t max_rev_full);
|
||||||
|
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
|
* @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
|
||||||
*/
|
*/
|
||||||
|
@ -33,6 +33,8 @@
|
|||||||
#include "esp32p4/rom/secure_boot.h"
|
#include "esp32p4/rom/secure_boot.h"
|
||||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||||
#include "esp32c5/rom/secure_boot.h"
|
#include "esp32c5/rom/secure_boot.h"
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32C61
|
||||||
|
#include "esp32c61/rom/secure_boot.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SECURE_BOOT_V1_ENABLED
|
#ifdef CONFIG_SECURE_BOOT_V1_ENABLED
|
||||||
@ -85,7 +87,7 @@ typedef enum {
|
|||||||
*
|
*
|
||||||
* @return key type for the selected secure boot scheme
|
* @return key type for the selected secure boot scheme
|
||||||
*/
|
*/
|
||||||
static inline char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme)
|
static inline const char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme)
|
||||||
{
|
{
|
||||||
switch (scheme) {
|
switch (scheme) {
|
||||||
case ESP_SECURE_BOOT_V2_RSA:
|
case ESP_SECURE_BOOT_V2_RSA:
|
||||||
|
@ -27,6 +27,8 @@
|
|||||||
#include "esp32p4/rom/secure_boot.h"
|
#include "esp32p4/rom/secure_boot.h"
|
||||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||||
#include "esp32c5/rom/secure_boot.h"
|
#include "esp32c5/rom/secure_boot.h"
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32C61
|
||||||
|
#include "esp32c61/rom/secure_boot.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
@ -17,13 +17,6 @@ extern "C"
|
|||||||
*/
|
*/
|
||||||
void bootloader_ana_super_wdt_reset_config(bool enable);
|
void bootloader_ana_super_wdt_reset_config(bool enable);
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configure analog brownout reset
|
|
||||||
*
|
|
||||||
* @param enable Boolean to enable or disable brownout reset
|
|
||||||
*/
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Configure analog clock glitch reset
|
* @brief Configure analog clock glitch reset
|
||||||
*
|
*
|
||||||
|
@ -27,7 +27,7 @@
|
|||||||
#include "esp_rom_caps.h"
|
#include "esp_rom_caps.h"
|
||||||
|
|
||||||
#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
|
#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
|
||||||
#define IS_MAX_REV_SET(max_chip_rev_full) (((max_chip_rev_full) != 65535) && ((max_chip_rev_full) != 0))
|
#define IS_FIELD_SET(rev_full) (((rev_full) != 65535) && ((rev_full) != 0))
|
||||||
|
|
||||||
static const char* TAG = "boot_comm";
|
static const char* TAG = "boot_comm";
|
||||||
|
|
||||||
@ -57,6 +57,31 @@ int bootloader_common_get_active_otadata(esp_ota_select_entry_t *two_otadata)
|
|||||||
return bootloader_common_select_otadata(two_otadata, valid_two_otadata, true);
|
return bootloader_common_select_otadata(two_otadata, valid_two_otadata, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32
|
||||||
|
esp_err_t bootloader_common_check_efuse_blk_validity(uint32_t min_rev_full, uint32_t max_rev_full)
|
||||||
|
{
|
||||||
|
esp_err_t err = ESP_OK;
|
||||||
|
#ifndef CONFIG_IDF_ENV_FPGA
|
||||||
|
// Check whether the efuse block version satisfy the requirements of current image.
|
||||||
|
uint32_t revision = efuse_hal_blk_version();
|
||||||
|
uint32_t major_rev = revision / 100;
|
||||||
|
uint32_t minor_rev = revision % 100;
|
||||||
|
if (IS_FIELD_SET(min_rev_full) && !ESP_EFUSE_BLK_REV_ABOVE(revision, min_rev_full)) {
|
||||||
|
ESP_LOGE(TAG, "Image requires efuse blk rev >= v%"PRIu32".%"PRIu32", but chip is v%"PRIu32".%"PRIu32,
|
||||||
|
min_rev_full / 100, min_rev_full % 100, major_rev, minor_rev);
|
||||||
|
err = ESP_FAIL;
|
||||||
|
}
|
||||||
|
// If burnt `disable_blk_version_major` bit, skip the max version check
|
||||||
|
if ((IS_FIELD_SET(max_rev_full) && (revision > max_rev_full) && !efuse_hal_get_disable_blk_version_major())) {
|
||||||
|
ESP_LOGE(TAG, "Image requires efuse blk rev <= v%"PRIu32".%"PRIu32", but chip is v%"PRIu32".%"PRIu32,
|
||||||
|
max_rev_full / 100, max_rev_full % 100, major_rev, minor_rev);
|
||||||
|
err = ESP_FAIL;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||||
|
|
||||||
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type)
|
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type)
|
||||||
{
|
{
|
||||||
esp_err_t err = ESP_OK;
|
esp_err_t err = ESP_OK;
|
||||||
@ -80,7 +105,7 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
|
|||||||
}
|
}
|
||||||
if (type == ESP_IMAGE_APPLICATION) {
|
if (type == ESP_IMAGE_APPLICATION) {
|
||||||
unsigned max_rev = img_hdr->max_chip_rev_full;
|
unsigned max_rev = img_hdr->max_chip_rev_full;
|
||||||
if ((IS_MAX_REV_SET(max_rev) && (revision > max_rev) && !efuse_hal_get_disable_wafer_version_major())) {
|
if ((IS_FIELD_SET(max_rev) && (revision > max_rev) && !efuse_hal_get_disable_wafer_version_major())) {
|
||||||
ESP_LOGE(TAG, "Image requires chip rev <= v%d.%d, but chip is v%d.%d",
|
ESP_LOGE(TAG, "Image requires chip rev <= v%d.%d, but chip is v%d.%d",
|
||||||
max_rev / 100, max_rev % 100,
|
max_rev / 100, max_rev % 100,
|
||||||
major_rev, minor_rev);
|
major_rev, minor_rev);
|
||||||
|
@ -48,8 +48,8 @@ void bootloader_console_init(void)
|
|||||||
|
|
||||||
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
|
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
|
||||||
// Some constants to make the following code less upper-case
|
// Some constants to make the following code less upper-case
|
||||||
const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
|
const int uart_tx_gpio = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM;
|
||||||
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
|
const int uart_rx_gpio = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM;
|
||||||
|
|
||||||
// Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
|
// Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
|
||||||
esp_rom_output_set_as_console(uart_num);
|
esp_rom_output_set_as_console(uart_num);
|
||||||
|
@ -43,10 +43,17 @@ esp_err_t bootloader_read_bootloader_header(void)
|
|||||||
|
|
||||||
esp_err_t bootloader_check_bootloader_validity(void)
|
esp_err_t bootloader_check_bootloader_validity(void)
|
||||||
{
|
{
|
||||||
unsigned int revision = efuse_hal_chip_revision();
|
unsigned int chip_revision = efuse_hal_chip_revision();
|
||||||
unsigned int major = revision / 100;
|
unsigned int chip_major_rev = chip_revision / 100;
|
||||||
unsigned int minor = revision % 100;
|
unsigned int chip_minor_rev = chip_revision % 100;
|
||||||
ESP_EARLY_LOGI(TAG, "chip revision: v%d.%d", major, minor);
|
ESP_EARLY_LOGI(TAG, "chip revision: v%d.%d", chip_major_rev, chip_minor_rev);
|
||||||
|
/* ESP32 doesn't have more memory and more efuse bits for block major version. */
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32
|
||||||
|
unsigned int efuse_revision = efuse_hal_blk_version();
|
||||||
|
unsigned int efuse_major_rev = efuse_revision / 100;
|
||||||
|
unsigned int efuse_minor_rev = efuse_revision % 100;
|
||||||
|
ESP_EARLY_LOGI(TAG, "efuse block revision: v%d.%d", efuse_major_rev, efuse_minor_rev);
|
||||||
|
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||||
/* compare with the one set in bootloader image header */
|
/* compare with the one set in bootloader image header */
|
||||||
if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) {
|
if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) {
|
||||||
return ESP_FAIL;
|
return ESP_FAIL;
|
||||||
|
@ -16,6 +16,12 @@
|
|||||||
#include "hal/apm_hal.h"
|
#include "hal/apm_hal.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
|
||||||
|
#include "soc/hp_apm_reg.h"
|
||||||
|
#include "soc/lp_apm_reg.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
void bootloader_init_mem(void)
|
void bootloader_init_mem(void)
|
||||||
{
|
{
|
||||||
|
|
||||||
@ -32,6 +38,13 @@ void bootloader_init_mem(void)
|
|||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9230 Remove the workaround when APM supported on C61!
|
||||||
|
// disable apm filter
|
||||||
|
REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
|
||||||
|
REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
|
#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
|
||||||
// protect memory region
|
// protect memory region
|
||||||
esp_cpu_configure_region_protection();
|
esp_cpu_configure_region_protection();
|
||||||
|
@ -83,10 +83,10 @@
|
|||||||
}
|
}
|
||||||
#endif // BOOTLOADER_BUILD
|
#endif // BOOTLOADER_BUILD
|
||||||
|
|
||||||
#if CONFIG_IDF_ENV_FPGA
|
#if CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING
|
||||||
static void s_non_functional(const char *func)
|
static void s_non_functional(const char *func)
|
||||||
{
|
{
|
||||||
ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func);
|
ESP_EARLY_LOGW("rand", "%s non-functional as RNG has not been supported yet", func);
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_random_enable()
|
void bootloader_random_enable()
|
||||||
@ -98,4 +98,4 @@ void bootloader_random_disable()
|
|||||||
{
|
{
|
||||||
s_non_functional(__func__);
|
s_non_functional(__func__);
|
||||||
}
|
}
|
||||||
#endif // CONFIG_IDF_ENV_FPGA
|
#endif // CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING
|
||||||
|
@ -3,20 +3,100 @@
|
|||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
|
#include "sdkconfig.h"
|
||||||
|
#include "bootloader_random.h"
|
||||||
#include "soc/soc.h"
|
#include "soc/soc.h"
|
||||||
#include "soc/pcr_reg.h"
|
#include "soc/pcr_reg.h"
|
||||||
|
#include "soc/apb_saradc_reg.h"
|
||||||
#include "soc/pmu_reg.h"
|
#include "soc/pmu_reg.h"
|
||||||
#include "hal/regi2c_ctrl.h"
|
#include "hal/regi2c_ctrl.h"
|
||||||
|
#include "soc/lpperi_reg.h"
|
||||||
|
#include "soc/regi2c_saradc.h"
|
||||||
#include "esp_log.h"
|
#include "esp_log.h"
|
||||||
|
|
||||||
|
static const uint32_t SAR2_CHANNEL = 9;
|
||||||
|
static const uint32_t SAR1_CHANNEL = 7;
|
||||||
|
static const uint32_t PATTERN_BIT_WIDTH = 6;
|
||||||
|
static const uint32_t SAR1_ATTEN = 3;
|
||||||
|
static const uint32_t SAR2_ATTEN = 3;
|
||||||
|
|
||||||
void bootloader_random_enable(void)
|
void bootloader_random_enable(void)
|
||||||
{
|
{
|
||||||
// TODO: [ESP32C5] IDF-8626
|
// pull SAR ADC out of reset
|
||||||
ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
|
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
|
||||||
|
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
|
||||||
|
|
||||||
|
// enable SAR ADC APB clock
|
||||||
|
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
|
||||||
|
|
||||||
|
// pull APB register out of reset
|
||||||
|
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
|
||||||
|
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
|
||||||
|
|
||||||
|
// enable ADC_CTRL_CLK (SAR ADC function clock)
|
||||||
|
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
|
||||||
|
|
||||||
|
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
|
||||||
|
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0); // 0: XTAL; 1: 80M(from bbpll); 2. FOSC
|
||||||
|
|
||||||
|
// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
|
||||||
|
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
|
||||||
|
|
||||||
|
// some magic register poke from the digital team
|
||||||
|
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
|
||||||
|
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
|
||||||
|
|
||||||
|
// Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 1);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 1);
|
||||||
|
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x08);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x66);
|
||||||
|
|
||||||
|
// create patterns and set them in pattern table
|
||||||
|
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
|
||||||
|
uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
|
||||||
|
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
|
||||||
|
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
|
||||||
|
|
||||||
|
// set pattern length (APB_SARADC_SARADC_SAR_PATT_LEN counts from 0)
|
||||||
|
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
|
||||||
|
|
||||||
|
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
|
||||||
|
|
||||||
|
// set timer expiry (timer is ADC_CTRL_CLK)
|
||||||
|
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
|
||||||
|
|
||||||
|
// enable timer
|
||||||
|
REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
|
||||||
|
CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_random_disable(void)
|
void bootloader_random_disable(void)
|
||||||
{
|
{
|
||||||
// TODO: [ESP32C5] IDF-8626
|
// disable timer
|
||||||
ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
|
REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
|
||||||
|
|
||||||
|
// Write reset value of this register
|
||||||
|
REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
|
||||||
|
|
||||||
|
// Revert ADC I2C configuration and initial voltage source setting
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x60);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
|
||||||
|
|
||||||
|
// disable ADC_CTRL_CLK (SAR ADC function clock)
|
||||||
|
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
|
||||||
|
|
||||||
|
// Set PCR_SARADC_CONF_REG to initial state
|
||||||
|
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
|
||||||
}
|
}
|
||||||
|
@ -88,9 +88,6 @@ void bootloader_random_disable(void)
|
|||||||
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
|
||||||
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
|
||||||
|
|
||||||
// Revert PMU_RF_PWC_REG to it's initial value
|
|
||||||
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
|
|
||||||
|
|
||||||
// disable ADC_CTRL_CLK (SAR ADC function clock)
|
// disable ADC_CTRL_CLK (SAR ADC function clock)
|
||||||
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
|
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
|
||||||
|
|
||||||
|
101
components/bootloader_support/src/bootloader_random_esp32c61.c
Normal file
101
components/bootloader_support/src/bootloader_random_esp32c61.c
Normal file
@ -0,0 +1,101 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
#include "sdkconfig.h"
|
||||||
|
#include "bootloader_random.h"
|
||||||
|
#include "soc/soc.h"
|
||||||
|
#include "soc/pcr_reg.h"
|
||||||
|
#include "soc/apb_saradc_reg.h"
|
||||||
|
#include "soc/pmu_reg.h"
|
||||||
|
#include "hal/regi2c_ctrl.h"
|
||||||
|
#include "soc/regi2c_saradc.h"
|
||||||
|
#include "esp_log.h"
|
||||||
|
|
||||||
|
static const uint32_t SAR2_CHANNEL = 9;
|
||||||
|
static const uint32_t SAR1_CHANNEL = 7;
|
||||||
|
static const uint32_t PATTERN_BIT_WIDTH = 6;
|
||||||
|
static const uint32_t SAR1_ATTEN = 3;
|
||||||
|
static const uint32_t SAR2_ATTEN = 3;
|
||||||
|
|
||||||
|
void bootloader_random_enable(void)
|
||||||
|
{
|
||||||
|
// pull SAR ADC out of reset
|
||||||
|
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
|
||||||
|
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
|
||||||
|
|
||||||
|
// enable SAR ADC APB clock
|
||||||
|
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
|
||||||
|
|
||||||
|
// pull APB register out of reset
|
||||||
|
REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
|
||||||
|
REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
|
||||||
|
|
||||||
|
// enable ADC_CTRL_CLK (SAR ADC function clock)
|
||||||
|
REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
|
||||||
|
|
||||||
|
// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
|
||||||
|
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
|
||||||
|
|
||||||
|
// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
|
||||||
|
REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
|
||||||
|
|
||||||
|
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
|
||||||
|
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
|
||||||
|
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
|
||||||
|
|
||||||
|
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
|
||||||
|
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
|
||||||
|
|
||||||
|
// create patterns and set them in pattern table
|
||||||
|
uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
|
||||||
|
uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
|
||||||
|
uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
|
||||||
|
REG_WRITE(SARADC_SAR_PATT_TAB1_REG, pattern_table);
|
||||||
|
|
||||||
|
// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
|
||||||
|
REG_SET_FIELD(SARADC_CTRL_REG, SARADC_SAR_PATT_LEN, 1);
|
||||||
|
|
||||||
|
// Same as in C3
|
||||||
|
REG_SET_FIELD(SARADC_CTRL_REG, SARADC_SAR_CLK_DIV, 15);
|
||||||
|
|
||||||
|
// set timer expiry (timer is ADC_CTRL_CLK)
|
||||||
|
REG_SET_FIELD(SARADC_CTRL2_REG, SARADC_TIMER_TARGET, 200);
|
||||||
|
|
||||||
|
// enable timer
|
||||||
|
REG_SET_BIT(SARADC_CTRL2_REG, SARADC_TIMER_EN);
|
||||||
|
}
|
||||||
|
|
||||||
|
void bootloader_random_disable(void)
|
||||||
|
{
|
||||||
|
// disable timer
|
||||||
|
REG_CLR_BIT(SARADC_CTRL2_REG, SARADC_TIMER_EN);
|
||||||
|
|
||||||
|
// Write reset value of this register
|
||||||
|
REG_WRITE(SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
|
||||||
|
|
||||||
|
// Revert ADC I2C configuration and initial voltage source setting
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
|
||||||
|
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
|
||||||
|
|
||||||
|
// disable ADC_CTRL_CLK (SAR ADC function clock)
|
||||||
|
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
|
||||||
|
|
||||||
|
// Set PCR_SARADC_CONF_REG to initial state
|
||||||
|
REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
|
||||||
|
}
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -69,11 +69,11 @@ static void bootloader_reset_mmu(void)
|
|||||||
}
|
}
|
||||||
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||||
|
|
||||||
static esp_err_t bootloader_check_rated_cpu_clock(void)
|
static inline esp_err_t bootloader_check_rated_cpu_clock(void)
|
||||||
{
|
{
|
||||||
int rated_freq = bootloader_clock_get_rated_freq_mhz();
|
int rated_freq = bootloader_clock_get_rated_freq_mhz();
|
||||||
if (rated_freq < CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) {
|
if (rated_freq < CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) {
|
||||||
ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig",
|
ESP_LOGE(TAG, "Chip CPU freq rated for %dMHz, configured for %dMHz. Modify CPU freq in menuconfig",
|
||||||
rated_freq, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
|
rated_freq, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
|
||||||
return ESP_FAIL;
|
return ESP_FAIL;
|
||||||
}
|
}
|
||||||
@ -119,19 +119,19 @@ static void wdt_reset_info_dump(int cpu)
|
|||||||
|
|
||||||
if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
|
if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
|
||||||
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
|
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
|
||||||
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
|
ESP_LOGW(TAG, "WDT rst info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
|
||||||
} else {
|
} else {
|
||||||
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
|
ESP_LOGW(TAG, "WDT rst info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
|
||||||
}
|
}
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
|
||||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
|
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void bootloader_check_wdt_reset(void)
|
static void bootloader_check_wdt_reset(void)
|
||||||
@ -143,12 +143,12 @@ static void bootloader_check_wdt_reset(void)
|
|||||||
rst_reas[1] = esp_rom_get_reset_reason(1);
|
rst_reas[1] = esp_rom_get_reset_reason(1);
|
||||||
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
|
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
|
||||||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
|
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
|
||||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
ESP_LOGW(TAG, "PRO CPU has been reset by WDT");
|
||||||
wdt_rst = 1;
|
wdt_rst = 1;
|
||||||
}
|
}
|
||||||
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
|
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
|
||||||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
|
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
|
||||||
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
|
ESP_LOGW(TAG, "APP CPU has been reset by WDT");
|
||||||
wdt_rst = 1;
|
wdt_rst = 1;
|
||||||
}
|
}
|
||||||
if (wdt_rst) {
|
if (wdt_rst) {
|
||||||
@ -215,7 +215,7 @@ esp_err_t bootloader_init(void)
|
|||||||
bootloader_flash_update_id();
|
bootloader_flash_update_id();
|
||||||
// Check and run XMC startup flow
|
// Check and run XMC startup flow
|
||||||
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
||||||
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
|
ESP_LOGE(TAG, "XMC startup flow failed, reboot!");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
// read bootloader header
|
// read bootloader header
|
||||||
@ -232,7 +232,7 @@ esp_err_t bootloader_init(void)
|
|||||||
}
|
}
|
||||||
#endif // #if !CONFIG_APP_BUILD_TYPE_RAM
|
#endif // #if !CONFIG_APP_BUILD_TYPE_RAM
|
||||||
|
|
||||||
// check whether a WDT reset happend
|
// check whether a WDT reset happened
|
||||||
bootloader_check_wdt_reset();
|
bootloader_check_wdt_reset();
|
||||||
// config WDT
|
// config WDT
|
||||||
bootloader_config_wdt();
|
bootloader_config_wdt();
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -37,6 +37,7 @@
|
|||||||
#include "hal/mmu_hal.h"
|
#include "hal/mmu_hal.h"
|
||||||
#include "hal/cache_hal.h"
|
#include "hal/cache_hal.h"
|
||||||
#include "hal/rwdt_ll.h"
|
#include "hal/rwdt_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32c2";
|
static const char *TAG = "boot.esp32c2";
|
||||||
|
|
||||||
@ -81,8 +82,8 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
{
|
{
|
||||||
//Enable super WDT reset.
|
//Enable super WDT reset.
|
||||||
bootloader_ana_super_wdt_reset_config(true);
|
bootloader_ana_super_wdt_reset_config(true);
|
||||||
//Enable BOD reset
|
//Enable BOD reset (mode1)
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t bootloader_init(void)
|
esp_err_t bootloader_init(void)
|
||||||
@ -138,7 +139,7 @@ esp_err_t bootloader_init(void)
|
|||||||
}
|
}
|
||||||
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
||||||
|
|
||||||
// check whether a WDT reset happend
|
// check whether a WDT reset happened
|
||||||
bootloader_check_wdt_reset();
|
bootloader_check_wdt_reset();
|
||||||
// config WDT
|
// config WDT
|
||||||
bootloader_config_wdt();
|
bootloader_config_wdt();
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -18,17 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
|
|
||||||
|
|
||||||
if (enable) {
|
|
||||||
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
|
||||||
} else {
|
|
||||||
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//Not supported but common bootloader calls the function. Do nothing
|
//Not supported but common bootloader calls the function. Do nothing
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -42,6 +42,7 @@
|
|||||||
#include "hal/cache_hal.h"
|
#include "hal/cache_hal.h"
|
||||||
#include "hal/efuse_hal.h"
|
#include "hal/efuse_hal.h"
|
||||||
#include "hal/rwdt_ll.h"
|
#include "hal/rwdt_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32c3";
|
static const char *TAG = "boot.esp32c3";
|
||||||
|
|
||||||
@ -106,18 +107,18 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
case 0:
|
case 0:
|
||||||
case 1:
|
case 1:
|
||||||
//Disable BOD and GLITCH reset
|
//Disable BOD and GLITCH reset
|
||||||
bootloader_ana_bod_reset_config(false);
|
brownout_ll_ana_reset_enable(false);
|
||||||
bootloader_ana_clock_glitch_reset_config(false);
|
bootloader_ana_clock_glitch_reset_config(false);
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
//Enable BOD reset. Disable GLITCH reset
|
//Enable BOD reset. Disable GLITCH reset
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
bootloader_ana_clock_glitch_reset_config(false);
|
bootloader_ana_clock_glitch_reset_config(false);
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
default:
|
default:
|
||||||
//Enable BOD, and GLITCH reset
|
//Enable BOD, and GLITCH reset
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
bootloader_ana_clock_glitch_reset_config(true);
|
bootloader_ana_clock_glitch_reset_config(true);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -182,7 +183,7 @@ esp_err_t bootloader_init(void)
|
|||||||
}
|
}
|
||||||
#endif //#if !CONFIG_APP_BUILD_TYPE_RAM
|
#endif //#if !CONFIG_APP_BUILD_TYPE_RAM
|
||||||
|
|
||||||
// check whether a WDT reset happend
|
// check whether a WDT reset happened
|
||||||
bootloader_check_wdt_reset();
|
bootloader_check_wdt_reset();
|
||||||
// config WDT
|
// config WDT
|
||||||
bootloader_config_wdt();
|
bootloader_config_wdt();
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -18,17 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
|
|
||||||
|
|
||||||
if (enable) {
|
|
||||||
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
|
||||||
} else {
|
|
||||||
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
|
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
|
||||||
|
@ -42,6 +42,7 @@
|
|||||||
#include "hal/efuse_hal.h"
|
#include "hal/efuse_hal.h"
|
||||||
#include "hal/lpwdt_ll.h"
|
#include "hal/lpwdt_ll.h"
|
||||||
#include "hal/regi2c_ctrl_ll.h"
|
#include "hal/regi2c_ctrl_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32c5";
|
static const char *TAG = "boot.esp32c5";
|
||||||
|
|
||||||
@ -94,9 +95,8 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
// TODO: [ESP32C5] IDF-8650
|
// TODO: [ESP32C5] IDF-8650
|
||||||
//Enable super WDT reset.
|
//Enable super WDT reset.
|
||||||
// bootloader_ana_super_wdt_reset_config(true);
|
// bootloader_ana_super_wdt_reset_config(true);
|
||||||
// TODO: [ESP32C5] IDF-8647
|
//Enable BOD reset (mode1)
|
||||||
//Enable BOD reset
|
brownout_ll_ana_reset_enable(true);
|
||||||
// bootloader_ana_bod_reset_config(true);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t bootloader_init(void)
|
esp_err_t bootloader_init(void)
|
||||||
|
@ -16,15 +16,9 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
|
ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
// TODO: [ESP32C5] IDF-8667
|
|
||||||
ESP_EARLY_LOGW("bootloader", "bootloader_ana_bod_reset_config() has not been implemented on C5 yet");
|
|
||||||
}
|
|
||||||
|
|
||||||
//Not supported but common bootloader calls the function. Do nothing
|
//Not supported but common bootloader calls the function. Do nothing
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
// TODO: [ESP32C5] IDF-8667
|
// TODO: [ESP32C5] IDF-8667, PM-207
|
||||||
(void)enable;
|
(void)enable;
|
||||||
}
|
}
|
||||||
|
@ -44,6 +44,7 @@
|
|||||||
#include "hal/efuse_hal.h"
|
#include "hal/efuse_hal.h"
|
||||||
#include "hal/lpwdt_ll.h"
|
#include "hal/lpwdt_ll.h"
|
||||||
#include "hal/regi2c_ctrl_ll.h"
|
#include "hal/regi2c_ctrl_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32c6";
|
static const char *TAG = "boot.esp32c6";
|
||||||
|
|
||||||
@ -103,8 +104,8 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
{
|
{
|
||||||
//Enable super WDT reset.
|
//Enable super WDT reset.
|
||||||
bootloader_ana_super_wdt_reset_config(true);
|
bootloader_ana_super_wdt_reset_config(true);
|
||||||
//Enable BOD reset
|
//Enable BOD mode1 hardware reset
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t bootloader_init(void)
|
esp_err_t bootloader_init(void)
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -15,17 +15,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
|
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
|
|
||||||
|
|
||||||
if (enable) {
|
|
||||||
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
|
||||||
} else {
|
|
||||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//Not supported but common bootloader calls the function. Do nothing
|
//Not supported but common bootloader calls the function. Do nothing
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
|
@ -39,11 +39,11 @@
|
|||||||
#include "esp_efuse.h"
|
#include "esp_efuse.h"
|
||||||
#include "hal/mmu_hal.h"
|
#include "hal/mmu_hal.h"
|
||||||
#include "hal/cache_hal.h"
|
#include "hal/cache_hal.h"
|
||||||
#include "hal/clk_tree_ll.h"
|
|
||||||
#include "soc/lp_wdt_reg.h"
|
#include "soc/lp_wdt_reg.h"
|
||||||
#include "hal/efuse_hal.h"
|
#include "hal/efuse_hal.h"
|
||||||
#include "hal/lpwdt_ll.h"
|
#include "hal/lpwdt_ll.h"
|
||||||
#include "hal/regi2c_ctrl_ll.h"
|
#include "hal/regi2c_ctrl_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32c61";
|
static const char *TAG = "boot.esp32c61";
|
||||||
|
|
||||||
@ -86,15 +86,6 @@ static void bootloader_super_wdt_auto_feed(void)
|
|||||||
|
|
||||||
static inline void bootloader_hardware_init(void)
|
static inline void bootloader_hardware_init(void)
|
||||||
{
|
{
|
||||||
// In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here
|
|
||||||
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM
|
|
||||||
clk_ll_mspi_fast_set_hs_divider(6);
|
|
||||||
esp_rom_spiflash_config_clk(1, 0);
|
|
||||||
esp_rom_spiflash_config_clk(1, 1);
|
|
||||||
esp_rom_spiflash_fix_dummylen(0, 1);
|
|
||||||
esp_rom_spiflash_fix_dummylen(1, 1);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
regi2c_ctrl_ll_master_enable_clock(true);
|
regi2c_ctrl_ll_master_enable_clock(true);
|
||||||
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
|
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
|
||||||
regi2c_ctrl_ll_master_configure_clock();
|
regi2c_ctrl_ll_master_configure_clock();
|
||||||
@ -104,8 +95,8 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
{
|
{
|
||||||
//Enable super WDT reset.
|
//Enable super WDT reset.
|
||||||
bootloader_ana_super_wdt_reset_config(true);
|
bootloader_ana_super_wdt_reset_config(true);
|
||||||
//Enable BOD reset
|
//Enable BOD reset (mode1)
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t bootloader_init(void)
|
esp_err_t bootloader_init(void)
|
||||||
|
@ -18,18 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
// REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
|
// REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
// lp_analog_peri_reg.h updated, now following registers
|
|
||||||
// REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
|
|
||||||
|
|
||||||
if (enable) {
|
|
||||||
REG_SET_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
|
|
||||||
} else {
|
|
||||||
REG_CLR_BIT(LP_ANA_BOD_MODE1_CNTL_REG, LP_ANA_BOD_MODE1_RESET_ENA);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//Not supported but common bootloader calls the function. Do nothing
|
//Not supported but common bootloader calls the function. Do nothing
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
|
@ -0,0 +1,71 @@
|
|||||||
|
/*
|
||||||
|
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <strings.h>
|
||||||
|
#include "esp_flash_encrypt.h"
|
||||||
|
#include "esp_secure_boot.h"
|
||||||
|
#include "esp_efuse.h"
|
||||||
|
#include "esp_efuse_table.h"
|
||||||
|
#include "esp_log.h"
|
||||||
|
#include "sdkconfig.h"
|
||||||
|
|
||||||
|
static __attribute__((unused)) const char *TAG = "secure_boot";
|
||||||
|
|
||||||
|
esp_err_t esp_secure_boot_enable_secure_features(void)
|
||||||
|
{
|
||||||
|
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||||
|
|
||||||
|
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
|
||||||
|
ESP_LOGI(TAG, "Enabling Security download mode...");
|
||||||
|
esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
|
||||||
|
if (err != ESP_OK) {
|
||||||
|
ESP_LOGE(TAG, "Could not enable Security download mode...");
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
|
||||||
|
ESP_LOGI(TAG, "Disable ROM Download mode...");
|
||||||
|
esp_err_t err = esp_efuse_disable_rom_download_mode();
|
||||||
|
if (err != ESP_OK) {
|
||||||
|
ESP_LOGE(TAG, "Could not disable ROM Download mode...");
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||||
|
ESP_LOGI(TAG, "Disable hardware & software JTAG...");
|
||||||
|
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||||
|
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||||
|
// TODO in IDF-10694
|
||||||
|
// esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
|
||||||
|
#else
|
||||||
|
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
|
||||||
|
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
|
||||||
|
|
||||||
|
#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||||
|
bool rd_dis_now = true;
|
||||||
|
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
|
||||||
|
/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
|
||||||
|
when Flash Encryption is being enabled */
|
||||||
|
rd_dis_now = esp_flash_encryption_enabled();
|
||||||
|
#endif
|
||||||
|
if (rd_dis_now) {
|
||||||
|
ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
|
||||||
|
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return ESP_OK;
|
||||||
|
}
|
@ -43,6 +43,7 @@
|
|||||||
#include "soc/pmu_reg.h"
|
#include "soc/pmu_reg.h"
|
||||||
#include "hal/efuse_hal.h"
|
#include "hal/efuse_hal.h"
|
||||||
#include "hal/regi2c_ctrl_ll.h"
|
#include "hal/regi2c_ctrl_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32h2";
|
static const char *TAG = "boot.esp32h2";
|
||||||
|
|
||||||
@ -97,8 +98,8 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
{
|
{
|
||||||
//Enable super WDT reset.
|
//Enable super WDT reset.
|
||||||
bootloader_ana_super_wdt_reset_config(true);
|
bootloader_ana_super_wdt_reset_config(true);
|
||||||
//Enable BOD reset
|
//Enable BOD reset (mode1)
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t bootloader_init(void)
|
esp_err_t bootloader_init(void)
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -13,17 +13,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
|
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
|
|
||||||
|
|
||||||
if (enable) {
|
|
||||||
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
|
||||||
} else {
|
|
||||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//Not supported but common bootloader calls the function. Do nothing
|
//Not supported but common bootloader calls the function. Do nothing
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
|
@ -49,6 +49,7 @@
|
|||||||
#include "soc/regi2c_bias.h"
|
#include "soc/regi2c_bias.h"
|
||||||
#include "esp_private/periph_ctrl.h"
|
#include "esp_private/periph_ctrl.h"
|
||||||
#include "hal/regi2c_ctrl_ll.h"
|
#include "hal/regi2c_ctrl_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
|
|
||||||
static const char *TAG = "boot.esp32p4";
|
static const char *TAG = "boot.esp32p4";
|
||||||
|
|
||||||
@ -120,8 +121,8 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
{
|
{
|
||||||
//Enable super WDT reset.
|
//Enable super WDT reset.
|
||||||
bootloader_ana_super_wdt_reset_config(true);
|
bootloader_ana_super_wdt_reset_config(true);
|
||||||
//Enable BOD reset
|
//Enable BOD reset (mode1)
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t bootloader_init(void)
|
esp_err_t bootloader_init(void)
|
||||||
|
@ -5,21 +5,12 @@
|
|||||||
*/
|
*/
|
||||||
#include <stdbool.h>
|
#include <stdbool.h>
|
||||||
#include "soc/lp_analog_peri_reg.h"
|
#include "soc/lp_analog_peri_reg.h"
|
||||||
#include "soc/soc.h"
|
|
||||||
#include "hal/brownout_ll.h"
|
|
||||||
|
|
||||||
void bootloader_ana_super_wdt_reset_config(bool enable)
|
void bootloader_ana_super_wdt_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
//TODO: IDF-7514
|
//TODO: IDF-7514
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
REG_CLR_BIT(LP_ANALOG_PERI_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST);
|
|
||||||
|
|
||||||
brownout_ll_ana_reset_enable(enable);
|
|
||||||
}
|
|
||||||
|
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
//TODO: IDF-7514
|
//TODO: IDF-7514
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -39,6 +39,7 @@
|
|||||||
#include "hal/mmu_hal.h"
|
#include "hal/mmu_hal.h"
|
||||||
#include "hal/cache_hal.h"
|
#include "hal/cache_hal.h"
|
||||||
#include "hal/rwdt_ll.h"
|
#include "hal/rwdt_ll.h"
|
||||||
|
#include "hal/brownout_ll.h"
|
||||||
#include "xtensa/config/core.h"
|
#include "xtensa/config/core.h"
|
||||||
#include "xt_instr_macros.h"
|
#include "xt_instr_macros.h"
|
||||||
|
|
||||||
@ -133,7 +134,7 @@ static inline void bootloader_ana_reset_config(void)
|
|||||||
{
|
{
|
||||||
//Enable WDT, BOD, and GLITCH reset
|
//Enable WDT, BOD, and GLITCH reset
|
||||||
bootloader_ana_super_wdt_reset_config(true);
|
bootloader_ana_super_wdt_reset_config(true);
|
||||||
bootloader_ana_bod_reset_config(true);
|
brownout_ll_ana_reset_enable(true);
|
||||||
bootloader_ana_clock_glitch_reset_config(true);
|
bootloader_ana_clock_glitch_reset_config(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -204,7 +205,7 @@ esp_err_t bootloader_init(void)
|
|||||||
}
|
}
|
||||||
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
||||||
|
|
||||||
// check whether a WDT reset happend
|
// check whether a WDT reset happened
|
||||||
bootloader_check_wdt_reset();
|
bootloader_check_wdt_reset();
|
||||||
// config WDT
|
// config WDT
|
||||||
bootloader_config_wdt();
|
bootloader_config_wdt();
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -18,17 +18,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void bootloader_ana_bod_reset_config(bool enable)
|
|
||||||
{
|
|
||||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
|
|
||||||
|
|
||||||
if (enable) {
|
|
||||||
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
|
||||||
} else {
|
|
||||||
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||||
{
|
{
|
||||||
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
|
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
|
||||||
|
@ -691,19 +691,28 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
|
|||||||
|
|
||||||
const uint32_t *src = data;
|
const uint32_t *src = data;
|
||||||
|
|
||||||
#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
|
||||||
// Case I: Bootloader verifying application
|
// Case I: Bootloader verifying application
|
||||||
// Case II: Bootloader verifying bootloader
|
// Case II: Bootloader verifying bootloader
|
||||||
// Anti-rollback check should handle only Case I from above.
|
// The esp_app_desc_t structure is located in DROM and is always in segment #0.
|
||||||
|
// Anti-rollback check and efuse block version check should handle only Case I from above.
|
||||||
if (segment == 0 && metadata->start_addr != ESP_BOOTLOADER_OFFSET) {
|
if (segment == 0 && metadata->start_addr != ESP_BOOTLOADER_OFFSET) {
|
||||||
|
/* ESP32 doesn't have more memory and more efuse bits for block major version. */
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32
|
||||||
|
const esp_app_desc_t *app_desc = (const esp_app_desc_t *)src;
|
||||||
|
esp_err_t ret = bootloader_common_check_efuse_blk_validity(app_desc->min_efuse_blk_rev_full, app_desc->max_efuse_blk_rev_full);
|
||||||
|
if (ret != ESP_OK) {
|
||||||
|
bootloader_munmap(data);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||||
|
#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
||||||
ESP_LOGD(TAG, "additional anti-rollback check 0x%"PRIx32, data_addr);
|
ESP_LOGD(TAG, "additional anti-rollback check 0x%"PRIx32, data_addr);
|
||||||
// The esp_app_desc_t structure is located in DROM and is always in segment #0.
|
|
||||||
size_t len = process_esp_app_desc_data(src, sha_handle, checksum, metadata);
|
size_t len = process_esp_app_desc_data(src, sha_handle, checksum, metadata);
|
||||||
data_len -= len;
|
data_len -= len;
|
||||||
src += len / 4;
|
src += len / 4;
|
||||||
// In BOOTLOADER_BUILD, for DROM (segment #0) we do not load it into dest (only map it), do_load = false.
|
// In BOOTLOADER_BUILD, for DROM (segment #0) we do not load it into dest (only map it), do_load = false.
|
||||||
}
|
|
||||||
#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
||||||
|
}
|
||||||
|
|
||||||
for (size_t i = 0; i < data_len; i += 4) {
|
for (size_t i = 0; i < data_len; i += 4) {
|
||||||
int w_i = i / 4; // Word index
|
int w_i = i / 4; // Word index
|
||||||
|
@ -17,16 +17,15 @@
|
|||||||
#include "hal/wdt_hal.h"
|
#include "hal/wdt_hal.h"
|
||||||
|
|
||||||
// Need to remove check and merge accordingly for ESP32C5 once key manager support added in IDF-8621
|
// Need to remove check and merge accordingly for ESP32C5 once key manager support added in IDF-8621
|
||||||
#if SOC_KEY_MANAGER_SUPPORTED || CONFIG_IDF_TARGET_ESP32C5
|
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
|
||||||
#if CONFIG_IDF_TARGET_ESP32C5
|
#if CONFIG_IDF_TARGET_ESP32C5
|
||||||
#include "soc/keymng_reg.h"
|
#include "soc/keymng_reg.h"
|
||||||
#include "hal/key_mgr_types.h"
|
|
||||||
#include "soc/pcr_reg.h"
|
#include "soc/pcr_reg.h"
|
||||||
#else
|
#else /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||||
#include "hal/key_mgr_hal.h"
|
#include "hal/key_mgr_ll.h"
|
||||||
#include "hal/mspi_timing_tuning_ll.h"
|
#include "hal/mspi_timing_tuning_ll.h"
|
||||||
#endif /* CONFIG_IDF_TARGET_ESP32C5 */
|
#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
|
||||||
#endif
|
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||||
|
|
||||||
#ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
|
#ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
|
||||||
#include "soc/sensitive_reg.h"
|
#include "soc/sensitive_reg.h"
|
||||||
@ -223,17 +222,25 @@ static esp_err_t check_and_generate_encryption_keys(void)
|
|||||||
ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
|
ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
|
||||||
}
|
}
|
||||||
// Need to remove check for ESP32C5 and merge accordingly once key manager support added in IDF-8621
|
// Need to remove check for ESP32C5 and merge accordingly once key manager support added in IDF-8621
|
||||||
#if SOC_KEY_MANAGER_SUPPORTED || CONFIG_IDF_TARGET_ESP32C5
|
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
|
||||||
#if CONFIG_IDF_TARGET_ESP32C5
|
#if CONFIG_IDF_TARGET_ESP32C5
|
||||||
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
|
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
|
||||||
REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
||||||
REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
||||||
#else
|
#else /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||||
|
// Enable and reset key manager
|
||||||
|
// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
|
||||||
|
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
|
||||||
|
key_mgr_ll_enable_bus_clock(true);
|
||||||
|
key_mgr_ll_enable_peripheral_clock(true);
|
||||||
|
key_mgr_ll_reset_register();
|
||||||
|
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
|
||||||
|
};
|
||||||
// Force Key Manager to use eFuse key for XTS-AES operation
|
// Force Key Manager to use eFuse key for XTS-AES operation
|
||||||
key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||||
_mspi_timing_ll_reset_mspi();
|
_mspi_timing_ll_reset_mspi();
|
||||||
#endif /* CONFIG_IDF_TARGET_ESP32C5 */
|
#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
|
||||||
#endif
|
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||||
|
|
||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
@ -428,7 +435,7 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit
|
|||||||
&partition->pos,
|
&partition->pos,
|
||||||
&image_data);
|
&image_data);
|
||||||
should_encrypt = (err == ESP_OK);
|
should_encrypt = (err == ESP_OK);
|
||||||
#ifdef SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
|
#ifdef CONFIG_SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
|
||||||
if (should_encrypt) {
|
if (should_encrypt) {
|
||||||
// Encrypt only the app image instead of encrypting the whole partition
|
// Encrypt only the app image instead of encrypting the whole partition
|
||||||
size = image_data.image_len;
|
size = image_data.image_len;
|
||||||
|
@ -23,6 +23,8 @@
|
|||||||
#include "esp32p4/rom/secure_boot.h"
|
#include "esp32p4/rom/secure_boot.h"
|
||||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||||
#include "esp32c5/rom/secure_boot.h"
|
#include "esp32c5/rom/secure_boot.h"
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32C61
|
||||||
|
#include "esp32c61/rom/secure_boot.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
esp_err_t verify_ecdsa_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, const ets_secure_boot_sig_block_t *trusted_block);
|
esp_err_t verify_ecdsa_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, const ets_secure_boot_sig_block_t *trusted_block);
|
||||||
|
@ -634,6 +634,7 @@ if(CONFIG_BT_ENABLED)
|
|||||||
host/nimble/nimble/nimble/host/services/tps/include
|
host/nimble/nimble/nimble/host/services/tps/include
|
||||||
host/nimble/nimble/nimble/host/services/hid/include
|
host/nimble/nimble/nimble/host/services/hid/include
|
||||||
host/nimble/nimble/nimble/host/services/sps/include
|
host/nimble/nimble/nimble/host/services/sps/include
|
||||||
|
host/nimble/nimble/nimble/host/services/cte/include
|
||||||
host/nimble/nimble/nimble/host/util/include
|
host/nimble/nimble/nimble/host/util/include
|
||||||
host/nimble/nimble/nimble/host/store/ram/include
|
host/nimble/nimble/nimble/host/store/ram/include
|
||||||
host/nimble/nimble/nimble/host/store/config/include
|
host/nimble/nimble/nimble/host/store/config/include
|
||||||
@ -656,6 +657,7 @@ if(CONFIG_BT_ENABLED)
|
|||||||
"host/nimble/nimble/nimble/host/services/cts/src/ble_svc_cts.c"
|
"host/nimble/nimble/nimble/host/services/cts/src/ble_svc_cts.c"
|
||||||
"host/nimble/nimble/nimble/host/services/hid/src/ble_svc_hid.c"
|
"host/nimble/nimble/nimble/host/services/hid/src/ble_svc_hid.c"
|
||||||
"host/nimble/nimble/nimble/host/services/sps/src/ble_svc_sps.c"
|
"host/nimble/nimble/nimble/host/services/sps/src/ble_svc_sps.c"
|
||||||
|
"host/nimble/nimble/nimble/host/services/cte/src/ble_svc_cte.c"
|
||||||
"host/nimble/nimble/nimble/host/src/ble_hs_conn.c"
|
"host/nimble/nimble/nimble/host/src/ble_hs_conn.c"
|
||||||
"host/nimble/nimble/nimble/host/src/ble_store_util.c"
|
"host/nimble/nimble/nimble/host/src/ble_store_util.c"
|
||||||
"host/nimble/nimble/nimble/host/src/ble_sm.c"
|
"host/nimble/nimble/nimble/host/src/ble_sm.c"
|
||||||
@ -874,7 +876,7 @@ if(CONFIG_BLE_MESH)
|
|||||||
add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32h2/libble_mesh.a")
|
add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32h2/libble_mesh.a")
|
||||||
target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
|
target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
|
||||||
elseif(CONFIG_IDF_TARGET_ESP32C5)
|
elseif(CONFIG_IDF_TARGET_ESP32C5)
|
||||||
add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32C5/libble_mesh.a")
|
add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32c5/libble_mesh.a")
|
||||||
target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
|
target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
|
||||||
endif()
|
endif()
|
||||||
endif()
|
endif()
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -124,7 +124,31 @@ static size_t write_value(uint16_t conn_handle, uint16_t attr_handle,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
btc_blufi_recv_handler(&ctxt->om->om_data[0], ctxt->om->om_len);
|
/* Data may come in linked om. So retrieve all data */
|
||||||
|
if (SLIST_NEXT(ctxt->om, om_next) != NULL) {
|
||||||
|
uint8_t *fw_buf = (uint8_t *)malloc(517 * sizeof(uint8_t));
|
||||||
|
memset(fw_buf, 0x0, 517);
|
||||||
|
|
||||||
|
memcpy(fw_buf, &ctxt->om->om_data[0], ctxt->om->om_len);
|
||||||
|
struct os_mbuf *last;
|
||||||
|
last = ctxt->om;
|
||||||
|
uint32_t offset = ctxt->om->om_len;
|
||||||
|
|
||||||
|
while (SLIST_NEXT(last, om_next) != NULL) {
|
||||||
|
struct os_mbuf *temp = SLIST_NEXT(last, om_next);
|
||||||
|
memcpy(fw_buf + offset , &temp->om_data[0], temp->om_len);
|
||||||
|
offset += temp->om_len;
|
||||||
|
last = SLIST_NEXT(last, om_next);
|
||||||
|
temp = NULL;
|
||||||
|
}
|
||||||
|
btc_blufi_recv_handler(fw_buf, offset);
|
||||||
|
|
||||||
|
free(fw_buf);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
btc_blufi_recv_handler(&ctxt->om->om_data[0], ctxt->om->om_len);
|
||||||
|
}
|
||||||
|
|
||||||
rc = ble_hs_mbuf_to_flat(ctxt->om, value->buf->om_data,
|
rc = ble_hs_mbuf_to_flat(ctxt->om, value->buf->om_data,
|
||||||
value->buf->om_len, &len);
|
value->buf->om_len, &len);
|
||||||
if (rc != 0) {
|
if (rc != 0) {
|
||||||
|
@ -46,6 +46,7 @@
|
|||||||
#define OSI_INITIAL_TRACE_LEVEL UC_BT_LOG_OSI_TRACE_LEVEL
|
#define OSI_INITIAL_TRACE_LEVEL UC_BT_LOG_OSI_TRACE_LEVEL
|
||||||
#define BLUFI_INITIAL_TRACE_LEVEL UC_BT_LOG_BLUFI_TRACE_LEVEL
|
#define BLUFI_INITIAL_TRACE_LEVEL UC_BT_LOG_BLUFI_TRACE_LEVEL
|
||||||
|
|
||||||
|
// MEMORY
|
||||||
#if UC_BT_BLE_DYNAMIC_ENV_MEMORY
|
#if UC_BT_BLE_DYNAMIC_ENV_MEMORY
|
||||||
#define BT_BLE_DYNAMIC_ENV_MEMORY TRUE
|
#define BT_BLE_DYNAMIC_ENV_MEMORY TRUE
|
||||||
#define BTC_DYNAMIC_MEMORY TRUE
|
#define BTC_DYNAMIC_MEMORY TRUE
|
||||||
@ -64,6 +65,19 @@
|
|||||||
#define BT_BLE_DYNAMIC_ENV_MEMORY FALSE
|
#define BT_BLE_DYNAMIC_ENV_MEMORY FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if UC_HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
||||||
|
#define HEAP_ALLOCATION_FROM_SPIRAM_FIRST TRUE
|
||||||
|
#else
|
||||||
|
#define HEAP_ALLOCATION_FROM_SPIRAM_FIRST FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if UC_BT_ABORT_WHEN_ALLOCATION_FAILS
|
||||||
|
#define HEAP_ALLOCATION_FAILS_ABORT TRUE
|
||||||
|
#else
|
||||||
|
#define HEAP_ALLOCATION_FAILS_ABORT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// HCI LOG
|
||||||
#if UC_BT_HCI_LOG_DEBUG_EN
|
#if UC_BT_HCI_LOG_DEBUG_EN
|
||||||
#define BT_HCI_LOG_INCLUDED UC_BT_HCI_LOG_DEBUG_EN
|
#define BT_HCI_LOG_INCLUDED UC_BT_HCI_LOG_DEBUG_EN
|
||||||
#else
|
#else
|
||||||
|
@ -100,13 +100,26 @@
|
|||||||
#define UC_BT_BLUFI_ENABLE FALSE
|
#define UC_BT_BLUFI_ENABLE FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
//MEMORY DEBUG
|
//MEMORY
|
||||||
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
|
#ifdef CONFIG_BT_BLUEDROID_MEM_DEBUG
|
||||||
#define UC_BT_BLUEDROID_MEM_DEBUG TRUE
|
#define UC_BT_BLUEDROID_MEM_DEBUG TRUE
|
||||||
#else
|
#else
|
||||||
#define UC_BT_BLUEDROID_MEM_DEBUG FALSE
|
#define UC_BT_BLUEDROID_MEM_DEBUG FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST
|
||||||
|
#define UC_HEAP_ALLOCATION_FROM_SPIRAM_FIRST CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST
|
||||||
|
#else
|
||||||
|
#define UC_HEAP_ALLOCATION_FROM_SPIRAM_FIRST FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_BT_ABORT_WHEN_ALLOCATION_FAILS
|
||||||
|
#define UC_BT_ABORT_WHEN_ALLOCATION_FAILS CONFIG_BT_ABORT_WHEN_ALLOCATION_FAILS
|
||||||
|
#else
|
||||||
|
#define UC_BT_ABORT_WHEN_ALLOCATION_FAILS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//HCI LOG
|
||||||
#ifdef CONFIG_BT_HCI_LOG_DEBUG_EN
|
#ifdef CONFIG_BT_HCI_LOG_DEBUG_EN
|
||||||
#define UC_BT_HCI_LOG_DEBUG_EN TRUE
|
#define UC_BT_HCI_LOG_DEBUG_EN TRUE
|
||||||
#else
|
#else
|
||||||
|
@ -213,48 +213,33 @@ char *osi_strdup(const char *str)
|
|||||||
|
|
||||||
void *osi_malloc_func(size_t size)
|
void *osi_malloc_func(size_t size)
|
||||||
{
|
{
|
||||||
#if HEAP_MEMORY_DEBUG
|
void *p = osi_malloc_base(size);
|
||||||
void *p;
|
|
||||||
#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
if (size != 0 && p == NULL) {
|
||||||
p = heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
|
OSI_TRACE_ERROR("malloc failed (caller=%p size=%u)\n", __builtin_return_address(0), size);
|
||||||
#else
|
#if HEAP_ALLOCATION_FAILS_ABORT
|
||||||
p = malloc(size);
|
assert(0);
|
||||||
#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
|
#endif
|
||||||
osi_mem_dbg_record(p, size, __func__, __LINE__);
|
}
|
||||||
|
|
||||||
return p;
|
return p;
|
||||||
#else
|
|
||||||
#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
|
||||||
return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
|
|
||||||
#else
|
|
||||||
return malloc(size);
|
|
||||||
#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
|
|
||||||
#endif /* #if HEAP_MEMORY_DEBUG */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void *osi_calloc_func(size_t size)
|
void *osi_calloc_func(size_t size)
|
||||||
{
|
{
|
||||||
#if HEAP_MEMORY_DEBUG
|
void *p = osi_calloc_base(size);
|
||||||
void *p;
|
|
||||||
#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
if (size != 0 && p == NULL) {
|
||||||
p = heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
|
OSI_TRACE_ERROR("calloc failed (caller=%p size=%u)\n", __builtin_return_address(0), size);
|
||||||
#else
|
#if HEAP_ALLOCATION_FAILS_ABORT
|
||||||
p = calloc(1, size);
|
assert(0);
|
||||||
#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
|
#endif
|
||||||
osi_mem_dbg_record(p, size, __func__, __LINE__);
|
}
|
||||||
|
|
||||||
return p;
|
return p;
|
||||||
#else
|
|
||||||
#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
|
||||||
return heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);
|
|
||||||
#else
|
|
||||||
return calloc(1, size);
|
|
||||||
#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
|
|
||||||
#endif /* #if HEAP_MEMORY_DEBUG */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void osi_free_func(void *ptr)
|
void osi_free_func(void *ptr)
|
||||||
{
|
{
|
||||||
#if HEAP_MEMORY_DEBUG
|
|
||||||
osi_mem_dbg_clean(ptr, __func__, __LINE__);
|
|
||||||
#endif
|
|
||||||
free(ptr);
|
free(ptr);
|
||||||
}
|
}
|
||||||
|
@ -122,13 +122,18 @@ do { \
|
|||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
|
// Memory alloc function without print and assertion
|
||||||
#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
|
||||||
#define osi_malloc(size) heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
|
#define osi_malloc_base(size) heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
|
||||||
#define osi_calloc(size) heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
|
#define osi_calloc_base(size) heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
|
||||||
#else
|
#else
|
||||||
#define osi_malloc(size) malloc((size))
|
#define osi_malloc_base(size) malloc((size))
|
||||||
#define osi_calloc(size) calloc(1, (size))
|
#define osi_calloc_base(size) calloc(1, (size))
|
||||||
#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
|
#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
|
||||||
|
|
||||||
|
// Memory alloc function with print and assertion when fails
|
||||||
|
#define osi_malloc(size) osi_malloc_func((size))
|
||||||
|
#define osi_calloc(size) osi_calloc_func((size))
|
||||||
#define osi_free(p) free((p))
|
#define osi_free(p) free((p))
|
||||||
|
|
||||||
#endif /* HEAP_MEMORY_DEBUG */
|
#endif /* HEAP_MEMORY_DEBUG */
|
||||||
|
@ -271,10 +271,10 @@ _err:
|
|||||||
}
|
}
|
||||||
|
|
||||||
for (int i = 0; i < thread->work_queue_num; i++) {
|
for (int i = 0; i < thread->work_queue_num; i++) {
|
||||||
if (thread->work_queues[i]) {
|
if (thread->work_queues && thread->work_queues[i]) {
|
||||||
osi_work_queue_delete(thread->work_queues[i]);
|
osi_work_queue_delete(thread->work_queues[i]);
|
||||||
|
thread->work_queues[i] = NULL;
|
||||||
}
|
}
|
||||||
thread->work_queues[i] = NULL;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (thread->work_queues) {
|
if (thread->work_queues) {
|
||||||
|
@ -96,6 +96,7 @@ do{\
|
|||||||
#define OSI_VERSION 0x00010005
|
#define OSI_VERSION 0x00010005
|
||||||
#define OSI_MAGIC_VALUE 0xFADEBEAD
|
#define OSI_MAGIC_VALUE 0xFADEBEAD
|
||||||
|
|
||||||
|
#define BLE_CONTROLLER_MALLOC_CAPS (MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL)
|
||||||
/* Types definition
|
/* Types definition
|
||||||
************************************************************************
|
************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -868,7 +869,21 @@ static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no)
|
|||||||
|
|
||||||
static void *malloc_internal_wrapper(size_t size)
|
static void *malloc_internal_wrapper(size_t size)
|
||||||
{
|
{
|
||||||
return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
|
return heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||||
|
}
|
||||||
|
|
||||||
|
void *malloc_ble_controller_mem(size_t size)
|
||||||
|
{
|
||||||
|
void *p = heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||||
|
if(p == NULL) {
|
||||||
|
ESP_LOGE(BTDM_LOG_TAG, "Malloc failed");
|
||||||
|
}
|
||||||
|
return p;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t get_ble_controller_free_heap_size(void)
|
||||||
|
{
|
||||||
|
return heap_caps_get_free_size(BLE_CONTROLLER_MALLOC_CAPS);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int32_t IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
static int32_t IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
||||||
@ -1432,6 +1447,14 @@ esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
|
|||||||
.name = "BT Controller Data"
|
.name = "BT Controller Data"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Free data and BSS section for Bluetooth controller ROM code.
|
||||||
|
* Note that rom mem release must be performed before section _bt_data_start to _bt_data_end is released,
|
||||||
|
* otherwise `btdm_dram_available_region` will no longer be available when performing rom mem release and
|
||||||
|
* thus causing heap corruption.
|
||||||
|
*/
|
||||||
|
ret = esp_bt_controller_rom_mem_release(mode);
|
||||||
|
|
||||||
if (mode == ESP_BT_MODE_BTDM) {
|
if (mode == ESP_BT_MODE_BTDM) {
|
||||||
/* Start by freeing Bluetooth BSS section */
|
/* Start by freeing Bluetooth BSS section */
|
||||||
if (ret == ESP_OK) {
|
if (ret == ESP_OK) {
|
||||||
@ -1444,11 +1467,6 @@ esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* free data and BSS section for Bluetooth controller ROM code */
|
|
||||||
if (ret == ESP_OK) {
|
|
||||||
ret = esp_bt_controller_rom_mem_release(mode);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -294,6 +294,24 @@ config BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
|||||||
help
|
help
|
||||||
Only operate in dump mode
|
Only operate in dump mode
|
||||||
|
|
||||||
|
config BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
bool "Store ble controller logs to flash(Experimental)"
|
||||||
|
depends on !BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Store ble controller logs to flash memory.
|
||||||
|
|
||||||
|
config BT_LE_CONTROLLER_LOG_PARTITION_SIZE
|
||||||
|
int "size of ble controller log partition(Multiples of 4K)"
|
||||||
|
depends on BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
default 65536
|
||||||
|
help
|
||||||
|
The size of ble controller log partition shall be a multiples of 4K.
|
||||||
|
The name of log partition shall be "bt_ctrl_log".
|
||||||
|
The partition type shall be ESP_PARTITION_TYPE_DATA.
|
||||||
|
The partition sub_type shall be ESP_PARTITION_SUBTYPE_ANY.
|
||||||
|
|
||||||
config BT_LE_LOG_CTRL_BUF1_SIZE
|
config BT_LE_LOG_CTRL_BUF1_SIZE
|
||||||
int "size of the first BLE controller LOG buffer"
|
int "size of the first BLE controller LOG buffer"
|
||||||
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
@ -49,6 +49,7 @@
|
|||||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
#include "esp_private/sleep_modem.h"
|
#include "esp_private/sleep_modem.h"
|
||||||
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
|
#include "esp_private/esp_modem_clock.h"
|
||||||
|
|
||||||
#include "freertos/FreeRTOS.h"
|
#include "freertos/FreeRTOS.h"
|
||||||
#include "freertos/task.h"
|
#include "freertos/task.h"
|
||||||
@ -75,11 +76,6 @@
|
|||||||
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
|
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
|
||||||
|
|
||||||
#define BT_ASSERT_PRINT ets_printf
|
#define BT_ASSERT_PRINT ets_printf
|
||||||
typedef enum ble_rtc_slow_clk_src {
|
|
||||||
BT_SLOW_CLK_SRC_MAIN_XTAL,
|
|
||||||
BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0,
|
|
||||||
} ble_rtc_slow_clk_src_t;
|
|
||||||
|
|
||||||
/* Types definition
|
/* Types definition
|
||||||
************************************************************************
|
************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -192,6 +188,9 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
|
|||||||
const uint8_t *our_priv_key, uint8_t *out_dhkey);
|
const uint8_t *our_priv_key, uint8_t *out_dhkey);
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
|
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
|
||||||
|
#endif // #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
/* Local variable definition
|
/* Local variable definition
|
||||||
***************************************************************************
|
***************************************************************************
|
||||||
@ -200,6 +199,237 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
|
|||||||
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
||||||
|
enum log_out_mode {
|
||||||
|
LOG_DUMP_MEMORY,
|
||||||
|
LOG_ASYNC_OUT,
|
||||||
|
LOG_STORAGE_TO_FLASH,
|
||||||
|
};
|
||||||
|
|
||||||
|
bool log_is_inited = false;
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
uint8_t log_output_mode = LOG_DUMP_MEMORY;
|
||||||
|
#else
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
uint8_t log_output_mode = LOG_STORAGE_TO_FLASH;
|
||||||
|
#else
|
||||||
|
uint8_t log_output_mode = LOG_ASYNC_OUT;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
|
||||||
|
void esp_bt_log_output_mode_set(uint8_t output_mode)
|
||||||
|
{
|
||||||
|
log_output_mode = output_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t esp_bt_log_output_mode_get(void)
|
||||||
|
{
|
||||||
|
return log_output_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
|
||||||
|
{
|
||||||
|
esp_err_t ret = ESP_OK;
|
||||||
|
interface_func_t bt_controller_log_interface;
|
||||||
|
bt_controller_log_interface = esp_bt_controller_log_interface;
|
||||||
|
bool task_create;
|
||||||
|
uint8_t buffers = 0;
|
||||||
|
|
||||||
|
if (log_is_inited) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
||||||
|
buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
||||||
|
buffers |= ESP_BLE_LOG_BUF_HCI;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
||||||
|
|
||||||
|
switch (log_output_mode) {
|
||||||
|
case LOG_DUMP_MEMORY:
|
||||||
|
task_create = false;
|
||||||
|
break;
|
||||||
|
case LOG_ASYNC_OUT:
|
||||||
|
case LOG_STORAGE_TO_FLASH:
|
||||||
|
task_create = true;
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
|
esp_bt_ctrl_log_partition_get_and_erase_first_block();
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
assert(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
|
||||||
|
if (ret == ESP_OK) {
|
||||||
|
log_is_inited = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_ontroller_log_deinit(void)
|
||||||
|
{
|
||||||
|
ble_log_deinit_async();
|
||||||
|
log_is_inited = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
#include "esp_partition.h"
|
||||||
|
#include "hal/wdt_hal.h"
|
||||||
|
|
||||||
|
#define MAX_STORAGE_SIZE (CONFIG_BT_LE_CONTROLLER_LOG_PARTITION_SIZE)
|
||||||
|
#define BLOCK_SIZE (4096)
|
||||||
|
#define THRESHOLD (3072)
|
||||||
|
#define PARTITION_NAME "bt_ctrl_log"
|
||||||
|
|
||||||
|
static const esp_partition_t *log_partition;
|
||||||
|
static uint32_t write_index = 0;
|
||||||
|
static uint32_t next_erase_index = BLOCK_SIZE;
|
||||||
|
static bool block_erased = false;
|
||||||
|
static bool stop_write = false;
|
||||||
|
static bool is_filled = false;
|
||||||
|
|
||||||
|
static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void)
|
||||||
|
{
|
||||||
|
log_partition = NULL;
|
||||||
|
assert(MAX_STORAGE_SIZE % BLOCK_SIZE == 0);
|
||||||
|
// Find the partition map in the partition table
|
||||||
|
log_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, PARTITION_NAME);
|
||||||
|
assert(log_partition != NULL);
|
||||||
|
// Prepare data to be read later using the mapped address
|
||||||
|
ESP_ERROR_CHECK(esp_partition_erase_range(log_partition, 0, BLOCK_SIZE));
|
||||||
|
write_index = 0;
|
||||||
|
next_erase_index = BLOCK_SIZE;
|
||||||
|
block_erased = false;
|
||||||
|
is_filled = false;
|
||||||
|
stop_write = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end)
|
||||||
|
{
|
||||||
|
if (len > MAX_STORAGE_SIZE) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (stop_write) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert(log_partition != NULL);
|
||||||
|
if (((write_index) % BLOCK_SIZE) >= THRESHOLD && !block_erased) {
|
||||||
|
// esp_rom_printf("Ers nxt: %d,%d\n", next_erase_index, write_index);
|
||||||
|
esp_partition_erase_range(log_partition, next_erase_index, BLOCK_SIZE);
|
||||||
|
next_erase_index = (next_erase_index + BLOCK_SIZE) % MAX_STORAGE_SIZE;
|
||||||
|
block_erased = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (((write_index + len) / BLOCK_SIZE) > (write_index / BLOCK_SIZE)) {
|
||||||
|
block_erased = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (write_index + len <= MAX_STORAGE_SIZE) {
|
||||||
|
esp_partition_write(log_partition, write_index, addr, len);
|
||||||
|
write_index = (write_index + len) % MAX_STORAGE_SIZE;
|
||||||
|
} else {
|
||||||
|
uint32_t first_part_len = MAX_STORAGE_SIZE - write_index;
|
||||||
|
esp_partition_write(log_partition, write_index, addr, first_part_len);
|
||||||
|
esp_partition_write(log_partition, 0, addr + first_part_len, len - first_part_len);
|
||||||
|
write_index = len - first_part_len;
|
||||||
|
is_filled = true;
|
||||||
|
// esp_rom_printf("old idx: %d,%d\n",next_erase_index, write_index);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_read_ctrl_log_from_flash(bool output)
|
||||||
|
{
|
||||||
|
esp_partition_mmap_handle_t mmap_handle;
|
||||||
|
uint32_t read_index;
|
||||||
|
const void *mapped_ptr;
|
||||||
|
const uint8_t *buffer;
|
||||||
|
uint32_t print_len;
|
||||||
|
uint32_t max_print_len;
|
||||||
|
esp_err_t err;
|
||||||
|
|
||||||
|
print_len = 0;
|
||||||
|
max_print_len = 4096;
|
||||||
|
err = esp_partition_mmap(log_partition, 0, MAX_STORAGE_SIZE, ESP_PARTITION_MMAP_DATA, &mapped_ptr, &mmap_handle);
|
||||||
|
if (err != ESP_OK) {
|
||||||
|
ESP_LOGE("FLASH", "Mmap failed: %s", esp_err_to_name(err));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
ble_log_async_output_dump_all(true);
|
||||||
|
stop_write = true;
|
||||||
|
esp_bt_ontroller_log_deinit();
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
|
|
||||||
|
buffer = (const uint8_t *)mapped_ptr;
|
||||||
|
if (is_filled) {
|
||||||
|
read_index = next_erase_index;
|
||||||
|
} else {
|
||||||
|
read_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_rom_printf("\r\nREAD_CHECK:%ld,%ld,%d\r\n",read_index, write_index, is_filled);
|
||||||
|
esp_rom_printf("\r\n[DUMP_START:");
|
||||||
|
while (read_index != write_index) {
|
||||||
|
esp_rom_printf("%02x ", buffer[read_index]);
|
||||||
|
if (print_len > max_print_len) {
|
||||||
|
vTaskDelay(2);
|
||||||
|
print_len = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
print_len++;
|
||||||
|
read_index = (read_index + 1) % MAX_STORAGE_SIZE;
|
||||||
|
}
|
||||||
|
esp_rom_printf(":DUMP_END]\r\n");
|
||||||
|
esp_partition_munmap(mmap_handle);
|
||||||
|
err = esp_bt_controller_log_init(log_output_mode);
|
||||||
|
assert(err == ESP_OK);
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
|
||||||
|
{
|
||||||
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
esp_bt_controller_log_storage(len, addr, end);
|
||||||
|
#endif //CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
} else {
|
||||||
|
for (int i = 0; i < len; i++) {
|
||||||
|
esp_rom_printf("%02x ", addr[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (end) {
|
||||||
|
esp_rom_printf("\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_ble_controller_log_dump_all(bool output)
|
||||||
|
{
|
||||||
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
esp_bt_read_ctrl_log_from_flash(output);
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
} else {
|
||||||
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
BT_ASSERT_PRINT("\r\n[DUMP_START:");
|
||||||
|
ble_log_async_output_dump_all(output);
|
||||||
|
BT_ASSERT_PRINT(":DUMP_END]\r\n");
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
|
}
|
||||||
|
}
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
/* This variable tells if BLE is running */
|
/* This variable tells if BLE is running */
|
||||||
@ -208,6 +438,7 @@ static bool s_ble_active = false;
|
|||||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||||
#endif // CONFIG_PM_ENABLE
|
#endif // CONFIG_PM_ENABLE
|
||||||
|
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||||
|
|
||||||
#define BLE_RTC_DELAY_US (1800)
|
#define BLE_RTC_DELAY_US (1800)
|
||||||
|
|
||||||
@ -322,6 +553,20 @@ void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
|
|||||||
}
|
}
|
||||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||||
|
|
||||||
|
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||||
|
{
|
||||||
|
return s_bt_lpclk_src;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||||
|
{
|
||||||
|
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
s_bt_lpclk_src = clk_src;
|
||||||
|
}
|
||||||
|
|
||||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||||
{
|
{
|
||||||
if (!s_ble_active) {
|
if (!s_ble_active) {
|
||||||
@ -348,7 +593,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
|
|||||||
s_ble_active = true;
|
s_ble_active = true;
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
|
esp_err_t controller_sleep_init(modem_clock_lpclk_src_t slow_clk_src)
|
||||||
{
|
{
|
||||||
esp_err_t rc = 0;
|
esp_err_t rc = 0;
|
||||||
#ifdef CONFIG_BT_LE_SLEEP_ENABLE
|
#ifdef CONFIG_BT_LE_SLEEP_ENABLE
|
||||||
@ -356,7 +601,7 @@ esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
|
|||||||
r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
|
r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
|
||||||
|
|
||||||
#ifdef CONFIG_PM_ENABLE
|
#ifdef CONFIG_PM_ENABLE
|
||||||
if (slow_clk_src == BT_SLOW_CLK_SRC_MAIN_XTAL) {
|
if (slow_clk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||||
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
|
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
|
||||||
} else {
|
} else {
|
||||||
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
|
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
|
||||||
@ -411,11 +656,11 @@ void controller_sleep_deinit(void)
|
|||||||
#endif //CONFIG_PM_ENABLE
|
#endif //CONFIG_PM_ENABLE
|
||||||
}
|
}
|
||||||
|
|
||||||
static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
|
static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)
|
||||||
{
|
{
|
||||||
/* Select slow clock source for BT momdule */
|
/* Select slow clock source for BT momdule */
|
||||||
switch (slow_clk_src) {
|
switch (slow_clk_src) {
|
||||||
case BT_SLOW_CLK_SRC_MAIN_XTAL:
|
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
|
||||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
|
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
|
||||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
|
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
|
||||||
@ -427,7 +672,7 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
|
|||||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
|
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
|
||||||
#endif // CONFIG_XTAL_FREQ_26
|
#endif // CONFIG_XTAL_FREQ_26
|
||||||
break;
|
break;
|
||||||
case BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0:
|
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
|
||||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
|
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
|
||||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
|
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
|
||||||
@ -444,40 +689,39 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
|
|||||||
SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
|
SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
|
||||||
}
|
}
|
||||||
|
|
||||||
static ble_rtc_slow_clk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
static modem_clock_lpclk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||||
{
|
{
|
||||||
ble_rtc_slow_clk_src_t slow_clk_src;
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||||
|
|
||||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||||
#ifdef CONFIG_XTAL_FREQ_26
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
cfg->rtc_freq = 40000;
|
|
||||||
#else
|
#else
|
||||||
cfg->rtc_freq = 32000;
|
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
|
||||||
#endif // CONFIG_XTAL_FREQ_26
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||||
slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
|
} else {
|
||||||
#else
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||||
cfg->rtc_freq = 32768;
|
cfg->rtc_freq = 32768;
|
||||||
slow_clk_src = BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0;
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||||
} else {
|
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
|
||||||
#ifdef CONFIG_XTAL_FREQ_26
|
#ifdef CONFIG_XTAL_FREQ_26
|
||||||
cfg->rtc_freq = 40000;
|
cfg->rtc_freq = 40000;
|
||||||
#else
|
#else
|
||||||
cfg->rtc_freq = 32000;
|
cfg->rtc_freq = 32000;
|
||||||
#endif // CONFIG_XTAL_FREQ_26
|
#endif // CONFIG_XTAL_FREQ_26
|
||||||
slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
|
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||||
esp_bt_rtc_slow_clk_select(slow_clk_src);
|
return s_bt_lpclk_src;
|
||||||
return slow_clk_src;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||||
{
|
{
|
||||||
esp_err_t ret = ESP_OK;
|
esp_err_t ret = ESP_OK;
|
||||||
ble_npl_count_info_t npl_info;
|
ble_npl_count_info_t npl_info;
|
||||||
ble_rtc_slow_clk_src_t rtc_clk_src;
|
modem_clock_lpclk_src_t rtc_clk_src;
|
||||||
uint8_t hci_transport_mode;
|
uint8_t hci_transport_mode;
|
||||||
|
|
||||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||||
@ -566,20 +810,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble rom commit:[%s]", r_ble_controller_get_rom_compile_version());
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble rom commit:[%s]", r_ble_controller_get_rom_compile_version());
|
||||||
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
interface_func_t bt_controller_log_interface;
|
ret = esp_bt_controller_log_init(log_output_mode);
|
||||||
bt_controller_log_interface = esp_bt_controller_log_interface;
|
|
||||||
uint8_t buffers = 0;
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
|
||||||
buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
|
||||||
buffers |= ESP_BLE_LOG_BUF_HCI;
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
|
||||||
ret = ble_log_init_async(bt_controller_log_interface, false, buffers, (uint32_t *)log_bufs_size);
|
|
||||||
#else
|
|
||||||
ret = ble_log_init_async(bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
|
|
||||||
#endif // CONFIG_BT_CONTROLLER_LOG_DUMP
|
|
||||||
if (ret != ESP_OK) {
|
if (ret != ESP_OK) {
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
|
||||||
goto controller_init_err;
|
goto controller_init_err;
|
||||||
@ -595,6 +826,9 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
uint8_t mac[6];
|
uint8_t mac[6];
|
||||||
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
||||||
|
|
||||||
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Bluetooth MAC: %02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||||
|
|
||||||
swap_in_place(mac, 6);
|
swap_in_place(mac, 6);
|
||||||
|
|
||||||
esp_ble_ll_set_public_addr(mac);
|
esp_ble_ll_set_public_addr(mac);
|
||||||
@ -617,7 +851,7 @@ free_controller:
|
|||||||
controller_sleep_deinit();
|
controller_sleep_deinit();
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
controller_init_err:
|
controller_init_err:
|
||||||
ble_log_deinit_async();
|
esp_bt_ontroller_log_deinit();
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
ble_controller_deinit();
|
ble_controller_deinit();
|
||||||
modem_deint:
|
modem_deint:
|
||||||
@ -646,7 +880,7 @@ esp_err_t esp_bt_controller_deinit(void)
|
|||||||
controller_sleep_deinit();
|
controller_sleep_deinit();
|
||||||
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
ble_log_deinit_async();
|
esp_bt_ontroller_log_deinit();
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
ble_controller_deinit();
|
ble_controller_deinit();
|
||||||
|
|
||||||
@ -996,30 +1230,6 @@ uint8_t esp_ble_get_chip_rev_version(void)
|
|||||||
return efuse_ll_get_chip_wafer_version_minor();
|
return efuse_ll_get_chip_wafer_version_minor();
|
||||||
}
|
}
|
||||||
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
|
||||||
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
|
|
||||||
{
|
|
||||||
for (int i = 0; i < len; i++) {
|
|
||||||
esp_rom_printf("%02x ", addr[i]);
|
|
||||||
}
|
|
||||||
if (end) {
|
|
||||||
esp_rom_printf("\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void esp_ble_controller_log_dump_all(bool output)
|
|
||||||
{
|
|
||||||
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
|
||||||
|
|
||||||
portENTER_CRITICAL_SAFE(&spinlock);
|
|
||||||
esp_panic_handler_reconfigure_wdts(5000);
|
|
||||||
BT_ASSERT_PRINT("\r\n[DUMP_START:");
|
|
||||||
ble_log_async_output_dump_all(output);
|
|
||||||
BT_ASSERT_PRINT(":DUMP_END]\r\n");
|
|
||||||
portEXIT_CRITICAL_SAFE(&spinlock);
|
|
||||||
}
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
|
||||||
|
|
||||||
#if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
|
#if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
|
||||||
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
|
#if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
|
||||||
#define BLE_SM_KEY_ERR 0x17
|
#define BLE_SM_KEY_ERR 0x17
|
||||||
|
@ -118,6 +118,9 @@ do{\
|
|||||||
#define OSI_VERSION 0x00010009
|
#define OSI_VERSION 0x00010009
|
||||||
#define OSI_MAGIC_VALUE 0xFADEBEAD
|
#define OSI_MAGIC_VALUE 0xFADEBEAD
|
||||||
|
|
||||||
|
#define BLE_PWR_HDL_INVL 0xFFFF
|
||||||
|
|
||||||
|
#define BLE_CONTROLLER_MALLOC_CAPS (MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA)
|
||||||
/* Types definition
|
/* Types definition
|
||||||
************************************************************************
|
************************************************************************
|
||||||
*/
|
*/
|
||||||
@ -254,8 +257,8 @@ extern bool API_vhci_host_check_send_available(void);
|
|||||||
extern void API_vhci_host_send_packet(uint8_t *data, uint16_t len);
|
extern void API_vhci_host_send_packet(uint8_t *data, uint16_t len);
|
||||||
extern int API_vhci_host_register_callback(const vhci_host_callback_t *callback);
|
extern int API_vhci_host_register_callback(const vhci_host_callback_t *callback);
|
||||||
/* TX power */
|
/* TX power */
|
||||||
extern int ble_txpwr_set(int power_type, int power_level);
|
extern int ble_txpwr_set(int power_type, uint16_t handle, int power_level);
|
||||||
extern int ble_txpwr_get(int power_type);
|
extern int ble_txpwr_get(int power_type, uint16_t handle);
|
||||||
|
|
||||||
extern uint16_t l2c_ble_link_get_tx_buf_num(void);
|
extern uint16_t l2c_ble_link_get_tx_buf_num(void);
|
||||||
extern void coex_pti_v2(void);
|
extern void coex_pti_v2(void);
|
||||||
@ -687,13 +690,27 @@ static bool IRAM_ATTR is_in_isr_wrapper(void)
|
|||||||
|
|
||||||
static void *malloc_internal_wrapper(size_t size)
|
static void *malloc_internal_wrapper(size_t size)
|
||||||
{
|
{
|
||||||
void *p = heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA);
|
void *p = heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||||
if(p == NULL) {
|
if(p == NULL) {
|
||||||
ESP_LOGE(BT_LOG_TAG, "Malloc failed");
|
ESP_LOGE(BT_LOG_TAG, "Malloc failed");
|
||||||
}
|
}
|
||||||
return p;
|
return p;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void *malloc_ble_controller_mem(size_t size)
|
||||||
|
{
|
||||||
|
void *p = heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||||
|
if(p == NULL) {
|
||||||
|
ESP_LOGE(BT_LOG_TAG, "Malloc failed");
|
||||||
|
}
|
||||||
|
return p;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t get_ble_controller_free_heap_size(void)
|
||||||
|
{
|
||||||
|
return heap_caps_get_free_size(BLE_CONTROLLER_MALLOC_CAPS);
|
||||||
|
}
|
||||||
|
|
||||||
static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
||||||
{
|
{
|
||||||
int ret = esp_read_mac(mac, ESP_MAC_BT);
|
int ret = esp_read_mac(mac, ESP_MAC_BT);
|
||||||
@ -1677,16 +1694,89 @@ esp_bt_controller_status_t esp_bt_controller_get_status(void)
|
|||||||
return btdm_controller_status;
|
return btdm_controller_status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int enh_power_type_get(esp_ble_power_type_t power_type)
|
||||||
|
{
|
||||||
|
switch (power_type) {
|
||||||
|
case ESP_BLE_PWR_TYPE_ADV:
|
||||||
|
return ESP_BLE_ENHANCED_PWR_TYPE_ADV;
|
||||||
|
case ESP_BLE_PWR_TYPE_SCAN:
|
||||||
|
return ESP_BLE_ENHANCED_PWR_TYPE_SCAN;
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL0:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL1:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL2:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL3:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL4:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL5:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL6:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL7:
|
||||||
|
case ESP_BLE_PWR_TYPE_CONN_HDL8:
|
||||||
|
return ESP_BLE_ENHANCED_PWR_TYPE_CONN;
|
||||||
|
case ESP_BLE_PWR_TYPE_DEFAULT:
|
||||||
|
return ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return power_type;
|
||||||
|
}
|
||||||
|
|
||||||
/* extra functions */
|
/* extra functions */
|
||||||
esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
|
esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
|
||||||
|
{
|
||||||
|
esp_err_t stat = ESP_FAIL;
|
||||||
|
uint16_t handle = BLE_PWR_HDL_INVL;
|
||||||
|
int enh_pwr_type = enh_power_type_get(power_type);
|
||||||
|
|
||||||
|
if (power_type > ESP_BLE_PWR_TYPE_DEFAULT) {
|
||||||
|
return ESP_ERR_NOT_SUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (enh_pwr_type == ESP_BLE_ENHANCED_PWR_TYPE_CONN) {
|
||||||
|
handle = power_type;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ble_txpwr_set(enh_pwr_type, handle, power_level) == 0) {
|
||||||
|
stat = ESP_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
return stat;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
|
||||||
|
{
|
||||||
|
esp_power_level_t lvl;
|
||||||
|
uint16_t handle = BLE_PWR_HDL_INVL;
|
||||||
|
int enh_pwr_type = enh_power_type_get(power_type);
|
||||||
|
|
||||||
|
if (power_type > ESP_BLE_PWR_TYPE_DEFAULT) {
|
||||||
|
return ESP_PWR_LVL_INVALID;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (enh_pwr_type == ESP_BLE_ENHANCED_PWR_TYPE_CONN) {
|
||||||
|
handle = power_type;
|
||||||
|
}
|
||||||
|
|
||||||
|
lvl = (esp_power_level_t)ble_txpwr_get(power_type, handle);
|
||||||
|
|
||||||
|
return lvl;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle,
|
||||||
|
esp_power_level_t power_level)
|
||||||
{
|
{
|
||||||
esp_err_t stat = ESP_FAIL;
|
esp_err_t stat = ESP_FAIL;
|
||||||
|
|
||||||
switch (power_type) {
|
switch (power_type) {
|
||||||
case ESP_BLE_PWR_TYPE_ADV:
|
case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
|
||||||
case ESP_BLE_PWR_TYPE_SCAN:
|
case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
|
||||||
case ESP_BLE_PWR_TYPE_DEFAULT:
|
case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
|
||||||
if (ble_txpwr_set(power_type, power_level) == 0) {
|
if (ble_txpwr_set(power_type, BLE_PWR_HDL_INVL, power_level) == 0) {
|
||||||
|
stat = ESP_OK;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
|
||||||
|
case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
|
||||||
|
if (ble_txpwr_set(power_type, handle, power_level) == 0) {
|
||||||
stat = ESP_OK;
|
stat = ESP_OK;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
@ -1698,33 +1788,26 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_
|
|||||||
return stat;
|
return stat;
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
|
esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type,
|
||||||
|
uint16_t handle)
|
||||||
{
|
{
|
||||||
esp_power_level_t lvl;
|
int tx_level = 0;
|
||||||
|
|
||||||
switch (power_type) {
|
switch (power_type) {
|
||||||
case ESP_BLE_PWR_TYPE_ADV:
|
case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
|
||||||
case ESP_BLE_PWR_TYPE_SCAN:
|
case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
|
||||||
lvl = (esp_power_level_t)ble_txpwr_get(power_type);
|
case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
|
||||||
|
tx_level = ble_txpwr_get(power_type, BLE_PWR_HDL_INVL);
|
||||||
break;
|
break;
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL0:
|
case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL1:
|
case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL2:
|
tx_level = ble_txpwr_get(power_type, handle);
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL3:
|
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL4:
|
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL5:
|
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL6:
|
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL7:
|
|
||||||
case ESP_BLE_PWR_TYPE_CONN_HDL8:
|
|
||||||
case ESP_BLE_PWR_TYPE_DEFAULT:
|
|
||||||
lvl = (esp_power_level_t)ble_txpwr_get(ESP_BLE_PWR_TYPE_DEFAULT);
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
lvl = ESP_PWR_LVL_INVALID;
|
return ESP_PWR_LVL_INVALID;
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return lvl;
|
return (esp_power_level_t)tx_level;
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t esp_bt_sleep_enable (void)
|
esp_err_t esp_bt_sleep_enable (void)
|
||||||
|
@ -39,11 +39,10 @@
|
|||||||
#include "esp_pm.h"
|
#include "esp_pm.h"
|
||||||
#include "esp_phy_init.h"
|
#include "esp_phy_init.h"
|
||||||
#include "esp_private/periph_ctrl.h"
|
#include "esp_private/periph_ctrl.h"
|
||||||
#include "bt_osi_mem.h"
|
#include "soc/retention_periph_defs.h"
|
||||||
|
|
||||||
#if SOC_PM_RETENTION_HAS_CLOCK_BUG
|
|
||||||
#include "esp_private/sleep_retention.h"
|
#include "esp_private/sleep_retention.h"
|
||||||
#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
|
#include "soc/regdma.h"
|
||||||
|
#include "bt_osi_mem.h"
|
||||||
|
|
||||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
#include "esp_private/sleep_modem.h"
|
#include "esp_private/sleep_modem.h"
|
||||||
@ -52,9 +51,6 @@
|
|||||||
#include "freertos/FreeRTOS.h"
|
#include "freertos/FreeRTOS.h"
|
||||||
#include "freertos/task.h"
|
#include "freertos/task.h"
|
||||||
|
|
||||||
#include "esp_private/periph_ctrl.h"
|
|
||||||
#include "esp_sleep.h"
|
|
||||||
|
|
||||||
#include "hal/efuse_hal.h"
|
#include "hal/efuse_hal.h"
|
||||||
#include "soc/rtc.h"
|
#include "soc/rtc.h"
|
||||||
/* Macro definition
|
/* Macro definition
|
||||||
@ -190,6 +186,7 @@ static bool s_ble_active = false;
|
|||||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||||
#endif // CONFIG_PM_ENABLE
|
#endif // CONFIG_PM_ENABLE
|
||||||
|
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||||
|
|
||||||
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
|
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
|
||||||
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
|
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
|
||||||
@ -333,6 +330,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||||
|
{
|
||||||
|
return s_bt_lpclk_src;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||||
|
{
|
||||||
|
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
s_bt_lpclk_src = clk_src;
|
||||||
|
}
|
||||||
|
|
||||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||||
{
|
{
|
||||||
if (!s_ble_active) {
|
if (!s_ble_active) {
|
||||||
@ -362,25 +373,53 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
|
// TODO: IDF-10765
|
||||||
|
// static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
|
||||||
|
// {
|
||||||
|
// uint8_t size;
|
||||||
|
// int extra = *(int *)arg;
|
||||||
|
// const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
||||||
|
// esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||||
|
// if (err == ESP_OK) {
|
||||||
|
// ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||||
|
// }
|
||||||
|
// return err;
|
||||||
|
// return ESP_OK;
|
||||||
|
// }
|
||||||
|
|
||||||
static esp_err_t sleep_modem_ble_mac_modem_state_init(uint8_t extra)
|
static esp_err_t sleep_modem_ble_mac_modem_state_init(uint8_t extra)
|
||||||
{
|
{
|
||||||
uint8_t size;
|
// TODO: IDF-10765
|
||||||
const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
// int retention_args = extra;
|
||||||
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
// sleep_retention_module_init_param_t init_param = {
|
||||||
if (err == ESP_OK) {
|
// .cbs = { .create = { .handle = sleep_modem_ble_mac_retention_init, .arg = &retention_args } },
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
// .depends = BIT(SLEEP_RETENTION_MODULE_BT_BB)
|
||||||
}
|
// };
|
||||||
return err;
|
// esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_BLE_MAC, &init_param);
|
||||||
|
// if (err == ESP_OK) {
|
||||||
|
// err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||||
|
// }
|
||||||
|
// return err;
|
||||||
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "This func temporary not supported for current target!");
|
||||||
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void sleep_modem_ble_mac_modem_state_deinit(void)
|
static void sleep_modem_ble_mac_modem_state_deinit(void)
|
||||||
{
|
{
|
||||||
sleep_retention_entries_destroy(SLEEP_RETENTION_MODULE_BLE_MAC);
|
// TODO: IDF-10765
|
||||||
|
// esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||||
|
// if (err == ESP_OK) {
|
||||||
|
// err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||||
|
// assert(err == ESP_OK);
|
||||||
|
// }
|
||||||
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "This func temporary not supported for current target!");
|
||||||
}
|
}
|
||||||
|
|
||||||
void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
|
void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
|
||||||
{
|
{
|
||||||
esp_ble_set_wakeup_overhead(overhead);
|
// TODO: IDF-10765
|
||||||
|
// esp_ble_set_wakeup_overhead(overhead);
|
||||||
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "This func temporary not supported for current target!");
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||||
|
|
||||||
@ -534,12 +573,51 @@ void ble_controller_scan_duplicate_config(void)
|
|||||||
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||||
|
{
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||||
|
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
#else
|
||||||
|
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||||
|
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
|
||||||
|
} else {
|
||||||
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
}
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||||
|
#else
|
||||||
|
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||||
|
assert(0);
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||||
|
cfg->rtc_freq = 100000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
|
||||||
|
cfg->rtc_freq = 32768;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
|
||||||
|
cfg->rtc_freq = 30000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
|
||||||
|
cfg->rtc_freq = 32000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||||
|
cfg->rtc_freq = 32000;
|
||||||
|
}
|
||||||
|
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||||
|
}
|
||||||
|
|
||||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||||
{
|
{
|
||||||
uint8_t mac[6];
|
uint8_t mac[6];
|
||||||
esp_err_t ret = ESP_OK;
|
esp_err_t ret = ESP_OK;
|
||||||
ble_npl_count_info_t npl_info;
|
ble_npl_count_info_t npl_info;
|
||||||
uint32_t slow_clk_freq = 0;
|
|
||||||
uint8_t hci_transport_mode;
|
uint8_t hci_transport_mode;
|
||||||
|
|
||||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||||
@ -592,33 +670,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
modem_clock_module_enable(PERIPH_BT_MODULE);
|
modem_clock_module_enable(PERIPH_BT_MODULE);
|
||||||
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
||||||
/* Select slow clock source for BT momdule */
|
/* Select slow clock source for BT momdule */
|
||||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
ble_rtc_clk_init(cfg);
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
|
||||||
slow_clk_freq = 100000;
|
|
||||||
#else
|
|
||||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
|
|
||||||
slow_clk_freq = 30000;
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
|
||||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
|
|
||||||
slow_clk_freq = 32768;
|
|
||||||
} else {
|
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
|
||||||
slow_clk_freq = 100000;
|
|
||||||
}
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
|
|
||||||
slow_clk_freq = 32000;
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
|
|
||||||
slow_clk_freq = 32000;
|
|
||||||
#else
|
|
||||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
|
||||||
assert(0);
|
|
||||||
#endif
|
|
||||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
|
||||||
esp_phy_modem_init();
|
esp_phy_modem_init();
|
||||||
|
|
||||||
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
||||||
@ -664,7 +716,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
||||||
r_esp_ble_change_rtc_freq(slow_clk_freq);
|
|
||||||
|
|
||||||
ble_controller_scan_duplicate_config();
|
ble_controller_scan_duplicate_config();
|
||||||
|
|
||||||
@ -680,6 +731,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
goto free_controller;
|
goto free_controller;
|
||||||
}
|
}
|
||||||
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
||||||
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Bluetooth MAC: %02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||||
swap_in_place(mac, 6);
|
swap_in_place(mac, 6);
|
||||||
r_esp_ble_ll_set_public_addr(mac);
|
r_esp_ble_ll_set_public_addr(mac);
|
||||||
|
|
||||||
|
@ -342,6 +342,24 @@ config BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
|||||||
help
|
help
|
||||||
Only operate in dump mode
|
Only operate in dump mode
|
||||||
|
|
||||||
|
config BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
bool "Store ble controller logs to flash(Experimental)"
|
||||||
|
depends on !BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Store ble controller logs to flash memory.
|
||||||
|
|
||||||
|
config BT_LE_CONTROLLER_LOG_PARTITION_SIZE
|
||||||
|
int "size of ble controller log partition(Multiples of 4K)"
|
||||||
|
depends on BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
default 65536
|
||||||
|
help
|
||||||
|
The size of ble controller log partition shall be a multiples of 4K.
|
||||||
|
The name of log partition shall be "bt_ctrl_log".
|
||||||
|
The partition type shall be ESP_PARTITION_TYPE_DATA.
|
||||||
|
The partition sub_type shall be ESP_PARTITION_SUBTYPE_ANY.
|
||||||
|
|
||||||
config BT_LE_LOG_CTRL_BUF1_SIZE
|
config BT_LE_LOG_CTRL_BUF1_SIZE
|
||||||
int "size of the first BLE controller LOG buffer"
|
int "size of the first BLE controller LOG buffer"
|
||||||
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
@ -134,7 +134,7 @@ extern void r_ble_rtc_wake_up_state_clr(void);
|
|||||||
extern int os_msys_init(void);
|
extern int os_msys_init(void);
|
||||||
extern void os_msys_deinit(void);
|
extern void os_msys_deinit(void);
|
||||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
||||||
extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
|
extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
|
||||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||||
extern void r_esp_ble_change_rtc_freq(uint32_t freq);
|
extern void r_esp_ble_change_rtc_freq(uint32_t freq);
|
||||||
@ -176,6 +176,9 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
|
|||||||
const uint8_t *our_priv_key, uint8_t *out_dhkey);
|
const uint8_t *our_priv_key, uint8_t *out_dhkey);
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
|
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
|
||||||
|
#endif // #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
/* Local variable definition
|
/* Local variable definition
|
||||||
***************************************************************************
|
***************************************************************************
|
||||||
@ -184,6 +187,204 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
|
|||||||
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
||||||
|
enum log_out_mode {
|
||||||
|
LOG_DUMP_MEMORY,
|
||||||
|
LOG_ASYNC_OUT,
|
||||||
|
LOG_STORAGE_TO_FLASH,
|
||||||
|
};
|
||||||
|
|
||||||
|
bool log_is_inited = false;
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
uint8_t log_output_mode = LOG_DUMP_MEMORY;
|
||||||
|
#else
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
uint8_t log_output_mode = LOG_STORAGE_TO_FLASH;
|
||||||
|
#else
|
||||||
|
uint8_t log_output_mode = LOG_ASYNC_OUT;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
|
||||||
|
void esp_bt_log_output_mode_set(uint8_t output_mode)
|
||||||
|
{
|
||||||
|
log_output_mode = output_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t esp_bt_log_output_mode_get(void)
|
||||||
|
{
|
||||||
|
return log_output_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
|
||||||
|
{
|
||||||
|
esp_err_t ret = ESP_OK;
|
||||||
|
interface_func_t bt_controller_log_interface;
|
||||||
|
bt_controller_log_interface = esp_bt_controller_log_interface;
|
||||||
|
bool task_create;
|
||||||
|
uint8_t buffers = 0;
|
||||||
|
|
||||||
|
if (log_is_inited) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
||||||
|
buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
||||||
|
buffers |= ESP_BLE_LOG_BUF_HCI;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
||||||
|
|
||||||
|
switch (log_output_mode) {
|
||||||
|
case LOG_DUMP_MEMORY:
|
||||||
|
task_create = false;
|
||||||
|
break;
|
||||||
|
case LOG_ASYNC_OUT:
|
||||||
|
case LOG_STORAGE_TO_FLASH:
|
||||||
|
task_create = true;
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
|
esp_bt_ctrl_log_partition_get_and_erase_first_block();
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
assert(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = r_ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
|
||||||
|
if (ret == ESP_OK) {
|
||||||
|
log_is_inited = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_ontroller_log_deinit(void)
|
||||||
|
{
|
||||||
|
r_ble_log_deinit_async();
|
||||||
|
log_is_inited = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
#include "esp_partition.h"
|
||||||
|
#include "hal/wdt_hal.h"
|
||||||
|
|
||||||
|
#define MAX_STORAGE_SIZE (CONFIG_BT_LE_CONTROLLER_LOG_PARTITION_SIZE)
|
||||||
|
#define BLOCK_SIZE (4096)
|
||||||
|
#define THRESHOLD (3072)
|
||||||
|
#define PARTITION_NAME "bt_ctrl_log"
|
||||||
|
|
||||||
|
static const esp_partition_t *log_partition;
|
||||||
|
static uint32_t write_index = 0;
|
||||||
|
static uint32_t next_erase_index = BLOCK_SIZE;
|
||||||
|
static bool block_erased = false;
|
||||||
|
static bool stop_write = false;
|
||||||
|
static bool is_filled = false;
|
||||||
|
|
||||||
|
static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void)
|
||||||
|
{
|
||||||
|
log_partition = NULL;
|
||||||
|
assert(MAX_STORAGE_SIZE % BLOCK_SIZE == 0);
|
||||||
|
// Find the partition map in the partition table
|
||||||
|
log_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, PARTITION_NAME);
|
||||||
|
assert(log_partition != NULL);
|
||||||
|
// Prepare data to be read later using the mapped address
|
||||||
|
ESP_ERROR_CHECK(esp_partition_erase_range(log_partition, 0, BLOCK_SIZE));
|
||||||
|
write_index = 0;
|
||||||
|
next_erase_index = BLOCK_SIZE;
|
||||||
|
block_erased = false;
|
||||||
|
is_filled = false;
|
||||||
|
stop_write = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end)
|
||||||
|
{
|
||||||
|
if (len > MAX_STORAGE_SIZE) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (stop_write) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (((write_index) % BLOCK_SIZE) >= THRESHOLD && !block_erased) {
|
||||||
|
// esp_rom_printf("Ers nxt: %d,%d\n", next_erase_index, write_index);
|
||||||
|
esp_partition_erase_range(log_partition, next_erase_index, BLOCK_SIZE);
|
||||||
|
next_erase_index = (next_erase_index + BLOCK_SIZE) % MAX_STORAGE_SIZE;
|
||||||
|
block_erased = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (((write_index + len) / BLOCK_SIZE) > (write_index / BLOCK_SIZE)) {
|
||||||
|
block_erased = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (write_index + len <= MAX_STORAGE_SIZE) {
|
||||||
|
esp_partition_write(log_partition, write_index, addr, len);
|
||||||
|
write_index = (write_index + len) % MAX_STORAGE_SIZE;
|
||||||
|
} else {
|
||||||
|
uint32_t first_part_len = MAX_STORAGE_SIZE - write_index;
|
||||||
|
esp_partition_write(log_partition, write_index, addr, first_part_len);
|
||||||
|
esp_partition_write(log_partition, 0, addr + first_part_len, len - first_part_len);
|
||||||
|
write_index = len - first_part_len;
|
||||||
|
is_filled = true;
|
||||||
|
// esp_rom_printf("old idx: %d,%d\n",next_erase_index, write_index);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_read_ctrl_log_from_flash(bool output)
|
||||||
|
{
|
||||||
|
esp_partition_mmap_handle_t mmap_handle;
|
||||||
|
uint32_t read_index;
|
||||||
|
const void *mapped_ptr;
|
||||||
|
const uint8_t *buffer;
|
||||||
|
uint32_t print_len;
|
||||||
|
uint32_t max_print_len;
|
||||||
|
esp_err_t err;
|
||||||
|
|
||||||
|
print_len = 0;
|
||||||
|
max_print_len = 4096;
|
||||||
|
err = esp_partition_mmap(log_partition, 0, MAX_STORAGE_SIZE, ESP_PARTITION_MMAP_DATA, &mapped_ptr, &mmap_handle);
|
||||||
|
if (err != ESP_OK) {
|
||||||
|
ESP_LOGE("FLASH", "Mmap failed: %s", esp_err_to_name(err));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
r_ble_log_async_output_dump_all(true);
|
||||||
|
esp_bt_ontroller_log_deinit();
|
||||||
|
stop_write = true;
|
||||||
|
|
||||||
|
buffer = (const uint8_t *)mapped_ptr;
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
if (is_filled) {
|
||||||
|
read_index = next_erase_index;
|
||||||
|
} else {
|
||||||
|
read_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_rom_printf("\r\nREAD_CHECK:%ld,%ld,%d\r\n",read_index, write_index, is_filled);
|
||||||
|
esp_rom_printf("\r\n[DUMP_START:");
|
||||||
|
while (read_index != write_index) {
|
||||||
|
esp_rom_printf("%02x ", buffer[read_index]);
|
||||||
|
if (print_len > max_print_len) {
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
print_len = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
print_len++;
|
||||||
|
read_index = (read_index + 1) % MAX_STORAGE_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_rom_printf(":DUMP_END]\r\n");
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_partition_munmap(mmap_handle);
|
||||||
|
err = esp_bt_controller_log_init(log_output_mode);
|
||||||
|
assert(err == ESP_OK);
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
/* This variable tells if BLE is running */
|
/* This variable tells if BLE is running */
|
||||||
@ -192,6 +393,7 @@ static bool s_ble_active = false;
|
|||||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||||
#endif // CONFIG_PM_ENABLE
|
#endif // CONFIG_PM_ENABLE
|
||||||
|
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||||
|
|
||||||
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
|
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
|
||||||
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
|
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
|
||||||
@ -335,6 +537,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||||
|
{
|
||||||
|
return s_bt_lpclk_src;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||||
|
{
|
||||||
|
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
s_bt_lpclk_src = clk_src;
|
||||||
|
}
|
||||||
|
|
||||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||||
{
|
{
|
||||||
if (!s_ble_active) {
|
if (!s_ble_active) {
|
||||||
@ -368,7 +584,7 @@ static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
|
|||||||
{
|
{
|
||||||
uint8_t size;
|
uint8_t size;
|
||||||
int extra = *(int *)arg;
|
int extra = *(int *)arg;
|
||||||
const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
sleep_retention_entries_config_t *ble_mac_modem_config = r_esp_ble_mac_retention_link_get(&size, extra);
|
||||||
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||||
if (err == ESP_OK) {
|
if (err == ESP_OK) {
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||||
@ -558,16 +774,54 @@ void ble_controller_scan_duplicate_config(void)
|
|||||||
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||||
|
{
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||||
|
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
#else
|
||||||
|
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||||
|
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
|
||||||
|
} else {
|
||||||
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
}
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||||
|
#else
|
||||||
|
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||||
|
assert(0);
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||||
|
cfg->rtc_freq = 100000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
|
||||||
|
cfg->rtc_freq = 32768;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
|
||||||
|
cfg->rtc_freq = 30000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
|
||||||
|
cfg->rtc_freq = 32000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||||
|
cfg->rtc_freq = 32000;
|
||||||
|
}
|
||||||
|
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||||
|
}
|
||||||
|
|
||||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||||
{
|
{
|
||||||
uint8_t mac[6];
|
uint8_t mac[6];
|
||||||
esp_err_t ret = ESP_OK;
|
esp_err_t ret = ESP_OK;
|
||||||
ble_npl_count_info_t npl_info;
|
ble_npl_count_info_t npl_info;
|
||||||
uint32_t slow_clk_freq = 0;
|
|
||||||
uint8_t hci_transport_mode;
|
uint8_t hci_transport_mode;
|
||||||
|
|
||||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||||
|
|
||||||
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
|
if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
|
||||||
return ESP_ERR_INVALID_STATE;
|
return ESP_ERR_INVALID_STATE;
|
||||||
@ -616,33 +870,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
modem_clock_module_enable(PERIPH_BT_MODULE);
|
modem_clock_module_enable(PERIPH_BT_MODULE);
|
||||||
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
||||||
/* Select slow clock source for BT momdule */
|
/* Select slow clock source for BT momdule */
|
||||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
ble_rtc_clk_init(cfg);
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
|
||||||
slow_clk_freq = 100000;
|
|
||||||
#else
|
|
||||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
|
|
||||||
slow_clk_freq = 30000;
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
|
||||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
|
|
||||||
slow_clk_freq = 32768;
|
|
||||||
} else {
|
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
|
||||||
slow_clk_freq = 100000;
|
|
||||||
}
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
|
|
||||||
slow_clk_freq = 32000;
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
|
|
||||||
slow_clk_freq = 32000;
|
|
||||||
#else
|
|
||||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
|
||||||
assert(0);
|
|
||||||
#endif
|
|
||||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
|
||||||
esp_phy_modem_init();
|
esp_phy_modem_init();
|
||||||
|
|
||||||
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
||||||
@ -656,20 +884,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
#endif // CONFIG_SW_COEXIST_ENABLE
|
#endif // CONFIG_SW_COEXIST_ENABLE
|
||||||
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
interface_func_t bt_controller_log_interface;
|
ret = esp_bt_controller_log_init(log_output_mode);
|
||||||
bt_controller_log_interface = esp_bt_controller_log_interface;
|
|
||||||
uint8_t buffers = 0;
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
|
||||||
buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
|
||||||
buffers |= ESP_BLE_LOG_BUF_HCI;
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
|
||||||
ret = r_ble_log_init_async(bt_controller_log_interface, false, buffers, (uint32_t *)log_bufs_size);
|
|
||||||
#else
|
|
||||||
ret = r_ble_log_init_async(bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
|
|
||||||
#endif // CONFIG_BT_CONTROLLER_LOG_DUMP
|
|
||||||
if (ret != ESP_OK) {
|
if (ret != ESP_OK) {
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
|
||||||
goto modem_deint;
|
goto modem_deint;
|
||||||
@ -688,7 +903,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
||||||
r_esp_ble_change_rtc_freq(slow_clk_freq);
|
|
||||||
|
|
||||||
ble_controller_scan_duplicate_config();
|
ble_controller_scan_duplicate_config();
|
||||||
|
|
||||||
@ -703,7 +917,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
|
||||||
goto free_controller;
|
goto free_controller;
|
||||||
}
|
}
|
||||||
|
|
||||||
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
||||||
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Bluetooth MAC: %02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||||
swap_in_place(mac, 6);
|
swap_in_place(mac, 6);
|
||||||
r_esp_ble_ll_set_public_addr(mac);
|
r_esp_ble_ll_set_public_addr(mac);
|
||||||
|
|
||||||
@ -732,7 +949,7 @@ free_controller:
|
|||||||
modem_deint:
|
modem_deint:
|
||||||
esp_ble_unregister_bb_funcs();
|
esp_ble_unregister_bb_funcs();
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
r_ble_log_deinit_async();
|
esp_bt_ontroller_log_deinit();
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
esp_phy_modem_deinit();
|
esp_phy_modem_deinit();
|
||||||
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
|
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
|
||||||
@ -768,7 +985,7 @@ esp_err_t esp_bt_controller_deinit(void)
|
|||||||
r_ble_controller_deinit();
|
r_ble_controller_deinit();
|
||||||
esp_ble_unregister_bb_funcs();
|
esp_ble_unregister_bb_funcs();
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
r_ble_log_deinit_async();
|
esp_bt_ontroller_log_deinit();
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
#if CONFIG_BT_NIMBLE_ENABLED
|
#if CONFIG_BT_NIMBLE_ENABLED
|
||||||
@ -1088,24 +1305,40 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
|
|||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
|
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
|
||||||
{
|
{
|
||||||
for (int i = 0; i < len; i++) {
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
esp_rom_printf("%02x ", addr[i]);
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
}
|
esp_bt_controller_log_storage(len, addr, end);
|
||||||
if (end) {
|
#endif //CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
esp_rom_printf("\n");
|
} else {
|
||||||
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_panic_handler_reconfigure_wdts(1000);
|
||||||
|
for (int i = 0; i < len; i++) {
|
||||||
|
esp_rom_printf("%02x ", addr[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (end) {
|
||||||
|
esp_rom_printf("\n");
|
||||||
|
}
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void esp_ble_controller_log_dump_all(bool output)
|
void esp_ble_controller_log_dump_all(bool output)
|
||||||
{
|
{
|
||||||
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
portENTER_CRITICAL_SAFE(&spinlock);
|
esp_bt_read_ctrl_log_from_flash(output);
|
||||||
esp_panic_handler_reconfigure_wdts(5000);
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
BT_ASSERT_PRINT("\r\n[DUMP_START:");
|
} else {
|
||||||
r_ble_log_async_output_dump_all(output);
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
BT_ASSERT_PRINT(":DUMP_END]\r\n");
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
portEXIT_CRITICAL_SAFE(&spinlock);
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
BT_ASSERT_PRINT("\r\n[DUMP_START:");
|
||||||
|
r_ble_log_async_output_dump_all(output);
|
||||||
|
BT_ASSERT_PRINT(":DUMP_END]\r\n");
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
|
@ -333,6 +333,24 @@ config BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
|||||||
help
|
help
|
||||||
Only operate in dump mode
|
Only operate in dump mode
|
||||||
|
|
||||||
|
config BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
bool "Store ble controller logs to flash(Experimental)"
|
||||||
|
depends on !BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Store ble controller logs to flash memory.
|
||||||
|
|
||||||
|
config BT_LE_CONTROLLER_LOG_PARTITION_SIZE
|
||||||
|
int "size of ble controller log partition(Multiples of 4K)"
|
||||||
|
depends on BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
default 65536
|
||||||
|
help
|
||||||
|
The size of ble controller log partition shall be a multiples of 4K.
|
||||||
|
The name of log partition shall be "bt_ctrl_log".
|
||||||
|
The partition type shall be ESP_PARTITION_TYPE_DATA.
|
||||||
|
The partition sub_type shall be ESP_PARTITION_SUBTYPE_ANY.
|
||||||
|
|
||||||
config BT_LE_LOG_CTRL_BUF1_SIZE
|
config BT_LE_LOG_CTRL_BUF1_SIZE
|
||||||
int "size of the first BLE controller LOG buffer"
|
int "size of the first BLE controller LOG buffer"
|
||||||
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
depends on BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
@ -126,9 +126,12 @@ extern void r_ble_rtc_wake_up_state_clr(void);
|
|||||||
extern int os_msys_init(void);
|
extern int os_msys_init(void);
|
||||||
extern void os_msys_deinit(void);
|
extern void os_msys_deinit(void);
|
||||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
||||||
extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
|
extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
|
||||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||||
|
#if CONFIG_PM_ENABLE
|
||||||
|
extern void r_esp_ble_stop_wakeup_timing(void);
|
||||||
|
#endif // CONFIG_PM_ENABLE
|
||||||
extern void r_esp_ble_change_rtc_freq(uint32_t freq);
|
extern void r_esp_ble_change_rtc_freq(uint32_t freq);
|
||||||
extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
|
extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
|
||||||
const uint8_t *peer_pub_key_y,
|
const uint8_t *peer_pub_key_y,
|
||||||
@ -168,6 +171,9 @@ static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer
|
|||||||
const uint8_t *our_priv_key, uint8_t *out_dhkey);
|
const uint8_t *our_priv_key, uint8_t *out_dhkey);
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
|
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
|
||||||
|
#endif // #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
/* Local variable definition
|
/* Local variable definition
|
||||||
***************************************************************************
|
***************************************************************************
|
||||||
@ -176,6 +182,203 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
|
|||||||
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
|
||||||
|
enum log_out_mode {
|
||||||
|
LOG_DUMP_MEMORY,
|
||||||
|
LOG_ASYNC_OUT,
|
||||||
|
LOG_STORAGE_TO_FLASH,
|
||||||
|
};
|
||||||
|
|
||||||
|
bool log_is_inited = false;
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
uint8_t log_output_mode = LOG_DUMP_MEMORY;
|
||||||
|
#else
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
uint8_t log_output_mode = LOG_STORAGE_TO_FLASH;
|
||||||
|
#else
|
||||||
|
uint8_t log_output_mode = LOG_ASYNC_OUT;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
||||||
|
|
||||||
|
void esp_bt_log_output_mode_set(uint8_t output_mode)
|
||||||
|
{
|
||||||
|
log_output_mode = output_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t esp_bt_log_output_mode_get(void)
|
||||||
|
{
|
||||||
|
return log_output_mode;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
|
||||||
|
{
|
||||||
|
esp_err_t ret = ESP_OK;
|
||||||
|
interface_func_t bt_controller_log_interface;
|
||||||
|
bt_controller_log_interface = esp_bt_controller_log_interface;
|
||||||
|
bool task_create;
|
||||||
|
uint8_t buffers = 0;
|
||||||
|
|
||||||
|
if (log_is_inited) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
||||||
|
buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
||||||
|
buffers |= ESP_BLE_LOG_BUF_HCI;
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
||||||
|
|
||||||
|
switch (log_output_mode) {
|
||||||
|
case LOG_DUMP_MEMORY:
|
||||||
|
task_create = false;
|
||||||
|
break;
|
||||||
|
case LOG_ASYNC_OUT:
|
||||||
|
case LOG_STORAGE_TO_FLASH:
|
||||||
|
task_create = true;
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
|
esp_bt_ctrl_log_partition_get_and_erase_first_block();
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
assert(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = r_ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
|
||||||
|
if (ret == ESP_OK) {
|
||||||
|
log_is_inited = true;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_ontroller_log_deinit(void)
|
||||||
|
{
|
||||||
|
r_ble_log_deinit_async();
|
||||||
|
log_is_inited = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
#include "esp_partition.h"
|
||||||
|
#include "hal/wdt_hal.h"
|
||||||
|
|
||||||
|
#define MAX_STORAGE_SIZE (CONFIG_BT_LE_CONTROLLER_LOG_PARTITION_SIZE)
|
||||||
|
#define BLOCK_SIZE (4096)
|
||||||
|
#define THRESHOLD (3072)
|
||||||
|
#define PARTITION_NAME "bt_ctrl_log"
|
||||||
|
|
||||||
|
static const esp_partition_t *log_partition;
|
||||||
|
static uint32_t write_index = 0;
|
||||||
|
static uint32_t next_erase_index = BLOCK_SIZE;
|
||||||
|
static bool block_erased = false;
|
||||||
|
static bool stop_write = false;
|
||||||
|
static bool is_filled = false;
|
||||||
|
|
||||||
|
static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void)
|
||||||
|
{
|
||||||
|
log_partition = NULL;
|
||||||
|
assert(MAX_STORAGE_SIZE % BLOCK_SIZE == 0);
|
||||||
|
// Find the partition map in the partition table
|
||||||
|
log_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, PARTITION_NAME);
|
||||||
|
assert(log_partition != NULL);
|
||||||
|
// Prepare data to be read later using the mapped address
|
||||||
|
ESP_ERROR_CHECK(esp_partition_erase_range(log_partition, 0, BLOCK_SIZE));
|
||||||
|
write_index = 0;
|
||||||
|
next_erase_index = BLOCK_SIZE;
|
||||||
|
block_erased = false;
|
||||||
|
is_filled = false;
|
||||||
|
stop_write = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end)
|
||||||
|
{
|
||||||
|
if (len > MAX_STORAGE_SIZE) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (stop_write) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (((write_index) % BLOCK_SIZE) >= THRESHOLD && !block_erased) {
|
||||||
|
// esp_rom_printf("Ers nxt: %d,%d\n", next_erase_index, write_index);
|
||||||
|
esp_partition_erase_range(log_partition, next_erase_index, BLOCK_SIZE);
|
||||||
|
next_erase_index = (next_erase_index + BLOCK_SIZE) % MAX_STORAGE_SIZE;
|
||||||
|
block_erased = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (((write_index + len) / BLOCK_SIZE) > (write_index / BLOCK_SIZE)) {
|
||||||
|
block_erased = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (write_index + len <= MAX_STORAGE_SIZE) {
|
||||||
|
esp_partition_write(log_partition, write_index, addr, len);
|
||||||
|
write_index = (write_index + len) % MAX_STORAGE_SIZE;
|
||||||
|
} else {
|
||||||
|
uint32_t first_part_len = MAX_STORAGE_SIZE - write_index;
|
||||||
|
esp_partition_write(log_partition, write_index, addr, first_part_len);
|
||||||
|
esp_partition_write(log_partition, 0, addr + first_part_len, len - first_part_len);
|
||||||
|
write_index = len - first_part_len;
|
||||||
|
is_filled = true;
|
||||||
|
// esp_rom_printf("old idx: %d,%d\n",next_erase_index, write_index);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_read_ctrl_log_from_flash(bool output)
|
||||||
|
{
|
||||||
|
esp_partition_mmap_handle_t mmap_handle;
|
||||||
|
uint32_t read_index;
|
||||||
|
const void *mapped_ptr;
|
||||||
|
const uint8_t *buffer;
|
||||||
|
uint32_t print_len;
|
||||||
|
uint32_t max_print_len;
|
||||||
|
esp_err_t err;
|
||||||
|
|
||||||
|
print_len = 0;
|
||||||
|
max_print_len = 4096;
|
||||||
|
err = esp_partition_mmap(log_partition, 0, MAX_STORAGE_SIZE, ESP_PARTITION_MMAP_DATA, &mapped_ptr, &mmap_handle);
|
||||||
|
if (err != ESP_OK) {
|
||||||
|
ESP_LOGE("FLASH", "Mmap failed: %s", esp_err_to_name(err));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
r_ble_log_async_output_dump_all(true);
|
||||||
|
esp_bt_ontroller_log_deinit();
|
||||||
|
stop_write = true;
|
||||||
|
|
||||||
|
buffer = (const uint8_t *)mapped_ptr;
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
if (is_filled) {
|
||||||
|
read_index = next_erase_index;
|
||||||
|
} else {
|
||||||
|
read_index = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_rom_printf("\r\nREAD_CHECK:%ld,%ld,%d\r\n",read_index, write_index, is_filled);
|
||||||
|
esp_rom_printf("\r\n[DUMP_START:");
|
||||||
|
while (read_index != write_index) {
|
||||||
|
esp_rom_printf("%02x ", buffer[read_index]);
|
||||||
|
if (print_len > max_print_len) {
|
||||||
|
esp_panic_handler_reconfigure_wdts(5000);
|
||||||
|
print_len = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
print_len++;
|
||||||
|
read_index = (read_index + 1) % MAX_STORAGE_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
esp_rom_printf(":DUMP_END]\r\n");
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_partition_munmap(mmap_handle);
|
||||||
|
err = esp_bt_controller_log_init(log_output_mode);
|
||||||
|
assert(err == ESP_OK);
|
||||||
|
}
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
/* This variable tells if BLE is running */
|
/* This variable tells if BLE is running */
|
||||||
@ -184,6 +387,7 @@ static bool s_ble_active = false;
|
|||||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||||
#endif // CONFIG_PM_ENABLE
|
#endif // CONFIG_PM_ENABLE
|
||||||
|
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||||
|
|
||||||
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (5100)
|
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (5100)
|
||||||
#define BLE_RTC_DELAY_US_MODEM_SLEEP (1500)
|
#define BLE_RTC_DELAY_US_MODEM_SLEEP (1500)
|
||||||
@ -322,6 +526,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||||
|
{
|
||||||
|
return s_bt_lpclk_src;
|
||||||
|
}
|
||||||
|
|
||||||
|
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||||
|
{
|
||||||
|
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
s_bt_lpclk_src = clk_src;
|
||||||
|
}
|
||||||
|
|
||||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||||
{
|
{
|
||||||
if (!s_ble_active) {
|
if (!s_ble_active) {
|
||||||
@ -355,7 +573,7 @@ static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
|
|||||||
{
|
{
|
||||||
uint8_t size;
|
uint8_t size;
|
||||||
int extra = *(int *)arg;
|
int extra = *(int *)arg;
|
||||||
const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
sleep_retention_entries_config_t *ble_mac_modem_config = r_esp_ble_mac_retention_link_get(&size, extra);
|
||||||
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||||
if (err == ESP_OK) {
|
if (err == ESP_OK) {
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||||
@ -413,6 +631,9 @@ esp_err_t controller_sleep_init(void)
|
|||||||
if (rc != ESP_OK) {
|
if (rc != ESP_OK) {
|
||||||
goto error;
|
goto error;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
rc = esp_deep_sleep_register_hook(&r_esp_ble_stop_wakeup_timing);
|
||||||
|
assert(rc == 0);
|
||||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||||
/* Create a new regdma link for BLE related register restoration */
|
/* Create a new regdma link for BLE related register restoration */
|
||||||
rc = sleep_modem_ble_mac_modem_state_init(0);
|
rc = sleep_modem_ble_mac_modem_state_init(0);
|
||||||
@ -433,6 +654,7 @@ error:
|
|||||||
esp_sleep_disable_bt_wakeup();
|
esp_sleep_disable_bt_wakeup();
|
||||||
esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
|
esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
|
||||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||||
|
esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
|
||||||
/*lock should release first and then delete*/
|
/*lock should release first and then delete*/
|
||||||
if (s_pm_lock != NULL) {
|
if (s_pm_lock != NULL) {
|
||||||
esp_pm_lock_delete(s_pm_lock);
|
esp_pm_lock_delete(s_pm_lock);
|
||||||
@ -452,6 +674,7 @@ void controller_sleep_deinit(void)
|
|||||||
esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
|
esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
|
||||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||||
#ifdef CONFIG_PM_ENABLE
|
#ifdef CONFIG_PM_ENABLE
|
||||||
|
esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
|
||||||
/* lock should be released first */
|
/* lock should be released first */
|
||||||
esp_pm_lock_delete(s_pm_lock);
|
esp_pm_lock_delete(s_pm_lock);
|
||||||
s_pm_lock = NULL;
|
s_pm_lock = NULL;
|
||||||
@ -529,12 +752,51 @@ void ble_controller_scan_duplicate_config(void)
|
|||||||
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||||
|
{
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||||
|
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
#else
|
||||||
|
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||||
|
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
|
||||||
|
} else {
|
||||||
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||||
|
}
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
|
||||||
|
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||||
|
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||||
|
#else
|
||||||
|
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||||
|
assert(0);
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||||
|
cfg->rtc_freq = 100000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
|
||||||
|
cfg->rtc_freq = 32768;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
|
||||||
|
cfg->rtc_freq = 30000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
|
||||||
|
cfg->rtc_freq = 32000;
|
||||||
|
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||||
|
cfg->rtc_freq = 32000;
|
||||||
|
}
|
||||||
|
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||||
|
}
|
||||||
|
|
||||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||||
{
|
{
|
||||||
uint8_t mac[6];
|
uint8_t mac[6];
|
||||||
esp_err_t ret = ESP_OK;
|
esp_err_t ret = ESP_OK;
|
||||||
ble_npl_count_info_t npl_info;
|
ble_npl_count_info_t npl_info;
|
||||||
uint32_t slow_clk_freq = 0;
|
|
||||||
uint8_t hci_transport_mode;
|
uint8_t hci_transport_mode;
|
||||||
|
|
||||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||||
@ -586,33 +848,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
modem_clock_module_enable(PERIPH_BT_MODULE);
|
modem_clock_module_enable(PERIPH_BT_MODULE);
|
||||||
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
||||||
/* Select slow clock source for BT momdule */
|
/* Select slow clock source for BT momdule */
|
||||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
ble_rtc_clk_init(cfg);
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
|
||||||
slow_clk_freq = 100000;
|
|
||||||
#else
|
|
||||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
|
|
||||||
slow_clk_freq = 30000;
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
|
||||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
|
|
||||||
slow_clk_freq = 32768;
|
|
||||||
} else {
|
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
|
||||||
slow_clk_freq = 100000;
|
|
||||||
}
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
|
|
||||||
slow_clk_freq = 32000;
|
|
||||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
|
||||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
|
|
||||||
slow_clk_freq = 32000;
|
|
||||||
#else
|
|
||||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
|
||||||
assert(0);
|
|
||||||
#endif
|
|
||||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
|
||||||
|
|
||||||
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
|
||||||
@ -625,20 +861,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
#endif // CONFIG_SW_COEXIST_ENABLE
|
#endif // CONFIG_SW_COEXIST_ENABLE
|
||||||
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
interface_func_t bt_controller_log_interface;
|
ret = esp_bt_controller_log_init(log_output_mode);
|
||||||
bt_controller_log_interface = esp_bt_controller_log_interface;
|
|
||||||
uint8_t buffers = 0;
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
|
||||||
buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
|
||||||
buffers |= ESP_BLE_LOG_BUF_HCI;
|
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
|
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
|
|
||||||
ret = r_ble_log_init_async(bt_controller_log_interface, false, buffers, (uint32_t *)log_bufs_size);
|
|
||||||
#else
|
|
||||||
ret = r_ble_log_init_async(bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
|
|
||||||
#endif // CONFIG_BT_CONTROLLER_LOG_DUMP
|
|
||||||
if (ret != ESP_OK) {
|
if (ret != ESP_OK) {
|
||||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
|
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
|
||||||
goto modem_deint;
|
goto modem_deint;
|
||||||
@ -657,7 +880,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
||||||
r_esp_ble_change_rtc_freq(slow_clk_freq);
|
|
||||||
|
|
||||||
ble_controller_scan_duplicate_config();
|
ble_controller_scan_duplicate_config();
|
||||||
|
|
||||||
@ -673,6 +895,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
|||||||
goto free_controller;
|
goto free_controller;
|
||||||
}
|
}
|
||||||
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
|
||||||
|
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Bluetooth MAC: %02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
|
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||||
swap_in_place(mac, 6);
|
swap_in_place(mac, 6);
|
||||||
r_esp_ble_ll_set_public_addr(mac);
|
r_esp_ble_ll_set_public_addr(mac);
|
||||||
|
|
||||||
@ -701,7 +925,7 @@ free_controller:
|
|||||||
modem_deint:
|
modem_deint:
|
||||||
esp_ble_unregister_bb_funcs();
|
esp_ble_unregister_bb_funcs();
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
r_ble_log_deinit_async();
|
esp_bt_ontroller_log_deinit();
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
|
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
|
||||||
modem_clock_module_disable(PERIPH_BT_MODULE);
|
modem_clock_module_disable(PERIPH_BT_MODULE);
|
||||||
@ -735,7 +959,7 @@ esp_err_t esp_bt_controller_deinit(void)
|
|||||||
r_ble_controller_deinit();
|
r_ble_controller_deinit();
|
||||||
esp_ble_unregister_bb_funcs();
|
esp_ble_unregister_bb_funcs();
|
||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
r_ble_log_deinit_async();
|
esp_bt_ontroller_log_deinit();
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
#if CONFIG_BT_NIMBLE_ENABLED
|
#if CONFIG_BT_NIMBLE_ENABLED
|
||||||
@ -1055,16 +1279,30 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po
|
|||||||
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
|
static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
|
||||||
{
|
{
|
||||||
for (int i = 0; i < len; i++) {
|
if (log_output_mode == LOG_STORAGE_TO_FLASH) {
|
||||||
esp_rom_printf("%02x ", addr[i]);
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
}
|
esp_bt_controller_log_storage(len, addr, end);
|
||||||
if (end) {
|
#endif //CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
esp_rom_printf("\n");
|
} else {
|
||||||
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
|
esp_panic_handler_reconfigure_wdts(1000);
|
||||||
|
for (int i = 0; i < len; i++) {
|
||||||
|
esp_rom_printf("%02x ", addr[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (end) {
|
||||||
|
esp_rom_printf("\n");
|
||||||
|
}
|
||||||
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void esp_ble_controller_log_dump_all(bool output)
|
void esp_ble_controller_log_dump_all(bool output)
|
||||||
{
|
{
|
||||||
|
#if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
|
esp_bt_read_ctrl_log_from_flash(output);
|
||||||
|
#else
|
||||||
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
|
|
||||||
portENTER_CRITICAL_SAFE(&spinlock);
|
portENTER_CRITICAL_SAFE(&spinlock);
|
||||||
@ -1073,6 +1311,7 @@ void esp_ble_controller_log_dump_all(bool output)
|
|||||||
r_ble_log_async_output_dump_all(output);
|
r_ble_log_async_output_dump_all(output);
|
||||||
BT_ASSERT_PRINT(":DUMP_END]\r\n");
|
BT_ASSERT_PRINT(":DUMP_END]\r\n");
|
||||||
portEXIT_CRITICAL_SAFE(&spinlock);
|
portEXIT_CRITICAL_SAFE(&spinlock);
|
||||||
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
|
||||||
}
|
}
|
||||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||||
|
|
||||||
|
@ -1 +1 @@
|
|||||||
Subproject commit ad0d5df0b9890c783c02da126df8a979e5ca1cf9
|
Subproject commit 8112ca2c575c6feb32d755623f097f1b66759490
|
@ -1 +1 @@
|
|||||||
Subproject commit fc65dbee2093051bdf8dd45fd4346811a39a4ff8
|
Subproject commit e652624750341aca124e9f850e261b0c1ac63529
|
@ -1 +1 @@
|
|||||||
Subproject commit bfdfe8f851c99ced8316b133b0b15521917ea049
|
Subproject commit d874f55e1132416fe18293ae1aa9ac73c40b3261
|
@ -1 +1 @@
|
|||||||
Subproject commit a59ed65177bd3af09efcbf687a3360c824549cdd
|
Subproject commit 53056440bc6e76f5bf00fd920769a4979dcc7d66
|
@ -1 +1 @@
|
|||||||
Subproject commit 2085541b6e9963640e4090401faaf2061758d847
|
Subproject commit f95513f22be7b21429b01ba05dbfbc98097b5e67
|
@ -1 +1 @@
|
|||||||
Subproject commit 9e29a8b39fe81ac82064dc4525e56e0faa9e1b8a
|
Subproject commit 58a293a2b4c305157723908ea29c2776f5803bbc
|
@ -1309,7 +1309,6 @@ int bt_mesh_gatts_service_stop(struct bt_mesh_gatt_service *svc)
|
|||||||
{
|
{
|
||||||
int rc;
|
int rc;
|
||||||
uint16_t handle;
|
uint16_t handle;
|
||||||
const ble_uuid_t *uuid;
|
|
||||||
|
|
||||||
if (!svc) {
|
if (!svc) {
|
||||||
BT_ERR("%s, Invalid parameter", __func__);
|
BT_ERR("%s, Invalid parameter", __func__);
|
||||||
@ -1317,12 +1316,11 @@ int bt_mesh_gatts_service_stop(struct bt_mesh_gatt_service *svc)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (BLE_MESH_UUID_16(svc->attrs[0].user_data)->val == BT_UUID_MESH_PROXY_VAL) {
|
if (BLE_MESH_UUID_16(svc->attrs[0].user_data)->val == BT_UUID_MESH_PROXY_VAL) {
|
||||||
uuid = BLE_UUID16_DECLARE(BT_UUID_MESH_PROXY_VAL);
|
rc = ble_gatts_find_svc(BLE_UUID16_DECLARE(BT_UUID_MESH_PROXY_VAL), &handle);
|
||||||
} else {
|
} else {
|
||||||
uuid = BLE_UUID16_DECLARE(BT_UUID_MESH_PROV_VAL);
|
rc = ble_gatts_find_svc(BLE_UUID16_DECLARE(BT_UUID_MESH_PROV_VAL), &handle);
|
||||||
}
|
}
|
||||||
|
|
||||||
rc = ble_gatts_find_svc(uuid, &handle);
|
|
||||||
assert(rc == 0);
|
assert(rc == 0);
|
||||||
ble_gatts_svc_set_visibility(handle, 0);
|
ble_gatts_svc_set_visibility(handle, 0);
|
||||||
|
|
||||||
@ -1336,15 +1334,13 @@ int bt_mesh_gatts_service_start(struct bt_mesh_gatt_service *svc)
|
|||||||
{
|
{
|
||||||
int rc;
|
int rc;
|
||||||
uint16_t handle;
|
uint16_t handle;
|
||||||
const ble_uuid_t *uuid;
|
|
||||||
|
|
||||||
if (BLE_MESH_UUID_16(svc->attrs[0].user_data)->val == BT_UUID_MESH_PROXY_VAL) {
|
if (BLE_MESH_UUID_16(svc->attrs[0].user_data)->val == BT_UUID_MESH_PROXY_VAL) {
|
||||||
uuid = BLE_UUID16_DECLARE(BT_UUID_MESH_PROXY_VAL);
|
rc = ble_gatts_find_svc(BLE_UUID16_DECLARE(BT_UUID_MESH_PROXY_VAL), &handle);
|
||||||
} else {
|
} else {
|
||||||
uuid = BLE_UUID16_DECLARE(BT_UUID_MESH_PROV_VAL);
|
rc = ble_gatts_find_svc(BLE_UUID16_DECLARE(BT_UUID_MESH_PROV_VAL), &handle);
|
||||||
}
|
}
|
||||||
|
|
||||||
rc = ble_gatts_find_svc(uuid, &handle);
|
|
||||||
assert(rc == 0);
|
assert(rc == 0);
|
||||||
ble_gatts_svc_set_visibility(handle, 1);
|
ble_gatts_svc_set_visibility(handle, 1);
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -8,6 +8,8 @@
|
|||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
|
|
||||||
|
#include "esp_log.h"
|
||||||
|
|
||||||
#if CONFIG_BT_BLUEDROID_ENABLED
|
#if CONFIG_BT_BLUEDROID_ENABLED
|
||||||
#include "bta/bta_api.h"
|
#include "bta/bta_api.h"
|
||||||
#endif
|
#endif
|
||||||
@ -190,6 +192,11 @@ void bt_mesh_ext_mem_swap(void *buf, size_t length)
|
|||||||
sys_mem_swap(buf, length);
|
sys_mem_swap(buf, length);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
uint32_t bt_mesh_ext_log_timestamp(void)
|
||||||
|
{
|
||||||
|
return esp_log_timestamp();
|
||||||
|
}
|
||||||
|
|
||||||
/* Net buf */
|
/* Net buf */
|
||||||
void bt_mesh_ext_buf_simple_init(struct net_buf_simple *buf, size_t reserve_head)
|
void bt_mesh_ext_buf_simple_init(struct net_buf_simple *buf, size_t reserve_head)
|
||||||
{
|
{
|
||||||
@ -498,6 +505,11 @@ float bt_mesh_ext_log2(float num)
|
|||||||
return bt_mesh_log2(num);
|
return bt_mesh_log2(num);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
const char *bt_mesh_ext_hex(const void *buf, size_t len)
|
||||||
|
{
|
||||||
|
return bt_hex(buf, len);
|
||||||
|
}
|
||||||
|
|
||||||
/* Crypto */
|
/* Crypto */
|
||||||
bool bt_mesh_ext_s1(const char *m, uint8_t salt[16])
|
bool bt_mesh_ext_s1(const char *m, uint8_t salt[16])
|
||||||
{
|
{
|
||||||
@ -3954,6 +3966,8 @@ void bt_mesh_ext_mbt_server_cb_evt_to_btc(uint8_t event, void *model, void *ctx)
|
|||||||
}
|
}
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
uint64_t config_ble_mesh_stack_trace_level : 3;
|
||||||
|
|
||||||
uint64_t config_ble_mesh_use_duplicate_scan : 1;
|
uint64_t config_ble_mesh_use_duplicate_scan : 1;
|
||||||
uint64_t config_ble_mesh_pb_adv : 1;
|
uint64_t config_ble_mesh_pb_adv : 1;
|
||||||
uint64_t config_ble_mesh_pb_gatt : 1;
|
uint64_t config_ble_mesh_pb_gatt : 1;
|
||||||
@ -4116,6 +4130,8 @@ typedef struct {
|
|||||||
} bt_mesh_ext_config_t;
|
} bt_mesh_ext_config_t;
|
||||||
|
|
||||||
static const bt_mesh_ext_config_t bt_mesh_ext_cfg = {
|
static const bt_mesh_ext_config_t bt_mesh_ext_cfg = {
|
||||||
|
.config_ble_mesh_stack_trace_level = BLE_MESH_LOG_LEVEL,
|
||||||
|
|
||||||
.config_ble_mesh_use_duplicate_scan = IS_ENABLED(CONFIG_BLE_MESH_USE_DUPLICATE_SCAN),
|
.config_ble_mesh_use_duplicate_scan = IS_ENABLED(CONFIG_BLE_MESH_USE_DUPLICATE_SCAN),
|
||||||
.config_ble_mesh_pb_adv = IS_ENABLED(CONFIG_BLE_MESH_PB_ADV),
|
.config_ble_mesh_pb_adv = IS_ENABLED(CONFIG_BLE_MESH_PB_ADV),
|
||||||
.config_ble_mesh_pb_gatt = IS_ENABLED(CONFIG_BLE_MESH_PB_GATT),
|
.config_ble_mesh_pb_gatt = IS_ENABLED(CONFIG_BLE_MESH_PB_GATT),
|
||||||
|
@ -1 +1 @@
|
|||||||
Subproject commit 4934ca903807dd74f7f808dadcd9a478e18fc6c3
|
Subproject commit 8312e0e0d5390d04fd282e8005528d2b5c351c08
|
@ -244,7 +244,8 @@ static void time_get(struct bt_mesh_model *model,
|
|||||||
change.time_status.subsecond = srv->state->time.subsecond;
|
change.time_status.subsecond = srv->state->time.subsecond;
|
||||||
change.time_status.uncertainty = srv->state->time.uncertainty;
|
change.time_status.uncertainty = srv->state->time.uncertainty;
|
||||||
change.time_status.time_authority = srv->state->time.time_authority;
|
change.time_status.time_authority = srv->state->time.time_authority;
|
||||||
change.time_status.tai_utc_delta_curr = srv->state->time.subsecond;
|
change.time_status.tai_utc_delta_curr = srv->state->time.tai_utc_delta_curr;
|
||||||
|
change.time_status.time_zone_offset_curr = srv->state->time.time_zone_offset_curr;
|
||||||
bt_mesh_time_scene_server_cb_evt_to_btc(BTC_BLE_MESH_EVT_TIME_SCENE_SERVER_STATE_CHANGE,
|
bt_mesh_time_scene_server_cb_evt_to_btc(BTC_BLE_MESH_EVT_TIME_SCENE_SERVER_STATE_CHANGE,
|
||||||
model, ctx, (const uint8_t *)&change, sizeof(change));
|
model, ctx, (const uint8_t *)&change, sizeof(change));
|
||||||
|
|
||||||
@ -386,7 +387,8 @@ static void time_set(struct bt_mesh_model *model,
|
|||||||
change.time_set.subsecond = srv->state->time.subsecond;
|
change.time_set.subsecond = srv->state->time.subsecond;
|
||||||
change.time_set.uncertainty = srv->state->time.uncertainty;
|
change.time_set.uncertainty = srv->state->time.uncertainty;
|
||||||
change.time_set.time_authority = srv->state->time.time_authority;
|
change.time_set.time_authority = srv->state->time.time_authority;
|
||||||
change.time_set.tai_utc_delta_curr = srv->state->time.subsecond;
|
change.time_set.tai_utc_delta_curr = srv->state->time.tai_utc_delta_curr;
|
||||||
|
change.time_set.time_zone_offset_curr = srv->state->time.time_zone_offset_curr;
|
||||||
break;
|
break;
|
||||||
case BLE_MESH_MODEL_OP_TIME_ZONE_SET:
|
case BLE_MESH_MODEL_OP_TIME_ZONE_SET:
|
||||||
change.time_zone_set.time_zone_offset_new = srv->state->time.time_zone_offset_new;
|
change.time_zone_set.time_zone_offset_new = srv->state->time.time_zone_offset_new;
|
||||||
|
@ -1223,3 +1223,10 @@ config BT_BLE_HIGH_DUTY_ADV_INTERVAL
|
|||||||
default n
|
default n
|
||||||
help
|
help
|
||||||
This enable BLE high duty advertising interval feature
|
This enable BLE high duty advertising interval feature
|
||||||
|
|
||||||
|
config BT_ABORT_WHEN_ALLOCATION_FAILS
|
||||||
|
bool "Abort when memory allocation fails in BT/BLE stack"
|
||||||
|
depends on BT_BLUEDROID_ENABLED
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
This enables abort when memory allocation fails
|
||||||
|
@ -238,3 +238,14 @@ esp_err_t esp_bluedroid_deinit(void)
|
|||||||
|
|
||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_EXAMPLE_CI_ID) && defined(CONFIG_EXAMPLE_CI_PIPELINE_ID)
|
||||||
|
char *esp_bluedroid_get_example_name(void)
|
||||||
|
{
|
||||||
|
static char example_name[ESP_BLE_ADV_NAME_LEN_MAX];
|
||||||
|
memset(example_name, 0, sizeof(example_name));
|
||||||
|
sprintf(example_name, "BE%02X_%05X_%02X", CONFIG_EXAMPLE_CI_ID & 0xFF,
|
||||||
|
CONFIG_EXAMPLE_CI_PIPELINE_ID & 0xFFFFF, CONFIG_IDF_FIRMWARE_CHIP_ID & 0xFF);
|
||||||
|
return example_name;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
@ -504,21 +504,37 @@ esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t
|
|||||||
return ESP_OK;
|
return ESP_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8_t *esp_ble_resolve_adv_data( uint8_t *adv_data, uint8_t type, uint8_t *length)
|
uint8_t *esp_ble_resolve_adv_data_by_type( uint8_t *adv_data, uint16_t adv_data_len, esp_ble_adv_data_type type, uint8_t *length)
|
||||||
{
|
{
|
||||||
|
if (length == NULL) {
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
if (((type < ESP_BLE_AD_TYPE_FLAG) || (type > ESP_BLE_AD_TYPE_128SERVICE_DATA)) &&
|
if (((type < ESP_BLE_AD_TYPE_FLAG) || (type > ESP_BLE_AD_TYPE_128SERVICE_DATA)) &&
|
||||||
(type != ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE)) {
|
(type != ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE)) {
|
||||||
LOG_ERROR("the eir type not define, type = %x\n", type);
|
LOG_ERROR("The advertising data type is not defined, type = %x", type);
|
||||||
|
*length = 0;
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (adv_data_len == 0) {
|
||||||
|
*length = 0;
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
if (adv_data == NULL) {
|
if (adv_data == NULL) {
|
||||||
LOG_ERROR("Invalid p_eir data.\n");
|
LOG_ERROR("Invalid advertising data.");
|
||||||
|
*length = 0;
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
return (BTM_CheckAdvData( adv_data, type, length));
|
return (BTM_CheckAdvData( adv_data, adv_data_len, type, length));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
uint8_t *esp_ble_resolve_adv_data( uint8_t *adv_data, uint8_t type, uint8_t *length)
|
||||||
|
{
|
||||||
|
return esp_ble_resolve_adv_data_by_type( adv_data, ESP_BLE_ADV_DATA_LEN_MAX + ESP_BLE_SCAN_RSP_DATA_LEN_MAX, (esp_ble_adv_data_type) type, length);
|
||||||
|
}
|
||||||
|
|
||||||
#if (BLE_42_FEATURE_SUPPORT == TRUE)
|
#if (BLE_42_FEATURE_SUPPORT == TRUE)
|
||||||
esp_err_t esp_ble_gap_config_adv_data_raw(uint8_t *raw_data, uint32_t raw_data_len)
|
esp_err_t esp_ble_gap_config_adv_data_raw(uint8_t *raw_data, uint32_t raw_data_len)
|
||||||
{
|
{
|
||||||
|
@ -184,6 +184,7 @@ esp_err_t esp_bt_gap_set_cod(esp_bt_cod_t cod, esp_bt_cod_mode_t mode)
|
|||||||
}
|
}
|
||||||
|
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
|
case ESP_BT_SET_COD_RESERVED_2:
|
||||||
case ESP_BT_SET_COD_MAJOR_MINOR:
|
case ESP_BT_SET_COD_MAJOR_MINOR:
|
||||||
case ESP_BT_SET_COD_SERVICE_CLASS:
|
case ESP_BT_SET_COD_SERVICE_CLASS:
|
||||||
case ESP_BT_CLR_COD_SERVICE_CLASS:
|
case ESP_BT_CLR_COD_SERVICE_CLASS:
|
||||||
|
@ -110,6 +110,14 @@ typedef enum {
|
|||||||
ESP_BT_STATUS_HCI_CONN_TOUT_DUE_TO_MIC_FAILURE,
|
ESP_BT_STATUS_HCI_CONN_TOUT_DUE_TO_MIC_FAILURE,
|
||||||
ESP_BT_STATUS_HCI_CONN_FAILED_ESTABLISHMENT,
|
ESP_BT_STATUS_HCI_CONN_FAILED_ESTABLISHMENT,
|
||||||
ESP_BT_STATUS_HCI_MAC_CONNECTION_FAILED,
|
ESP_BT_STATUS_HCI_MAC_CONNECTION_FAILED,
|
||||||
|
ESP_BT_STATUS_HCI_CCA_REJECTED,
|
||||||
|
ESP_BT_STATUS_HCI_TYPE0_SUBMAP_NOT_DEFINED,
|
||||||
|
ESP_BT_STATUS_HCI_UNKNOWN_ADV_ID,
|
||||||
|
ESP_BT_STATUS_HCI_LIMIT_REACHED,
|
||||||
|
ESP_BT_STATUS_HCI_OPT_CANCEL_BY_HOST,
|
||||||
|
ESP_BT_STATUS_HCI_PKT_TOO_LONG,
|
||||||
|
ESP_BT_STATUS_HCI_TOO_LATE,
|
||||||
|
ESP_BT_STATUS_HCI_TOO_EARLY,
|
||||||
} esp_bt_status_t;
|
} esp_bt_status_t;
|
||||||
|
|
||||||
|
|
||||||
@ -201,6 +209,8 @@ typedef uint8_t esp_ble_key_mask_t; /* the key mask type */
|
|||||||
#define ESP_BD_ADDR_STR "%02x:%02x:%02x:%02x:%02x:%02x"
|
#define ESP_BD_ADDR_STR "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||||
#define ESP_BD_ADDR_HEX(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]
|
#define ESP_BD_ADDR_HEX(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]
|
||||||
|
|
||||||
|
#define ESP_BLE_ADV_NAME_LEN_MAX 29
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -95,6 +95,11 @@ esp_err_t esp_bluedroid_init_with_cfg(esp_bluedroid_config_t *cfg);
|
|||||||
*/
|
*/
|
||||||
esp_err_t esp_bluedroid_deinit(void);
|
esp_err_t esp_bluedroid_deinit(void);
|
||||||
|
|
||||||
|
#if defined(CONFIG_EXAMPLE_CI_ID) && defined(CONFIG_EXAMPLE_CI_PIPELINE_ID)
|
||||||
|
// Only for internal used (CI example test)
|
||||||
|
char *esp_bluedroid_get_example_name(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -631,6 +631,7 @@ typedef struct
|
|||||||
{
|
{
|
||||||
esp_bd_addr_t bd_addr; /*!< peer address */
|
esp_bd_addr_t bd_addr; /*!< peer address */
|
||||||
esp_ble_bond_key_info_t bond_key; /*!< the bond key information */
|
esp_ble_bond_key_info_t bond_key; /*!< the bond key information */
|
||||||
|
esp_ble_addr_type_t bd_addr_type; /*!< peer address type */
|
||||||
} esp_ble_bond_dev_t; /*!< the ble bond device type */
|
} esp_ble_bond_dev_t; /*!< the ble bond device type */
|
||||||
|
|
||||||
|
|
||||||
@ -1179,13 +1180,13 @@ typedef union {
|
|||||||
struct ble_update_conn_params_evt_param {
|
struct ble_update_conn_params_evt_param {
|
||||||
esp_bt_status_t status; /*!< Indicate update connection parameters success status */
|
esp_bt_status_t status; /*!< Indicate update connection parameters success status */
|
||||||
esp_bd_addr_t bda; /*!< Bluetooth device address */
|
esp_bd_addr_t bda; /*!< Bluetooth device address */
|
||||||
uint16_t min_int; /*!< Min connection interval */
|
uint16_t min_int; /*!< Minimum connection interval. If the master initiates the connection parameter update, this value is not applicable for the slave and will be set to zero. */
|
||||||
uint16_t max_int; /*!< Max connection interval */
|
uint16_t max_int; /*!< Maximum connection interval. If the master initiates the connection parameter update, this value is not applicable for the slave and will be set to zero. */
|
||||||
uint16_t latency; /*!< Slave latency for the connection in number of connection events. Range: 0x0000 to 0x01F3 */
|
uint16_t latency; /*!< Slave latency for the connection in number of connection events. Range: 0x0000 to 0x01F3 */
|
||||||
uint16_t conn_int; /*!< Current connection interval */
|
uint16_t conn_int; /*!< Current connection interval in milliseconds, calculated as N × 1.25 ms */
|
||||||
uint16_t timeout; /*!< Supervision timeout for the LE Link. Range: 0x000A to 0x0C80.
|
uint16_t timeout; /*!< Supervision timeout for the LE Link. Range: 0x000A to 0x0C80.
|
||||||
Mandatory Range: 0x000A to 0x0C80 Time = N * 10 msec */
|
This value is calculated as N × 10 ms */
|
||||||
} update_conn_params; /*!< Event parameter of ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT */
|
} update_conn_params; /*!< Event parameter for ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT */
|
||||||
/**
|
/**
|
||||||
* @brief ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT
|
* @brief ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT
|
||||||
*/
|
*/
|
||||||
@ -1902,17 +1903,41 @@ esp_err_t esp_ble_gap_get_device_name(void);
|
|||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t * addr_type);
|
esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t * addr_type);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief This function is called to get ADV data for a specific type.
|
* @brief This function is called to get ADV data for a specific type.
|
||||||
*
|
*
|
||||||
* @param[in] adv_data - pointer of ADV data which to be resolved
|
* @note This is the recommended function to use for resolving ADV data by type.
|
||||||
* @param[in] type - finding ADV data type
|
* It improves upon the deprecated `esp_ble_resolve_adv_data` function by
|
||||||
* @param[out] length - return the length of ADV data not including type
|
* including an additional parameter to specify the length of the ADV data,
|
||||||
|
* thereby offering better safety and reliability.
|
||||||
*
|
*
|
||||||
* @return pointer of ADV data
|
* @param[in] adv_data - pointer of ADV data which to be resolved
|
||||||
|
* @param[in] adv_data_len - the length of ADV data which to be resolved.
|
||||||
|
* @param[in] type - finding ADV data type
|
||||||
|
* @param[out] length - return the length of ADV data not including type
|
||||||
|
*
|
||||||
|
* @return pointer of ADV data
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
uint8_t *esp_ble_resolve_adv_data_by_type( uint8_t *adv_data, uint16_t adv_data_len, esp_ble_adv_data_type type, uint8_t *length);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function is called to get ADV data for a specific type.
|
||||||
|
*
|
||||||
|
* @note This function has been deprecated and will be removed in a future release.
|
||||||
|
* Please use `esp_ble_resolve_adv_data_by_type` instead, which provides
|
||||||
|
* better parameter validation and supports more accurate data resolution.
|
||||||
|
*
|
||||||
|
* @param[in] adv_data - pointer of ADV data which to be resolved
|
||||||
|
* @param[in] type - finding ADV data type
|
||||||
|
* @param[out] length - return the length of ADV data not including type
|
||||||
|
*
|
||||||
|
* @return pointer of ADV data
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
uint8_t *esp_ble_resolve_adv_data(uint8_t *adv_data, uint8_t type, uint8_t *length);
|
uint8_t *esp_ble_resolve_adv_data(uint8_t *adv_data, uint8_t type, uint8_t *length);
|
||||||
|
|
||||||
#if (BLE_42_FEATURE_SUPPORT == TRUE)
|
#if (BLE_42_FEATURE_SUPPORT == TRUE)
|
||||||
/**
|
/**
|
||||||
* @brief This function is called to set raw advertising data. User need to fill
|
* @brief This function is called to set raw advertising data. User need to fill
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user