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fix(gpio): esp32p4 IOs cannot keep being held in the entire deep sleep process

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This commit is contained in:
Song Ruo Jing 2024-08-05 21:00:37 +08:00
parent 1171c3c281
commit 706935f468
30 changed files with 156 additions and 25 deletions
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10
components/esp_driver_gpio/include/driver/gpio.h
View File

@ -376,7 +376,11 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
* in output mode: the output level of the GPIO will be locked and can not be changed.
* in input mode: the input read value can still reflect the changes of the input signal.
*
* However, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
* Please be aware that,
*
* On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep.
*
* Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
* Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from
* Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`.
*
@ -409,7 +413,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num);
*/
esp_err_t gpio_hold_dis(gpio_num_t gpio_num);
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Enable all digital gpio pads hold function during Deep-sleep.
*
@ -433,7 +437,7 @@ void gpio_deep_sleep_hold_en(void);
* @brief Disable all digital gpio pads hold function during Deep-sleep.
*/
void gpio_deep_sleep_hold_dis(void);
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Set pad input to a peripheral signal through the IOMUX.

4
components/esp_driver_gpio/src/gpio.c
View File

@ -753,7 +753,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
return ret;
}
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
void gpio_deep_sleep_hold_en(void)
{
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@ -767,7 +767,7 @@ void gpio_deep_sleep_hold_dis(void)
gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal);
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
}
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_FORCE_HOLD
esp_err_t IRAM_ATTR gpio_force_hold_all()

60
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@ -878,3 +878,63 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO);
}
#endif
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
// Pick one digital IO for each target to test is enough
static void gpio_deep_sleep_hold_test_first_stage(void)
{
printf("configure a digital pin to hold during deep sleep");
int io_num = TEST_GPIO_DEEP_SLEEP_HOLD_PIN;
TEST_ASSERT(GPIO_IS_VALID_DIGITAL_IO_PAD(io_num));
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2000000));
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT_OUTPUT,
.pin_bit_mask = (1ULL << io_num),
.pull_down_en = 0,
.pull_up_en = 0,
};
TEST_ESP_OK(gpio_config(&io_conf));
TEST_ESP_OK(gpio_set_level(io_num, 0));
// Enable global persistence
TEST_ESP_OK(gpio_hold_en(io_num));
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
// On such target, digital IOs cannot be held individually in Deep-sleep
// Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep
gpio_deep_sleep_hold_en();
#endif
esp_deep_sleep_start();
}
static void gpio_deep_sleep_hold_test_second_stage(void)
{
int io_num = TEST_GPIO_DEEP_SLEEP_HOLD_PIN;
// Check reset reason is waking up from deepsleep
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
// Pin should stay at low level after the deep sleep
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
// Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held)
TEST_ESP_OK(gpio_set_level(io_num, 1));
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
gpio_deep_sleep_hold_dis();
#endif
TEST_ESP_OK(gpio_hold_dis(io_num));
}
/*
* Test digital IOs hold function during deep sleep.
* This test case can only check the hold state after waking up from deep sleep
* If you want to check that the digital IO hold function works properly during deep sleep,
* please use logic analyzer or oscilloscope
*/
TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]",
gpio_deep_sleep_hold_test_first_stage,
gpio_deep_sleep_hold_test_second_stage)
#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP

12
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,27 +20,37 @@ extern "C" {
#define TEST_GPIO_INPUT_ONLY_PIN (34)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (4)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC224_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (5)
#elif CONFIG_IDF_TARGET_ESP32S2
#define TEST_GPIO_EXT_OUT_IO (17)
#define TEST_GPIO_EXT_IN_IO (21)
#define TEST_GPIO_INPUT_ONLY_PIN (46)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC223_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (45)
#elif CONFIG_IDF_TARGET_ESP32S3
#define TEST_GPIO_EXT_OUT_IO (17)
#define TEST_GPIO_EXT_IN_IO (21)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC208_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (45)
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX)
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (25)
#else
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (9)
#endif
#ifdef __cplusplus

8
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -235,10 +235,10 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
#endif //SOC_RTCIO_HOLD_SUPPORTED
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, P4: IO5, C5: IO5) these pads' default configuration is low level
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, C5: IO5) these pads' default configuration is low level
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5
static void rtcio_deep_sleep_hold_test_first_stage(void)
@ -284,4 +284,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
rtcio_deep_sleep_hold_test_first_stage,
rtcio_deep_sleep_hold_test_second_stage)
#endif // SOC_DEEP_SLEEP_SUPPORTED
#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP

2
components/esp_hw_support/include/esp_private/esp_sleep_internal.h
View File

@ -39,7 +39,7 @@ void esp_sleep_set_sleep_context(esp_sleep_context_t *sleep_ctx);
*/
void esp_sleep_enable_adc_tsens_monitor(bool enable);
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Isolate all digital IOs except those that are held during deep sleep
*

4
components/esp_hw_support/sleep_gpio.c
View File

@ -112,7 +112,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
}
}
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
{
gpio_hal_context_t gpio_hal = {
@ -150,7 +150,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
}
}
}
#endif // !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
void esp_deep_sleep_wakeup_io_reset(void)
{

2
components/esp_hw_support/sleep_modes.c
View File

@ -951,7 +951,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
}
#endif
if (deep_sleep) {
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
esp_sleep_isolate_digital_gpio();
#endif

5
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -468,6 +468,11 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
}
// On ESP32P4, all digital GPIO pads can be held together during Deep-sleep through PMU.hp_sys[PMU_MODE_HP_SLEEP].syscntl.hp_pad_hold_all = 1
// However, since the hold register for digital IOs is in TOP domain (HP_SYSTEM.gpio_o_hold_ctrlx), it gets powered down in Deep-sleep.
// Therefore, after waking up from Deep-sleep, the register has been reset, it is not able to hold at that time.
// In all, the users can not achieve the purpose of being hold all the time. So this feature is considered not usable on P4.
/**
* @brief Enable gpio pad hold function.
*

10
components/hal/include/hal/gpio_hal.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -291,7 +291,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
* e.g.
* If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called,
* gpio18 will output low level(because gpio18 is input mode by default). If you don't want this behavior,
* you should configure gpio18 as output mode and set it to hight level before calling `gpio_hold_dis`.
* you should configure gpio18 as output mode and set it to high level before calling `gpio_hold_dis`.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number, only support output GPIOs
@ -299,7 +299,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
#define gpio_hal_hold_dis(hal, gpio_num) gpio_ll_hold_dis((hal)->dev, gpio_num)
/**
* @brief Get wether digital gpio pad is held
* @brief Get whether digital gpio pad is held
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number, only support output GPIOs
@ -314,7 +314,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
*/
#define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num)
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Enable all digital gpio pad hold function during Deep-sleep.
*
@ -345,7 +345,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
* - false deep sleep hold is disabled
*/
#define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev)
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Set pad input to a peripheral signal through the IOMUX.

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@ -359,6 +359,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 2

3
components/soc/esp32/include/soc/soc_caps.h
View File

@ -193,6 +193,9 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32 has 2 I2C
#define SOC_I2C_NUM (2U)

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -327,6 +327,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32c2/include/soc/soc_caps.h
View File

@ -144,6 +144,9 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -419,6 +419,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -182,6 +182,9 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -487,6 +487,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -222,6 +222,8 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -515,6 +515,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -211,6 +211,8 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@ -247,6 +247,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32c61/include/soc/soc_caps.h
View File

@ -186,6 +186,8 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -519,6 +519,10 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -215,6 +215,8 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -659,10 +659,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 16

2
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -260,8 +260,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 16

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -407,6 +407,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

2
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -182,6 +182,8 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -483,6 +483,10 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -190,6 +190,9 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */