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feat(cache): supported cache panic on c61

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This commit is contained in:
Armando 2024-08-05 15:03:10 +08:00
parent 190ea15839
commit 7231a6388b
3 changed files with 28 additions and 17 deletions
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4
components/esp_system/port/soc/esp32c61/cache_err_int.c
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@ -60,10 +60,12 @@ void esp_cache_err_int_init(void)
esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/* On the hardware side, start by clearing all the bits reponsible for cache access error */
/* On the hardware side, start by clearing all the bits responsible for cache access error */
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Then enable cache access error interrupts. */
cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Enable the fail tracer */
cache_ll_l1_enable_fail_tracer(0, true);
/* Enable the interrupts for cache error. */
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);

33
components/hal/esp32c61/include/hal/cache_ll.h
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@ -10,6 +10,7 @@
#include <stdbool.h>
#include "soc/cache_reg.h"
#include "soc/cache_struct.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
@ -23,9 +24,6 @@ extern "C" {
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
#define CACHE_LL_L1_ACCESS_EVENT_MASK (1<<4)
#define CACHE_LL_L1_ACCESS_EVENT_CACHE_FAIL (1<<4)
#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
@ -33,6 +31,9 @@ extern "C" {
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x1f)
/**
* @brief Check if Cache auto preload is enabled or not.
*
@ -289,45 +290,53 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
return valid;
}
/**
* Enable the Cache fail tracer
*
* @param cache_id cache ID
* @param en enable / disable
*/
static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
{
CACHE.trace_ena.l1_cache_trace_ena = en;
}
/*------------------------------------------------------------------------------
* Interrupt
*----------------------------------------------------------------------------*/
/**
* @brief Enable Cache access error interrupt
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param cache_id Cache ID
* @param mask Interrupt mask
*/
static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C61] IDF-9252 (inherit from C6)
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
CACHE.l1_cache_acs_fail_int_ena.val |= mask;
}
/**
* @brief Clear Cache access error interrupt status
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param cache_id Cache ID
* @param mask Interrupt mask
*/
static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C61] IDF-9252 (inherit from C6)
SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
CACHE.l1_cache_acs_fail_int_clr.val = mask;
}
/**
* @brief Get Cache access error interrupt status
*
* @param cache_id Cache ID, not used on C3. For compabitlity
* @param cache_id Cache ID
* @param mask Interrupt mask
*
* @return Status mask
*/
static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
{
// TODO: [ESP32C61] IDF-9252 (inherit from C6)
return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
return CACHE.l1_cache_acs_fail_int_st.val & mask;
}
#ifdef __cplusplus

8
tools/test_apps/system/panic/pytest_panic.py
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@ -299,14 +299,14 @@ def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> Non
if dut.target in ['esp32c3', 'esp32c2']:
dut.expect_gme('Cache error')
dut.expect_exact('Cached memory region accessed while ibus or cache is disabled')
elif dut.target in ['esp32c6', 'esp32h2', 'esp32p4']:
dut.expect_gme('Cache error')
dut.expect_exact('Cache access error')
elif dut.target in ['esp32s2']:
# Cache error interrupt is not enabled, IDF-1558
dut.expect_gme('IllegalInstruction')
else:
elif dut.target in ['esp32', 'esp32s3']:
dut.expect_gme('Cache disabled but cached memory region accessed')
else:
dut.expect_gme('Cache error')
dut.expect_exact('Cache access error')
dut.expect_reg_dump(0)
if dut.is_xtensa:
dut.expect_backtrace()