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Merge branch 'fix/fix_c5_p4_c6_cache_disable_with_brc_predict_issue' into 'master'

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cache: fixed double exception after cache disabled caused by branch predictor

Closes IDFCI-2318 and IDF-10783

See merge request espressif/esp-idf!32828
This commit is contained in:
Armando (Dou Yiwen) 2024-08-16 10:24:05 +08:00
commit f6ec756b8e
3 changed files with 27 additions and 4 deletions
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8
components/esp_hw_support/include/esp_cpu.h
View File

@ -578,6 +578,14 @@ FORCE_INLINE_ATTR void esp_cpu_branch_prediction_enable(void)
{
rv_utils_en_branch_predictor();
}
/**
* @brief Disable branch prediction
*/
FORCE_INLINE_ATTR void esp_cpu_branch_prediction_disable(void)
{
rv_utils_dis_branch_predictor();
}
#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
#ifdef __cplusplus

16
components/riscv/include/riscv/rv_utils.h
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@ -27,6 +27,13 @@ extern "C" {
#define CSR_PCCR_MACHINE 0x7e2
#endif /* SOC_CPU_HAS_CSR_PC */
#if SOC_BRANCH_PREDICTOR_SUPPORTED
#define MHCR 0x7c1
#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
#endif //SOC_BRANCH_PREDICTOR_SUPPORTED
#if SOC_CPU_HAS_FPU
/* FPU bits in mstatus start at bit 13 */
@ -363,12 +370,13 @@ FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_
#if SOC_BRANCH_PREDICTOR_SUPPORTED
FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
{
#define MHCR 0x7c1
#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
}
FORCE_INLINE_ATTR void rv_utils_dis_branch_predictor(void)
{
RV_CLEAR_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
}
#endif
#ifdef __cplusplus

7
components/spi_flash/cache_utils.c
View File

@ -371,12 +371,19 @@ void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{
#if SOC_BRANCH_PREDICTOR_SUPPORTED
//branch predictor will start cache request as well
esp_cpu_branch_prediction_disable();
#endif
cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}
void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
{
cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
#if SOC_BRANCH_PREDICTOR_SUPPORTED
esp_cpu_branch_prediction_enable();
#endif
}
bool IRAM_ATTR spi_flash_cache_enabled(void)