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Merge branch 'ci/fix_esp32_exceed_bootloader_size' into 'master'

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fix(ci): esp32 build failure due to bootloader size too large

Closes IDFCI-2331

See merge request espressif/esp-idf!32926
This commit is contained in:
Armando (Dou Yiwen) 2024-08-20 09:20:18 +08:00
commit c01ccd1f62
3 changed files with 25 additions and 25 deletions
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36
components/bootloader_support/src/esp32/bootloader_esp32.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -69,11 +69,11 @@ static void bootloader_reset_mmu(void)
}
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
static esp_err_t bootloader_check_rated_cpu_clock(void)
static inline esp_err_t bootloader_check_rated_cpu_clock(void)
{
int rated_freq = bootloader_clock_get_rated_freq_mhz();
if (rated_freq < CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) {
ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig",
ESP_LOGE(TAG, "Chip CPU freq rated for %dMHz, configured for %dMHz. Modify CPU freq in menuconfig",
rated_freq, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
return ESP_FAIL;
}
@ -119,19 +119,19 @@ static void wdt_reset_info_dump(int cpu)
if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
ESP_LOGW(TAG, "WDT rst info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
} else {
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
ESP_LOGW(TAG, "WDT rst info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
}
ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
ESP_LOGD(TAG, "WDT rst info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
ESP_LOGD(TAG, "WDT rst info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
}
static void bootloader_check_wdt_reset(void)
@ -143,12 +143,12 @@ static void bootloader_check_wdt_reset(void)
rst_reas[1] = esp_rom_get_reset_reason(1);
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
ESP_LOGW(TAG, "PRO CPU has been reset by WDT");
wdt_rst = 1;
}
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
ESP_LOGW(TAG, "APP CPU has been reset by WDT");
wdt_rst = 1;
}
if (wdt_rst) {
@ -215,7 +215,7 @@ esp_err_t bootloader_init(void)
bootloader_flash_update_id();
// Check and run XMC startup flow
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
ESP_LOGE(TAG, "XMC startup flow failed, reboot!");
return ret;
}
// read bootloader header
@ -232,7 +232,7 @@ esp_err_t bootloader_init(void)
}
#endif // #if !CONFIG_APP_BUILD_TYPE_RAM
// check whether a WDT reset happend
// check whether a WDT reset happened
bootloader_check_wdt_reset();
// config WDT
bootloader_config_wdt();

12
components/esp_hw_support/port/esp32/rtc_clk_init.c
View File

@ -81,7 +81,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
/* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
xtal_freq = rtc_clk_xtal_freq_estimate();
if (xtal_freq == SOC_XTAL_FREQ_AUTO) {
ESP_HW_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
ESP_HW_LOGW(TAG, "Can't estimate XTAL freq, assuming 26MHz");
xtal_freq = SOC_XTAL_FREQ_26M;
}
}
@ -93,7 +93,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
soc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
if (est_xtal_freq != configured_xtal_freq) {
ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_XTAL_FREQ setting (%dMHz). Detected %dMHz.",
configured_xtal_freq, est_xtal_freq);
}
}
@ -108,7 +108,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
if (!res) {
ESP_HW_LOGE(TAG, "invalid CPU frequency value");
ESP_HW_LOGE(TAG, "invalid CPU freq value");
abort();
}
rtc_clk_cpu_freq_set_config(&new_config);
@ -163,18 +163,18 @@ static soc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
xtal_freq = SOC_XTAL_FREQ_26M;
break;
case 32 ... 33:
ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 26 MHz", freq_mhz);
ESP_HW_LOGW(TAG, "Potential bogus XTAL freq: %"PRIu32"MHz, guessing 26MHz", freq_mhz);
xtal_freq = SOC_XTAL_FREQ_26M;
break;
case 34 ... 35:
ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 40 MHz", freq_mhz);
ESP_HW_LOGW(TAG, "Potential bogus XTAL freq: %"PRIu32"MHz, guessing 40MHz", freq_mhz);
xtal_freq = SOC_XTAL_FREQ_40M;
break;
case 36 ... 45:
xtal_freq = SOC_XTAL_FREQ_40M;
break;
default:
ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %"PRIu32" MHz", freq_mhz);
ESP_HW_LOGW(TAG, "Bogus XTAL freq: %"PRIu32"MHz", freq_mhz);
xtal_freq = SOC_XTAL_FREQ_AUTO;
break;
}

2
components/esp_rom/patches/esp_rom_gpio.c
View File

@ -12,7 +12,7 @@
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
// On such targets, the ROM code for this function enabled output for the pad first, and then connected the signal
// This could result in an undesired glitch at the pad
IRAM_ATTR void esp_rom_gpio_connect_out_signal(uint32_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv)
IRAM_ATTR __attribute__((optimize("-Os"))) void esp_rom_gpio_connect_out_signal(uint32_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv)
{
uint32_t value = signal_idx << GPIO_FUNC0_OUT_SEL_S;
if (out_inv) {