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https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feat: remove support for aes and rsa peripherals in esp32c61
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@ -106,6 +106,9 @@ __attribute__((weak)) void esp_clk_init(void)
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// Re calculate the ccount to make time calculation correct.
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esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
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// Set crypto clock (`clk_sec`) to use 480M SPLL clock
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REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2);
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}
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -16,7 +16,6 @@
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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static SemaphoreHandle_t done_sem;
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static const unsigned char *one_hundred_bs = (unsigned char *)
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@ -77,11 +76,11 @@ static void tskRunAES256Test(void *pvParameters)
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memcpy(nonce, iv, 16);
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// allocate internal memory
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uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
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uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
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uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
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uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
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TEST_ASSERT_NOT_NULL(chipertext);
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TEST_ASSERT_NOT_NULL(ciphertext);
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TEST_ASSERT_NOT_NULL(plaintext);
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TEST_ASSERT_NOT_NULL(decryptedtext);
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@ -92,19 +91,19 @@ static void tskRunAES256Test(void *pvParameters)
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memset(decryptedtext, 0x0, SZ);
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// Encrypt
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mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
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mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
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// Decrypt
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memcpy(nonce, iv, 16);
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mbedtls_aes_setkey_dec(&ctx, key_256, 256);
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mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext);
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mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
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mbedtls_aes_free(&ctx);
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free(plaintext);
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free(chipertext);
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free(ciphertext);
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free(decryptedtext);
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}
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xSemaphoreGive(done_sem);
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@ -1,6 +1,6 @@
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/* mbedTLS bignum (MPI) self-tests as unit tests
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*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -17,6 +17,12 @@
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#include "sdkconfig.h"
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#include "test_utils.h"
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#ifdef SOC_MPI_SUPPORTED
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#define RSA_MAX_BIT_LEN SOC_RSA_MAX_BIT_LEN
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#else
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#define RSA_MAX_BIT_LEN 3072
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#endif
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#define MBEDTLS_OK 0
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/* Debugging function to print an MPI number to stdout. Happens to
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@ -54,7 +60,7 @@ static void test_bignum_mult_variant(const char *a_str, const char *b_str, const
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TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&A, 16, a_str));
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TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&B, 16, b_str));
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/* calulate X = A * B variant */
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/* calculate X = A * B variant */
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TEST_ASSERT_FALSE(mbedtls_mpi_read_string(&E, 16, e_str));
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if (res_operands_overlap == 0) {
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TEST_ASSERT_FALSE(mbedtls_mpi_mul_mpi(&X, &A, &B));
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@ -72,7 +78,7 @@ static void test_bignum_mult_variant(const char *a_str, const char *b_str, const
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#ifdef CONFIG_MBEDTLS_HARDWARE_MPI
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mbedtls_mpi M;
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/* if mod_bits arg is set, also do a esp_mpi_mul_mod() call */
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if (mod_bits > 0 && mod_bits <= SOC_RSA_MAX_BIT_LEN) {
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if (mod_bits > 0 && mod_bits <= RSA_MAX_BIT_LEN) {
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mbedtls_mpi_init(&M);
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for(int i = 0; i < mod_bits; i++) {
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mbedtls_mpi_set_bit(&M, i, 1);
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@ -106,7 +112,7 @@ TEST_CASE("test MPI multiplication", "[bignum]")
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/* Run some trivial numbers tests w/ various high modulo bit counts,
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should make no difference to the result
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*/
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for(int i = 512; i <= SOC_RSA_MAX_BIT_LEN; i+= 512) {
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for(int i = 512; i <= RSA_MAX_BIT_LEN; i+= 512) {
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test_bignum_mult("10", "100", "1000",
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i);
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -249,7 +249,7 @@ TEST_CASE("mbedtls SHA384 clone", "[mbedtls]")
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TEST_ASSERT_EQUAL(0, mbedtls_sha512_update(&ctx, one_hundred_bs, 100));
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TEST_ASSERT_EQUAL(0, mbedtls_sha512_update(&clone, one_hundred_bs, 100));
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}
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/* intended warning supression: is384 == true */
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/* intended warning suppression: is384 == true */
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wstringop-overflow"
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TEST_ASSERT_EQUAL(0, mbedtls_sha512_finish(&ctx, sha384));
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@ -435,10 +435,6 @@ config SOC_RTCIO_PIN_COUNT
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int
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default 0
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config SOC_RSA_MAX_BIT_LEN
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int
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default 3072
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config SOC_SHA_SUPPORT_RESUME
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bool
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default y
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@ -196,9 +196,6 @@
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* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
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#define SOC_RTCIO_PIN_COUNT (0U)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Due to very limited availability of the DMA channels, DMA support for the SHA peripheral is disabled */
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@ -71,22 +71,6 @@ config SOC_XTAL_SUPPORT_40M
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bool
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default y
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config SOC_AES_SUPPORT_DMA
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bool
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default y
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config SOC_AES_GDMA
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bool
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default y
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config SOC_AES_SUPPORT_AES_128
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bool
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default y
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config SOC_AES_SUPPORT_AES_256
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bool
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default y
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config SOC_ADC_PERIPH_NUM
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int
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default 1
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@ -283,18 +267,6 @@ config SOC_MPU_REGION_WO_SUPPORTED
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bool
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default n
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config SOC_MPI_MEM_BLOCKS_NUM
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int
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default 4
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config SOC_MPI_OPERATIONS_NUM
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int
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default 3
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config SOC_RSA_MAX_BIT_LEN
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int
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default 3072
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config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
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bool
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default y
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@ -41,7 +41,6 @@
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// \#define SOC_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9296, IDF-9297
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#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9307, IDF-9308
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// \#define SOC_SUPPORT_COEXISTENCE 1
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// \#define SOC_MPI_SUPPORTED 1
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// \#define SOC_SHA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9234
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#define SOC_ECC_SUPPORTED 1
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#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
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@ -64,7 +63,6 @@
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// \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336
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// \#define SOC_ETM_SUPPORTED 0
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// \#define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331
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// \#define SOC_AES_SUPPORTED 0 //TODO: [ESP32C61] IDF-9328
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// \#define SOC_SDIO_SLAVE_SUPPORTED 0
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// \#define SOC_PAU_SUPPORTED 0
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// \#define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337
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@ -73,15 +71,6 @@
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_40M 1
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_AES_GDMA (1)
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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//TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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@ -279,14 +268,6 @@
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/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
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// \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
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/*--------------------------- MPI CAPS ---------------------------------------*/
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#define SOC_MPI_MEM_BLOCKS_NUM (4)
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#define SOC_MPI_OPERATIONS_NUM (3)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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//TODO: [ESP32C61] IDF-9326
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#define SOC_RSA_MAX_BIT_LEN (3072)
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// TODO: IDF-5353 (Copy from esp32c3, need check)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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