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https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/riscv_task_wdt_cleanup' into 'master'
fix(wdt): changed register dump on task WDT to be more descriptive Closes IDFGH-13506 See merge request espressif/esp-idf!32947
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commit
766f1f2308
@ -0,0 +1,30 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ARCH_XTENSA
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#include "xtensa_context.h"
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#elif CONFIG_IDF_TARGET_ARCH_RISCV
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#include "riscv/rvruntime-frames.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if CONFIG_IDF_TARGET_ARCH_XTENSA
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typedef XtExcFrame esp_cpu_frame_t;
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#elif CONFIG_IDF_TARGET_ARCH_RISCV
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typedef RvExcFrame esp_cpu_frame_t;
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -86,6 +86,8 @@ void panic_set_address(void *frame, uint32_t addr);
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uint32_t panic_get_cause(const void* frame);
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void panic_prepare_frame_from_ctx(void* frame);
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#ifdef __cplusplus
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}
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#endif
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@ -4,13 +4,16 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_debug_helpers.h"
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#include "esp_private/panic_reason.h"
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#include "esp_private/panic_internal.h"
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_private/freertos_debug.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "riscv/rvruntime-frames.h"
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#include "esp_private/esp_cpu_internal.h"
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#include <string.h>
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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#include "esp_private/eh_frame_parser.h"
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@ -47,12 +50,17 @@ esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
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void *frame = snapshot.pxTopOfStack;
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esp_cpu_frame_t backtrace_frame = {};
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memcpy(&backtrace_frame, frame, sizeof(esp_cpu_frame_t));
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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esp_rom_printf("Print CPU %d (current core) backtrace\n", current_core);
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esp_eh_frame_print_backtrace(frame);
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esp_rom_printf("esp_backtrace_print: Print CPU %d (current core) backtrace\n", current_core);
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esp_eh_frame_print_backtrace(&frame);
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#else // CONFIG_ESP_SYSTEM_USE_EH_FRAME
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esp_rom_printf("Print CPU %d (current core) registers\n", current_core);
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panic_print_registers(frame, current_core);
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esp_rom_printf("esp_backtrace_print: Print CPU %d (current core) registers\n", current_core);
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panic_prepare_frame_from_ctx(&backtrace_frame);
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panic_print_registers(&backtrace_frame, current_core);
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esp_rom_printf("\r\n");
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#endif // CONFIG_ESP_SYSTEM_USE_EH_FRAME
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@ -350,3 +350,17 @@ void panic_set_address(void *f, uint32_t addr)
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{
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((RvExcFrame *)f)->mepc = addr;
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}
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void panic_prepare_frame_from_ctx(void* frame)
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{
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/* Cleanup the frame, status registers are not saved during context switches, so these will contain garbage
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values from the stack.
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*/
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((RvExcFrame *)frame)->mstatus = RV_READ_CSR(mstatus);
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((RvExcFrame *)frame)->mtvec = RV_READ_CSR(mtvec);
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((RvExcFrame *)frame)->mcause = MCAUSE_INVALID_VALUE;
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((RvExcFrame *)frame)->mtval = MCAUSE_INVALID_VALUE;
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((RvExcFrame *)frame)->mhartid = RV_READ_CSR(mhartid);
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}
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@ -479,3 +479,9 @@ void panic_print_backtrace(const void *f, int core)
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esp_backtrace_frame_t frame = {.pc = xt_frame->pc, .sp = xt_frame->a1, .next_pc = xt_frame->a0, .exc_frame = xt_frame};
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esp_backtrace_print_from_frame(100, &frame, true);
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}
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void panic_prepare_frame_from_ctx(void* frame)
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{
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/* Nothing to cleanup on xtensa */
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(void)frame;
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}
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@ -22,3 +22,4 @@
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#define MCAUSE_ILLIGAL_INSTRUCTION_ACCESS 1
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#define MCAUSE_ILLEGAL_INSTRUCTION 2
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#define MCAUSE_LOAD_ACCESS_FAULT 5
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#define MCAUSE_INVALID_VALUE 0xDEADC0DE // Frame mcause value was written by SW to indicate no useful info, e.g. during a register dump without a crash
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