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Merge branch 'fix/fix_cache_panic_c61_on_psram_board' into 'master'

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cache: fixed cache panic init flow on psram board

See merge request espressif/esp-idf!32701
This commit is contained in:
Armando (Dou Yiwen) 2024-08-13 14:08:17 +08:00
commit 11831cc0db
2 changed files with 16 additions and 10 deletions
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13
components/esp_system/port/soc/esp32c5/cache_err_int.c
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@ -61,12 +61,15 @@ void esp_cache_err_int_init(void)
esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/* On the hardware side, start by clearing all the bits responsible for cache access error */
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Then enable cache access error interrupts. */
cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Enable the fail tracer */
/**
* Here we
* 1. enable the cache fail tracer to take cache error interrupt into effect.
* 2. clear potential cache error interrupt raw bits
* 3. enable cache error interrupt en bits
*/
cache_ll_l1_enable_fail_tracer(0, true);
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Enable the interrupts for cache error. */
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);

13
components/esp_system/port/soc/esp32c61/cache_err_int.c
View File

@ -60,12 +60,15 @@ void esp_cache_err_int_init(void)
esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/* On the hardware side, start by clearing all the bits responsible for cache access error */
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Then enable cache access error interrupts. */
cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Enable the fail tracer */
/**
* Here we
* 1. enable the cache fail tracer to take cache error interrupt into effect.
* 2. clear potential cache error interrupt raw bits
* 3. enable cache error interrupt en bits
*/
cache_ll_l1_enable_fail_tracer(0, true);
cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
/* Enable the interrupts for cache error. */
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);