mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feat(isp_hist): Add ISP histogram support for esp32p4 (part1)
This commit is contained in:
C.S.M
gaoxu
parent
a263f833c9
commit
97acf99867
@ -14,7 +14,8 @@ if(CONFIG_SOC_ISP_SUPPORTED)
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"src/isp_ccm.c"
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"src/isp_awb.c"
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"src/isp_ae.c"
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"src/isp_gamma.c")
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"src/isp_gamma.c"
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"src/isp_hist.c")
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endif()
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if(CONFIG_SOC_ISP_BF_SUPPORTED)
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@ -18,3 +18,4 @@
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#include "driver/isp_bf.h"
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#include "driver/isp_ccm.h"
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#include "driver/isp_sharpen.h"
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#include "driver/isp_hist.h"
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194
components/esp_driver_isp/include/driver/isp_hist.h
Normal file
194
components/esp_driver_isp/include/driver/isp_hist.h
Normal file
@ -0,0 +1,194 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "driver/isp_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t first_window_x_offs; /*!< x offset for the first window */
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uint32_t window_x_size; /*!< x size for the window */
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uint32_t first_window_y_offs; /*!< y offset for the first window */
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uint32_t window_y_size; /*!< y size for the window */
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isp_hist_mode_enum_t hist_mode; /*!< ISP histogram mode */
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uint32_t hist_windows_weight[ISP_HIST_WINDOW_NUM]; /*!< Weight for histogram statistic windows */
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uint32_t hist_segment_threshold[ISP_HIST_INTERVAL_NUMS - 1]; /*!< threshold for histogram */
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isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficient for isp histogram */
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int intr_priority; /*!< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with
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* a relative low priority (1,2,3) */
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} esp_isp_hist_config_t;
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/**
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* @brief New an ISP hist controller
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*
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* @param[in] isp_proc ISP Processor handle
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* @param[in] hist_cfg Pointer to hist config. Refer to ``esp_isp_hist_config_t``.
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* @param[out] ret_hdl hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid
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* - ESP_ERR_INVALID_STATE Invalid state
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* - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
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* - ESP_ERR_NO_MEM If out of memory
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*/
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esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl);
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/**
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* @brief Delete an ISP hist controller
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*
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* @param[in] hist_ctlr hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Reconfigure the ISP histogram controller
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* @note This function is allowed to be called no matter the awb controller is enabled or not.
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] hist_cfg Pointer to histogram config. Refer to ``esp_isp_hist_config_t``
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid
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*/
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esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg);
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/**
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* @brief Enable an ISP hist controller
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*
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* @param[in] hist_ctlr hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Disable an ISP hist controller
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*
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* @param[in] hist_ctlr hist controller handle
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Trigger hist reference statistics for one time and get the result
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* @note This function is a synchronous and block function,
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* it only returns when hist reference statistics is done or timeout.
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* It's a simple method to get the result directly for one time.
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] timeout_ms Timeout in millisecond
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* - timeout_ms < 0: Won't return until finished
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* - timeout_ms = 0: No timeout, trigger one time statistics and return immediately,
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* in this case, the result won't be assigned in this function,
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* but you can get the result in the callback `esp_isp_hist_cbs_t::on_statistics_done`
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* - timeout_ms > 0: Wait for specified milliseconds, if not finished, then return timeout error
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* @param[out] out_res hist reference statistics result
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_TIMEOUT Wait for the result timeout
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid.
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res);
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/**
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* @brief Start hist continuous statistics of the reference in the window
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* @note This function is an asynchronous and non-block function,
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* it will start the continuous statistics and return immediately.
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* You have to register the hist callback and get the result from the callback event data.
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*
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* @param[in] hist_ctlr hist controller handle
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG Null pointer
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Stop hist continuous statistics of the reference in the window
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*
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* @param[in] hist_ctlr hist controller handle
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG Null pointer
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* - ESP_ERR_INVALID_STATE Driver state is invalid.
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*/
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esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Event data of callbacks
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*/
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typedef struct {
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isp_hist_result_t hist_result; /*!< The histogram reference statistics result */
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} esp_isp_hist_evt_data_t;
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/**
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* @brief Prototype of ISP hist event callback
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*
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* @param[in] handle ISP hist controller handle
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* @param[in] edata ISP hist event data
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* @param[in] user_data User registered context, registered when in `esp_isp_hist_env_detector_register_event_callbacks()`
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*
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* @return Whether a high priority task is woken up by this function
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*/
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typedef bool (*esp_isp_hist_callback_t)(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_evt_data_t *edata, void *user_data);
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/**
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* @brief Group of ISP hist callbacks
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*
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* @note These callbacks are all running in an ISR environment.
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* @note When CONFIG_ISP_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
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* Involved variables should be in internal RAM as well.
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*/
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typedef struct {
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esp_isp_hist_callback_t on_statistics_done; ///< Event callback, invoked when histogram statistic done.
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} esp_isp_hist_cbs_t;
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/**
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* @brief Register hist event callbacks
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*
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* @note User can deregister a previously registered callback by calling this function and setting the to-be-deregistered callback member in
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* the `cbs` structure to NULL.
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* @note When CONFIG_ISP_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
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* Involved variables (including `user_data`) should be in internal RAM as well.
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] cbs Group of callback functions
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* @param[in] user_data User data, which will be delivered to the callback functions directly
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*
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* @return
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* - ESP_OK: On success
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* - ESP_ERR_INVALID_ARG: Invalid arguments
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* - ESP_ERR_INVALID_STATE: Driver state is invalid, you shouldn't call this API at this moment
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*/
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esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data);
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#ifdef __cplusplus
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}
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#endif
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@ -76,6 +76,11 @@ typedef struct isp_awb_controller_t *isp_awb_ctlr_t;
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*/
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typedef struct isp_ae_controller_t *isp_ae_ctlr_t;
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/**
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* @brief Type of ISP HIST controller handle
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*/
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typedef struct isp_hist_controller_t *isp_hist_ctlr_t;
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/*---------------------------------------------
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Event Callbacks
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----------------------------------------------*/
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@ -68,6 +68,7 @@ typedef struct isp_processor_t {
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isp_af_ctlr_t af_ctlr[SOC_ISP_AF_CTLR_NUMS];
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isp_awb_ctlr_t awb_ctlr;
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isp_ae_ctlr_t ae_ctlr;
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isp_hist_ctlr_t hist_ctlr;
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isp_fsm_t bf_fsm;
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isp_fsm_t sharpen_fsm;
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esp_isp_evt_cbs_t cbs;
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282
components/esp_driver_isp/src/isp_hist.c
Normal file
282
components/esp_driver_isp/src/isp_hist.c
Normal file
@ -0,0 +1,282 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_types.h>
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#include <sys/lock.h>
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#include "freertos/FreeRTOS.h"
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_check.h"
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#include "esp_heap_caps.h"
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#include "driver/isp_hist.h"
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#include "esp_private/isp_private.h"
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typedef struct isp_hist_controller_t {
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isp_fsm_t fsm;
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portMUX_TYPE spinlock;
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intr_handle_t intr_handle;
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int intr_priority;
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isp_proc_handle_t isp_proc;
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QueueHandle_t evt_que;
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esp_isp_hist_cbs_t cbs;
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void *user_data;
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} isp_hist_controller_t;
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static const char *TAG = "ISP_hist";
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static void s_isp_hist_default_isr(void *arg);
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/*---------------------------------------------
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hist
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----------------------------------------------*/
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static esp_err_t s_isp_claim_hist_controller(isp_proc_handle_t isp_proc, isp_hist_ctlr_t hist_ctlr)
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{
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assert(isp_proc && hist_ctlr);
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bool found = false;
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portENTER_CRITICAL(&isp_proc->spinlock);
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if (!isp_proc->hist_ctlr) {
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isp_proc->hist_ctlr = hist_ctlr;
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found = true;
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}
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portEXIT_CRITICAL(&isp_proc->spinlock);
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if (!found) {
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return ESP_ERR_NOT_FOUND;
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}
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return ESP_OK;
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}
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static void s_isp_declaim_hist_controller(isp_hist_ctlr_t hist_ctlr)
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{
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if (hist_ctlr && hist_ctlr->isp_proc) {
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portENTER_CRITICAL(&hist_ctlr->isp_proc->spinlock);
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hist_ctlr->isp_proc->hist_ctlr = NULL;
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portEXIT_CRITICAL(&hist_ctlr->isp_proc->spinlock);
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}
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}
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static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr)
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{
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if (hist_ctlr) {
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if (hist_ctlr->intr_handle) {
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esp_intr_free(hist_ctlr->intr_handle);
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}
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if (hist_ctlr->evt_que) {
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vQueueDelete(hist_ctlr->evt_que);
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}
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free(hist_ctlr);
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}
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}
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esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl)
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{
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esp_err_t ret = ESP_FAIL;
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ESP_RETURN_ON_FALSE(isp_proc && hist_cfg && ret_hdl, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_hist_ctlr_t hist_ctlr = heap_caps_calloc(1, sizeof(isp_hist_controller_t), ISP_MEM_ALLOC_CAPS);
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ESP_RETURN_ON_FALSE(hist_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for hist controller");
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hist_ctlr->evt_que = xQueueCreateWithCaps(1, sizeof(isp_hist_result_t), ISP_MEM_ALLOC_CAPS);
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ESP_GOTO_ON_FALSE(hist_ctlr->evt_que, ESP_ERR_NO_MEM, err1, TAG, "no mem for hist event queue");
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hist_ctlr->fsm = ISP_FSM_INIT;
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hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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hist_ctlr->isp_proc = isp_proc;
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// Claim an hist controller
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ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller");
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// Register the hist ISR
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uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(isp_proc->hal.hw);
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int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 7 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED;
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ESP_GOTO_ON_ERROR(esp_intr_alloc_intrstatus(isp_hw_info.instances[isp_proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | intr_priority, intr_st_reg_addr, ISP_LL_EVENT_HIST_MASK,
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s_isp_hist_default_isr, hist_ctlr, &hist_ctlr->intr_handle), err2, TAG, "allocate interrupt failed");
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// Configure the hardware
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isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode);
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isp_ll_hist_set_x_offset(isp_proc->hal.hw, hist_cfg->first_window_x_offs);
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isp_ll_hist_set_y_offset(isp_proc->hal.hw, hist_cfg->first_window_y_offs);
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isp_ll_hist_set_window_x_size(isp_proc->hal.hw, hist_cfg->window_x_size);
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isp_ll_hist_set_window_y_size(isp_proc->hal.hw, hist_cfg->window_y_size);
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isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->hist_windows_weight);
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isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->hist_segment_threshold);
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if (hist_cfg->hist_mode == ISP_HIST_RGB) {
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isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient);
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}
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*ret_hdl = hist_ctlr;
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return ESP_OK;
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err2:
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s_isp_declaim_hist_controller(hist_ctlr);
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err1:
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s_isp_hist_free_controller(hist_ctlr);
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return ret;
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}
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esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->isp_proc->hist_ctlr == hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "controller isn't in use");
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ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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s_isp_declaim_hist_controller(hist_ctlr);
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s_isp_hist_free_controller(hist_ctlr);
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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esp_err_t ret = ESP_OK;
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ESP_GOTO_ON_ERROR(esp_intr_enable(hist_ctlr->intr_handle), err, TAG, "failed to enable the HIST interrupt");
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isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true);
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isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true);
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hist_ctlr->fsm = ISP_FSM_ENABLE;
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err:
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hist_ctlr->fsm = ISP_FSM_INIT;
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return ret;
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}
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esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
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isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false);
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isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false);
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esp_intr_disable(hist_ctlr->intr_handle);
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hist_ctlr->fsm = ISP_FSM_INIT;
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return ESP_OK;
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}
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|
||||
esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && hist_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 3 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED;
|
||||
ESP_RETURN_ON_FALSE(intr_priority == hist_ctlr->intr_priority, ESP_ERR_INVALID_ARG, TAG, "can't change interrupt priority after initialized");
|
||||
|
||||
// Configure the hardware
|
||||
isp_ll_hist_set_mode(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_mode);
|
||||
isp_ll_hist_set_x_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_x_offs);
|
||||
isp_ll_hist_set_y_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_y_offs);
|
||||
isp_ll_hist_set_window_x_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_x_size);
|
||||
isp_ll_hist_set_window_y_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_y_size);
|
||||
isp_ll_hist_set_subwindow_weight(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_windows_weight);
|
||||
isp_ll_hist_set_segment_threshold(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_segment_threshold);
|
||||
if (hist_cfg->hist_mode == ISP_HIST_RGB) {
|
||||
isp_ll_hist_set_rgb_coefficient(hist_ctlr->isp_proc->hal.hw, &hist_cfg->rgb_coefficient);
|
||||
}
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr && (out_res || timeout_ms == 0), ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
|
||||
|
||||
esp_err_t ret = ESP_OK;
|
||||
TickType_t ticks = timeout_ms < 0 ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms);
|
||||
// Reset the queue in case receiving the legacy data in the queue
|
||||
xQueueReset(hist_ctlr->evt_que);
|
||||
// Start the histogram reference statistics and waiting it done
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
// Wait the statistics to finish and receive the result from the queue
|
||||
if ((ticks > 0) && xQueueReceive(hist_ctlr->evt_que, out_res, ticks) != pdTRUE) {
|
||||
ret = ESP_ERR_TIMEOUT;
|
||||
}
|
||||
// Stop the histogram reference statistics
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
|
||||
|
||||
hist_ctlr->fsm = ISP_FSM_START;
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_START, ESP_ERR_INVALID_STATE, TAG, "controller isn't in continuous state");
|
||||
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
hist_ctlr->fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR
|
||||
---------------------------------------------------------------*/
|
||||
static void IRAM_ATTR s_isp_hist_default_isr(void *arg)
|
||||
{
|
||||
isp_hist_ctlr_t hist_ctlr = (isp_hist_ctlr_t)arg;
|
||||
isp_proc_handle_t proc = hist_ctlr->isp_proc;
|
||||
|
||||
uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK);
|
||||
|
||||
bool need_yield = false;
|
||||
|
||||
if (hist_events & ISP_LL_EVENT_HIST_MASK) {
|
||||
isp_hist_ctlr_t hist_ctlr = proc->hist_ctlr;
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS];
|
||||
isp_ll_hist_get_histogram_value(proc->hal.hw, hist_value);
|
||||
// Get the statistics result
|
||||
esp_isp_hist_evt_data_t edata = {};
|
||||
for (int i = 0; i < ISP_HIST_SEGMENT_NUMS; i++) {
|
||||
edata.hist_result.hist_value[i] = hist_value[i];
|
||||
}
|
||||
// Invoke the callback if the callback is registered
|
||||
if (hist_ctlr->cbs.on_statistics_done) {
|
||||
need_yield |= hist_ctlr->cbs.on_statistics_done(hist_ctlr, &edata, hist_ctlr->user_data);
|
||||
}
|
||||
BaseType_t high_task_awake = false;
|
||||
// Send the event data to the queue, overwrite the legacy one if exist
|
||||
xQueueOverwriteFromISR(hist_ctlr->evt_que, &edata.hist_result, &high_task_awake);
|
||||
need_yield |= high_task_awake == pdTRUE;
|
||||
/* If started continuous sampling, then trigger the next hist sample */
|
||||
if (hist_ctlr->fsm == ISP_FSM_START) {
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
}
|
||||
}
|
||||
|
||||
if (need_yield) {
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "detector isn't in the init state");
|
||||
#if CONFIG_ISP_ISR_IRAM_SAFE
|
||||
if (cbs->on_statistics_done) {
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_env_change callback not in IRAM");
|
||||
}
|
||||
if (user_data) {
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
|
||||
}
|
||||
#endif
|
||||
hist_ctlr->cbs.on_statistics_done = cbs->on_statistics_done;
|
||||
hist_ctlr->user_data = user_data;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -68,6 +68,7 @@ extern "C" {
|
||||
#define ISP_LL_EVENT_AE_MASK (ISP_LL_EVENT_AE_FDONE | ISP_LL_EVENT_AE_ENV)
|
||||
#define ISP_LL_EVENT_AWB_MASK (ISP_LL_EVENT_AWB_FDONE)
|
||||
#define ISP_LL_EVENT_SHARP_MASK (ISP_LL_EVENT_SHARP_FRAME)
|
||||
#define ISP_LL_EVENT_HIST_MASK (ISP_LL_EVENT_HIST_FDONE)
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
AF
|
||||
@ -1614,6 +1615,200 @@ static inline void isp_ll_gamma_set_correction_curve(isp_dev_t *hw, color_compon
|
||||
while (hw->gamma_ctrl.gamma_update);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief enable histogram clock
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] enable true: enable the clock. false: disable the clock
|
||||
*/
|
||||
static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->clk_en.clk_hist_force_on = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram subwindow weight
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] window_weight array for window weight
|
||||
*/
|
||||
static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_WINDOW_NUMS])
|
||||
{
|
||||
int idx = 0;
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_00, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_01, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_02, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_03, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_04, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_10, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_11, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_12, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_13, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_14, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_20, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_21, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_22, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_23, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_24, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_30, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_31, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_32, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_33, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_34, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_40, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_41, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_42, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_43, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight6, hist_weight_44, window_weight[idx++]);
|
||||
|
||||
HAL_ASSERT(idx == 25);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram segment threshold
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] segment_threshold array for segment threshold
|
||||
*/
|
||||
static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS - 1])
|
||||
{
|
||||
int idx = 0;
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_0_1, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_1_2, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_2_3, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_3_4, segment_threshold[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_4_5, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_5_6, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_6_7, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_7_8, segment_threshold[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_8_9, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_9_10, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_10_11, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_11_12, segment_threshold[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_12_13, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_13_14, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_14_15, segment_threshold[idx++]);
|
||||
|
||||
HAL_ASSERT(idx == 15);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram x offset
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] x_offset value for x offset
|
||||
*/
|
||||
static inline void isp_ll_hist_set_x_offset(isp_dev_t *hw, uint32_t x_offset)
|
||||
{
|
||||
hw->hist_offs.hist_x_offs = x_offset;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram y offset
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] y_offset value for y offset
|
||||
*/
|
||||
static inline void isp_ll_hist_set_y_offset(isp_dev_t *hw, uint32_t y_offset)
|
||||
{
|
||||
hw->hist_offs.hist_y_offs = y_offset;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram x size
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] x_size value for x size
|
||||
*/
|
||||
static inline void isp_ll_hist_set_window_x_size(isp_dev_t *hw, uint32_t x_size)
|
||||
{
|
||||
hw->hist_size.hist_x_size = x_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram y size
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] y_size value for y size
|
||||
*/
|
||||
static inline void isp_ll_hist_set_window_y_size(isp_dev_t *hw, uint32_t y_size)
|
||||
{
|
||||
hw->hist_size.hist_y_size = y_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start histogram statistic
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] enable enable/disable
|
||||
*/
|
||||
static inline void isp_ll_hist_enable(isp_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->cntl.hist_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop histogram statistic
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
*/
|
||||
static inline void isp_ll_hist_stop(isp_dev_t *hw)
|
||||
{
|
||||
hw->cntl.hist_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[out] histogram_value pointer to histogram result
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void isp_ll_hist_get_histogram_value(isp_dev_t *hw, uint32_t *histogram_value)
|
||||
{
|
||||
for (int i = 0; i < SOC_ISP_HIST_SEGMENT_NUMS; i++) {
|
||||
histogram_value[i] = hw->hist_binn[i].hist_bin_n;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[out] histogram_value pointer to histogram result
|
||||
*/
|
||||
static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_mode_enum_t hist_mode)
|
||||
{
|
||||
hw->hist_mode.hist_mode = hist_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[out] histogram_value pointer to histogram result
|
||||
*/
|
||||
static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient *rgb_coeff)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, rgb_coeff->coeff_r);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, rgb_coeff->coeff_g);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, rgb_coeff->coeff_b);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -235,6 +235,58 @@ typedef struct {
|
||||
} pt[ISP_GAMMA_CURVE_POINTS_NUM]; ///< Point (x, y)
|
||||
} isp_gamma_curve_points_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
#if SOC_ISP_HIST_WINDOW_NUMS
|
||||
#define ISP_HIST_WINDOW_NUM SOC_ISP_HIST_WINDOW_NUMS // The HIST window number for sampling
|
||||
#else
|
||||
#define ISP_HIST_WINDOW_NUM 0
|
||||
#endif
|
||||
|
||||
#if SOC_ISP_HIST_SEGMENT_NUMS
|
||||
#define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram
|
||||
#else
|
||||
#define ISP_HIST_SEGMENT_NUMS 0
|
||||
#endif
|
||||
|
||||
#if SOC_ISP_HIST_INTERVAL_NUMS
|
||||
#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The segment of histogram
|
||||
#else
|
||||
#define ISP_HIST_INTERVAL_NUMS 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ISP histogram mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ISP_HIST_RGB_B, ///< histogram mode for B component for RGB
|
||||
ISP_HIST_RGB_GB, ///< histogram mode for GB component for RGB
|
||||
ISP_HIST_RGB_GR, ///< histogram mode for GR component for RGB
|
||||
ISP_HIST_RGB_R, ///< histogram mode for R component for RGB
|
||||
ISP_HIST_RGB, ///< histogram mode for RGB
|
||||
ISP_HIST_YUV_Y, ///< histogram mode for Y component for YUV
|
||||
ISP_HIST_YUV_U, ///< histogram mode for U component for YUV
|
||||
ISP_HIST_YUV_V, ///< histogram mode for V component for YUV
|
||||
} isp_hist_mode_enum_t;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram r,g,b coefficient
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t coeff_r; ///< R coefficient
|
||||
uint8_t coeff_g; ///< G coefficient
|
||||
uint8_t coeff_b; ///< B coefficient
|
||||
} isp_hist_rgb_coefficient;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram result.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< histogram value.
|
||||
} isp_hist_result_t;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -923,6 +923,18 @@ config SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS
|
||||
int
|
||||
default 24
|
||||
|
||||
config SOC_ISP_HIST_WINDOW_NUMS
|
||||
int
|
||||
default 25
|
||||
|
||||
config SOC_ISP_HIST_SEGMENT_NUMS
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_ISP_HIST_INTERVAL_NUMS
|
||||
int
|
||||
default 15
|
||||
|
||||
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -2584,229 +2584,19 @@ typedef union {
|
||||
uint32_t val;
|
||||
} isp_blc_mean_reg_t;
|
||||
|
||||
/** Type of hist_bin0 register
|
||||
* result of histogram bin 0
|
||||
/** Type of hist_bin register
|
||||
* result of histogram bin n
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_0 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 0
|
||||
/** hist_bin_n : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin n
|
||||
*/
|
||||
uint32_t hist_bin_0:17;
|
||||
uint32_t hist_bin_n:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin0_reg_t;
|
||||
|
||||
/** Type of hist_bin1 register
|
||||
* result of histogram bin 1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_1 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 1
|
||||
*/
|
||||
uint32_t hist_bin_1:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin1_reg_t;
|
||||
|
||||
/** Type of hist_bin2 register
|
||||
* result of histogram bin 2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_2 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 2
|
||||
*/
|
||||
uint32_t hist_bin_2:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin2_reg_t;
|
||||
|
||||
/** Type of hist_bin3 register
|
||||
* result of histogram bin 3
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_3 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 3
|
||||
*/
|
||||
uint32_t hist_bin_3:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin3_reg_t;
|
||||
|
||||
/** Type of hist_bin4 register
|
||||
* result of histogram bin 4
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_4 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 4
|
||||
*/
|
||||
uint32_t hist_bin_4:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin4_reg_t;
|
||||
|
||||
/** Type of hist_bin5 register
|
||||
* result of histogram bin 5
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_5 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 5
|
||||
*/
|
||||
uint32_t hist_bin_5:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin5_reg_t;
|
||||
|
||||
/** Type of hist_bin6 register
|
||||
* result of histogram bin 6
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_6 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 6
|
||||
*/
|
||||
uint32_t hist_bin_6:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin6_reg_t;
|
||||
|
||||
/** Type of hist_bin7 register
|
||||
* result of histogram bin 7
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_7 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 7
|
||||
*/
|
||||
uint32_t hist_bin_7:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin7_reg_t;
|
||||
|
||||
/** Type of hist_bin8 register
|
||||
* result of histogram bin 8
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_8 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 8
|
||||
*/
|
||||
uint32_t hist_bin_8:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin8_reg_t;
|
||||
|
||||
/** Type of hist_bin9 register
|
||||
* result of histogram bin 9
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_9 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 9
|
||||
*/
|
||||
uint32_t hist_bin_9:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin9_reg_t;
|
||||
|
||||
/** Type of hist_bin10 register
|
||||
* result of histogram bin 10
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_10 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 10
|
||||
*/
|
||||
uint32_t hist_bin_10:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin10_reg_t;
|
||||
|
||||
/** Type of hist_bin11 register
|
||||
* result of histogram bin 11
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_11 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 11
|
||||
*/
|
||||
uint32_t hist_bin_11:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin11_reg_t;
|
||||
|
||||
/** Type of hist_bin12 register
|
||||
* result of histogram bin 12
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_12 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 12
|
||||
*/
|
||||
uint32_t hist_bin_12:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin12_reg_t;
|
||||
|
||||
/** Type of hist_bin13 register
|
||||
* result of histogram bin 13
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_13 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 13
|
||||
*/
|
||||
uint32_t hist_bin_13:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin13_reg_t;
|
||||
|
||||
/** Type of hist_bin14 register
|
||||
* result of histogram bin 14
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_14 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 14
|
||||
*/
|
||||
uint32_t hist_bin_14:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin14_reg_t;
|
||||
|
||||
/** Type of hist_bin15 register
|
||||
* result of histogram bin 15
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_bin_15 : RO; bitpos: [16:0]; default: 0;
|
||||
* this field represents result of histogram bin 15
|
||||
*/
|
||||
uint32_t hist_bin_15:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_bin15_reg_t;
|
||||
} isp_hist_binn_reg_t;
|
||||
|
||||
/** Type of rdn_eco_cs register
|
||||
* rdn eco cs register
|
||||
@ -3448,22 +3238,7 @@ typedef struct {
|
||||
volatile isp_hist_weight4_reg_t hist_weight4;
|
||||
volatile isp_hist_weight5_reg_t hist_weight5;
|
||||
volatile isp_hist_weight6_reg_t hist_weight6;
|
||||
volatile isp_hist_bin0_reg_t hist_bin0;
|
||||
volatile isp_hist_bin1_reg_t hist_bin1;
|
||||
volatile isp_hist_bin2_reg_t hist_bin2;
|
||||
volatile isp_hist_bin3_reg_t hist_bin3;
|
||||
volatile isp_hist_bin4_reg_t hist_bin4;
|
||||
volatile isp_hist_bin5_reg_t hist_bin5;
|
||||
volatile isp_hist_bin6_reg_t hist_bin6;
|
||||
volatile isp_hist_bin7_reg_t hist_bin7;
|
||||
volatile isp_hist_bin8_reg_t hist_bin8;
|
||||
volatile isp_hist_bin9_reg_t hist_bin9;
|
||||
volatile isp_hist_bin10_reg_t hist_bin10;
|
||||
volatile isp_hist_bin11_reg_t hist_bin11;
|
||||
volatile isp_hist_bin12_reg_t hist_bin12;
|
||||
volatile isp_hist_bin13_reg_t hist_bin13;
|
||||
volatile isp_hist_bin14_reg_t hist_bin14;
|
||||
volatile isp_hist_bin15_reg_t hist_bin15;
|
||||
volatile isp_hist_binn_reg_t hist_binn[16];
|
||||
volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0;
|
||||
volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1;
|
||||
volatile isp_mem_aux_ctrl_2_reg_t mem_aux_ctrl_2;
|
||||
|
||||
@ -355,6 +355,9 @@
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24
|
||||
#define SOC_ISP_HIST_WINDOW_NUMS 25
|
||||
#define SOC_ISP_HIST_SEGMENT_NUMS 16
|
||||
#define SOC_ISP_HIST_INTERVAL_NUMS 15
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
|
||||
|
||||
@ -62,8 +62,9 @@ The ISP driver offers following services:
|
||||
- `Get AF statistics in one shot or continuous way <#isp-af-statistics>`__ - covers how to get AF statistics one-shot or continuously.
|
||||
- `Get AE statistics in one shot or continuous way <#isp-ae-statistics>`__ - covers how to get AE statistics one-shot or continuously.
|
||||
- `Get AWB statistics in one shot or continuous way <#isp-awb-statistics>`__ - covers how to get AWB white patches statistics one-shot or continuously.
|
||||
- `Enable BF function <#isp-bf>`__ - covers how to enable and configure BF function.
|
||||
- `Configure CCM <#isp-ccm-config>`__ - covers how to config the Color Correction Matrix.
|
||||
- `Get histogram statistics in one shot or continuous way <#isp-hist-statistics>`__ - covers how to get histogram statistics one-shot or continuously.
|
||||
- `Enable BF function <#isp_bf>`__ - covers how to enable and configure BF function.
|
||||
- `Configure CCM <#isp-ccm-config>`__ - covers how to configure the Color Correction Matrix.
|
||||
- `Enable Gamma Correction <#isp-gamma-correction>`__ - covers how to enable and configure gamma correction.
|
||||
- `Configure Sharpen <#isp-sharpen>`__ - covers how to config the Sharpen function.
|
||||
- `Register callback <#isp-callback>`__ - covers how to hook user specific code to ISP driver event callback function.
|
||||
@ -394,7 +395,64 @@ Note that if you want to use the continuous statistics, you need to register the
|
||||
/* Delete the awb controller and free the resources */
|
||||
ESP_ERROR_CHECK(esp_isp_del_awb_controller(awb_ctlr));
|
||||
|
||||
.. _isp-bf:
|
||||
.. _isp-hist:
|
||||
|
||||
ISP histogram Processor
|
||||
-----------------------
|
||||
|
||||
Before doing ISP histogram statistics, you need to enable the ISP histogram processor first, by calling :cpp:func:`esp_isp_hist_controller_enable`. This function:
|
||||
|
||||
* Switches the driver state from **init** to **enable**.
|
||||
|
||||
Calling :cpp:func:`esp_isp_hist_controller_disable` does the opposite, that is, put the driver back to the **init** state.
|
||||
|
||||
.. _isp-hist-statistics:
|
||||
|
||||
Histogram One-shot and Continuous Statistics
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Calling :cpp:func:`esp_isp_hist_controller_get_oneshot_statistics` to get oneshot histogram statistics result. You can take following code as reference.
|
||||
|
||||
Aside from the above oneshot API, the ISP histogram driver also provides a way to start histogram statistics continuously. Calling :cpp:func:`esp_isp_hist_controller_start_continuous_statistics` starts the continuous statistics and :cpp:func:`esp_isp_hist_controller_stop_continuous_statistics` stops it.
|
||||
|
||||
Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__
|
||||
|
||||
.. code:: c
|
||||
|
||||
static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data)
|
||||
{
|
||||
for(int i = 0; i < 16; i++) {
|
||||
esp_rom_printf(DRAM_STR("val %d is %x\n"), i, edata->hist_result.hist_value[i]); // get the histogram statistic value
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
isp_hist_ctlr_t hist_ctrlr = NULL;
|
||||
esp_isp_hist_config_t hist_cfg = {
|
||||
.first_window_x_offs = 0,
|
||||
.first_window_y_offs = 0,
|
||||
.window_x_size = 800 / 25,
|
||||
.window_y_size = 640 / 25,
|
||||
.rgb_coefficient = {
|
||||
.coeff_b = 85,
|
||||
.coeff_g = 85,
|
||||
.coeff_r = 85,
|
||||
},
|
||||
.hist_windows_weight = {[0 ... ISP_HIST_WINDOW_NUM - 1] = 10},
|
||||
.hist_segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_RGB,
|
||||
};
|
||||
|
||||
esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctrlr);
|
||||
esp_isp_hist_cbs_t hist_cbs = {
|
||||
.on_statistics_done = s_hist_scheme_on_statistics_done_callback,
|
||||
};
|
||||
|
||||
esp_isp_hist_register_event_callbacks(hist_ctrlr, &hist_cbs, hist_ctrlr);
|
||||
esp_isp_hist_controller_enable(hist_ctrlr);
|
||||
|
||||
|
||||
.. _isp_bf:
|
||||
|
||||
ISP BF Processor
|
||||
~~~~~~~~~~~~~~~~
|
||||
|
||||
Loading…
Reference in New Issue
Block a user