mirror of
https://github.com/espressif/esp-idf.git
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feat(isp_hist): Add ISP histogram support and add test for esp32p4(part 2)
This commit is contained in:
gaoxu
parent
97acf99867
commit
fb5df708a1
@ -30,7 +30,7 @@ typedef struct {
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bool has_line_end_packet; ///< Enable line end packet
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uint32_t h_res; ///< Input horizontal resolution, i.e. the number of pixels in a line
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uint32_t v_res; ///< Input vertical resolution, i.e. the number of lines in a frame
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int intr_priority; ///< The interrupt priority, range 0~3
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int intr_priority; ///< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3)
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} esp_isp_processor_cfg_t;
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/**
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@ -16,16 +16,13 @@ extern "C" {
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#endif
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typedef struct {
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uint32_t first_window_x_offs; /*!< x offset for the first window */
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uint32_t window_x_size; /*!< x size for the window */
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uint32_t first_window_y_offs; /*!< y offset for the first window */
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uint32_t window_y_size; /*!< y size for the window */
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isp_hist_mode_enum_t hist_mode; /*!< ISP histogram mode */
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uint32_t hist_windows_weight[ISP_HIST_WINDOW_NUM]; /*!< Weight for histogram statistic windows */
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uint32_t hist_segment_threshold[ISP_HIST_INTERVAL_NUMS - 1]; /*!< threshold for histogram */
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isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficient for isp histogram */
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int intr_priority; /*!< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with
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* a relative low priority (1,2,3) */
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isp_window_t window; /*!< The sampling window of histogram, see `isp_window_t`*/
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isp_hist_sampling_mode_t hist_mode; /*!< ISP histogram sampling mode */
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isp_hist_rgb_coefficient rgb_coefficient; /*!< RGB coefficients, adjust the sensitivity to red, geen, and blue colors in the image,
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only effect when hist_mode is ISP_HIST_SAMPLING_RGB, the sum of all coefficients should be 100**/
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uint32_t windows_weight[ISP_HIST_BLOCK_X_NUM][ISP_HIST_BLOCK_Y_NUM]; /*!< Weights of histogram's each subwindows, the sum of all subwindows's weight should be 100*/
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uint32_t segment_threshold[ISP_HIST_INTERVAL_NUMS]; /*!< Threshold to segment the histogram into intervals, range 0~256 */
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} esp_isp_hist_config_t;
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/**
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@ -56,19 +53,6 @@ esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_
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*/
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esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Reconfigure the ISP histogram controller
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* @note This function is allowed to be called no matter the awb controller is enabled or not.
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] hist_cfg Pointer to histogram config. Refer to ``esp_isp_hist_config_t``
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*
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* @return
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* - ESP_OK On success
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* - ESP_ERR_INVALID_ARG If the combination of arguments is invalid
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*/
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esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg);
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/**
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* @brief Enable an ISP hist controller
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*
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@ -95,9 +79,6 @@ esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr);
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/**
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* @brief Trigger hist reference statistics for one time and get the result
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* @note This function is a synchronous and block function,
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* it only returns when hist reference statistics is done or timeout.
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* It's a simple method to get the result directly for one time.
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*
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* @param[in] hist_ctlr hist controller handle
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* @param[in] timeout_ms Timeout in millisecond
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@ -153,7 +134,7 @@ typedef struct {
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*
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* @param[in] handle ISP hist controller handle
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* @param[in] edata ISP hist event data
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* @param[in] user_data User registered context, registered when in `esp_isp_hist_env_detector_register_event_callbacks()`
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* @param[in] user_data User registered context, registered when in `esp_isp_hist_register_event_callbacks()`
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*
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* @return Whether a high priority task is woken up by this function
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*/
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@ -83,6 +83,7 @@ typedef struct isp_processor_t {
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uint32_t ae_isr_added: 1;
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uint32_t awb_isr_added: 1;
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uint32_t sharp_isr_added: 1;
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uint32_t hist_isr_added: 1;
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} isr_users;
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} isp_processor_t;
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@ -93,6 +94,7 @@ typedef enum {
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ISP_SUBMODULE_AE,
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ISP_SUBMODULE_AWB,
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ISP_SUBMODULE_SHARPEN,
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ISP_SUBMODULE_HIST,
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} isp_submodule_t;
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/*---------------------------------------------------------------
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@ -104,6 +106,7 @@ bool esp_isp_af_isr(isp_proc_handle_t proc, uint32_t af_events);
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bool esp_isp_ae_isr(isp_proc_handle_t proc, uint32_t ae_events);
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bool esp_isp_awb_isr(isp_proc_handle_t proc, uint32_t awb_events);
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bool esp_isp_sharpen_isr(isp_proc_handle_t proc, uint32_t sharp_events);
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bool esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events);
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#ifdef __cplusplus
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}
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@ -231,6 +231,7 @@ static void IRAM_ATTR s_isp_isr_dispatcher(void *arg)
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uint32_t awb_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_AWB_MASK);
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uint32_t ae_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_AE_MASK);
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uint32_t sharp_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_SHARP_MASK);
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uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK);
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bool do_dispatch = false;
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//Deal with hw events
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@ -274,7 +275,16 @@ static void IRAM_ATTR s_isp_isr_dispatcher(void *arg)
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}
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do_dispatch = false;
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}
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if (hist_events) {
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portENTER_CRITICAL_ISR(&proc->spinlock);
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do_dispatch = proc->isr_users.hist_isr_added;
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portEXIT_CRITICAL_ISR(&proc->spinlock);
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if (do_dispatch) {
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need_yield |= esp_isp_hist_isr(proc, hist_events);
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}
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do_dispatch = false;
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}
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if (need_yield) {
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portYIELD_FROM_ISR();
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}
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@ -306,6 +316,9 @@ esp_err_t esp_isp_register_isr(isp_proc_handle_t proc, isp_submodule_t submodule
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case ISP_SUBMODULE_SHARPEN:
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proc->isr_users.sharp_isr_added = true;
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break;
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case ISP_SUBMODULE_HIST:
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proc->isr_users.hist_isr_added = true;
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break;
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default:
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assert(false);
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}
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@ -314,7 +327,7 @@ esp_err_t esp_isp_register_isr(isp_proc_handle_t proc, isp_submodule_t submodule
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if (do_alloc) {
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uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(proc->hal.hw);
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uint32_t intr_st_mask = ISP_LL_EVENT_AF_MASK | ISP_LL_EVENT_AE_MASK | ISP_LL_EVENT_AWB_MASK;
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uint32_t intr_st_mask = ISP_LL_EVENT_AF_MASK | ISP_LL_EVENT_AE_MASK | ISP_LL_EVENT_AWB_MASK | ISP_LL_EVENT_HIST_MASK;
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ret = esp_intr_alloc_intrstatus(isp_hw_info.instances[proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | proc->intr_priority, intr_st_reg_addr, intr_st_mask,
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s_isp_isr_dispatcher, (void *)proc, &proc->intr_hdl);
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if (ret != ESP_OK) {
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@ -354,6 +367,9 @@ esp_err_t esp_isp_deregister_isr(isp_proc_handle_t proc, isp_submodule_t submodu
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case ISP_SUBMODULE_SHARPEN:
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proc->isr_users.sharp_isr_added = false;
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break;
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case ISP_SUBMODULE_HIST:
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proc->isr_users.hist_isr_added = false;
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break;
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default:
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assert(false);
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}
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@ -6,6 +6,7 @@
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#include <esp_types.h>
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#include <sys/lock.h>
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#include <stdatomic.h>
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#include "freertos/FreeRTOS.h"
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#include "sdkconfig.h"
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#include "esp_log.h"
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@ -15,10 +16,9 @@
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#include "esp_private/isp_private.h"
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typedef struct isp_hist_controller_t {
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isp_fsm_t fsm;
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_Atomic isp_fsm_t fsm;
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portMUX_TYPE spinlock;
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intr_handle_t intr_handle;
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int intr_priority;
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isp_proc_handle_t isp_proc;
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QueueHandle_t evt_que;
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esp_isp_hist_cbs_t cbs;
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@ -27,8 +27,6 @@ typedef struct isp_hist_controller_t {
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static const char *TAG = "ISP_hist";
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static void s_isp_hist_default_isr(void *arg);
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/*---------------------------------------------
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hist
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----------------------------------------------*/
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@ -66,7 +64,7 @@ static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr)
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esp_intr_free(hist_ctlr->intr_handle);
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}
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if (hist_ctlr->evt_que) {
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vQueueDelete(hist_ctlr->evt_que);
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vQueueDeleteWithCaps(hist_ctlr->evt_que);
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}
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free(hist_ctlr);
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}
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@ -81,27 +79,43 @@ esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_
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ESP_RETURN_ON_FALSE(hist_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for hist controller");
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hist_ctlr->evt_que = xQueueCreateWithCaps(1, sizeof(isp_hist_result_t), ISP_MEM_ALLOC_CAPS);
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ESP_GOTO_ON_FALSE(hist_ctlr->evt_que, ESP_ERR_NO_MEM, err1, TAG, "no mem for hist event queue");
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atomic_init(&hist_ctlr->fsm, ISP_FSM_INIT);
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hist_ctlr->fsm = ISP_FSM_INIT;
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hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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hist_ctlr->isp_proc = isp_proc;
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for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) {
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ESP_GOTO_ON_FALSE((hist_cfg->segment_threshold[i] > 0 && hist_cfg->segment_threshold[i] < 256), ESP_ERR_INVALID_ARG, err1, TAG, "invalid segment threshold");
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}
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int weight_sum = 0;
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for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS; i++) {
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for (int j = 0; j < SOC_ISP_HIST_BLOCK_Y_NUMS; j++) {
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weight_sum = weight_sum + hist_cfg->windows_weight[i][j];
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}
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}
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ESP_GOTO_ON_FALSE(weight_sum == 100, ESP_ERR_INVALID_ARG, err1, TAG, "The sum of all subwindow's weight is not 100");
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if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) {
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int rgb_coefficient_sum = hist_cfg->rgb_coefficient.coeff_r + hist_cfg->rgb_coefficient.coeff_g + hist_cfg->rgb_coefficient.coeff_b;
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ESP_GOTO_ON_FALSE(rgb_coefficient_sum == 100, ESP_ERR_INVALID_ARG, err1, TAG, "The sum of rgb_coefficient is not 100");
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}
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// Claim an hist controller
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ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller");
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// Register the hist ISR
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uint32_t intr_st_reg_addr = isp_ll_get_intr_status_reg_addr(isp_proc->hal.hw);
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int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 7 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED;
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ESP_GOTO_ON_ERROR(esp_intr_alloc_intrstatus(isp_hw_info.instances[isp_proc->proc_id].irq, ISP_INTR_ALLOC_FLAGS | intr_priority, intr_st_reg_addr, ISP_LL_EVENT_HIST_MASK,
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s_isp_hist_default_isr, hist_ctlr, &hist_ctlr->intr_handle), err2, TAG, "allocate interrupt failed");
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// Register the HIGT ISR
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ESP_GOTO_ON_ERROR(esp_isp_register_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST), err2, TAG, "fail to register ISR");
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// Configure the hardware
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isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode);
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isp_ll_hist_set_x_offset(isp_proc->hal.hw, hist_cfg->first_window_x_offs);
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isp_ll_hist_set_y_offset(isp_proc->hal.hw, hist_cfg->first_window_y_offs);
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isp_ll_hist_set_window_x_size(isp_proc->hal.hw, hist_cfg->window_x_size);
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isp_ll_hist_set_window_y_size(isp_proc->hal.hw, hist_cfg->window_y_size);
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isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->hist_windows_weight);
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isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->hist_segment_threshold);
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if (hist_cfg->hist_mode == ISP_HIST_RGB) {
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isp_hal_hist_window_config(&isp_proc->hal, &hist_cfg->window);
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isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->windows_weight);
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isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->segment_threshold);
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if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) {
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isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient);
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}
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@ -121,9 +135,13 @@ esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->isp_proc->hist_ctlr == hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "controller isn't in use");
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ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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s_isp_declaim_hist_controller(hist_ctlr);
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ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
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// Deregister the HIST ISR
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ESP_RETURN_ON_FALSE(esp_isp_deregister_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST) == ESP_OK, ESP_FAIL, TAG, "fail to deregister ISR");
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s_isp_declaim_hist_controller(hist_ctlr);
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s_isp_hist_free_controller(hist_ctlr);
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return ESP_OK;
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@ -132,49 +150,28 @@ esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr)
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esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller isn't in init state");
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esp_err_t ret = ESP_OK;
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ESP_GOTO_ON_ERROR(esp_intr_enable(hist_ctlr->intr_handle), err, TAG, "failed to enable the HIST interrupt");
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isp_fsm_t expected_fsm = ISP_FSM_INIT;
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ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
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ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
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isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true);
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isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true);
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hist_ctlr->fsm = ISP_FSM_ENABLE;
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err:
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hist_ctlr->fsm = ISP_FSM_INIT;
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return ret;
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
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isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
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ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_INIT),
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ESP_ERR_INVALID_STATE, TAG, "controller not in enable state");
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isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false);
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isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false);
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esp_intr_disable(hist_ctlr->intr_handle);
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hist_ctlr->fsm = ISP_FSM_INIT;
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_config_t *hist_cfg)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_cfg, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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int intr_priority = hist_cfg->intr_priority > 0 && hist_cfg->intr_priority <= 3 ? BIT(hist_cfg->intr_priority) : ESP_INTR_FLAG_LOWMED;
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ESP_RETURN_ON_FALSE(intr_priority == hist_ctlr->intr_priority, ESP_ERR_INVALID_ARG, TAG, "can't change interrupt priority after initialized");
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// Configure the hardware
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isp_ll_hist_set_mode(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_mode);
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isp_ll_hist_set_x_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_x_offs);
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isp_ll_hist_set_y_offset(hist_ctlr->isp_proc->hal.hw, hist_cfg->first_window_y_offs);
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isp_ll_hist_set_window_x_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_x_size);
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isp_ll_hist_set_window_y_size(hist_ctlr->isp_proc->hal.hw, hist_cfg->window_y_size);
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isp_ll_hist_set_subwindow_weight(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_windows_weight);
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isp_ll_hist_set_segment_threshold(hist_ctlr->isp_proc->hal.hw, hist_cfg->hist_segment_threshold);
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if (hist_cfg->hist_mode == ISP_HIST_RGB) {
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isp_ll_hist_set_rgb_coefficient(hist_ctlr->isp_proc->hal.hw, &hist_cfg->rgb_coefficient);
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}
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return ESP_OK;
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}
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@ -182,10 +179,13 @@ esp_err_t esp_isp_hist_controller_reconfig(isp_hist_ctlr_t hist_ctlr, const esp_
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esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res)
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{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr && (out_res || timeout_ms == 0), ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
|
||||
|
||||
esp_err_t ret = ESP_OK;
|
||||
TickType_t ticks = timeout_ms < 0 ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms);
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ONESHOT), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet");
|
||||
|
||||
// Reset the queue in case receiving the legacy data in the queue
|
||||
xQueueReset(hist_ctlr->evt_que);
|
||||
// Start the histogram reference statistics and waiting it done
|
||||
@ -197,15 +197,16 @@ esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ct
|
||||
// Stop the histogram reference statistics
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
|
||||
atomic_store(&hist_ctlr->fsm, ISP_FSM_ENABLE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "controller isn't in enable state");
|
||||
|
||||
hist_ctlr->fsm = ISP_FSM_START;
|
||||
isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
|
||||
ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_CONTINUOUS), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet");
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
|
||||
return ESP_OK;
|
||||
@ -214,10 +215,11 @@ esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hi
|
||||
esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
ESP_RETURN_ON_FALSE_ISR(hist_ctlr->fsm == ISP_FSM_START, ESP_ERR_INVALID_STATE, TAG, "controller isn't in continuous state");
|
||||
|
||||
isp_fsm_t expected_fsm = ISP_FSM_CONTINUOUS;
|
||||
ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
|
||||
ESP_ERR_INVALID_STATE, TAG, "controller is not running");
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
hist_ctlr->fsm = ISP_FSM_ENABLE;
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -225,18 +227,14 @@ esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t his
|
||||
/*---------------------------------------------------------------
|
||||
INTR
|
||||
---------------------------------------------------------------*/
|
||||
static void IRAM_ATTR s_isp_hist_default_isr(void *arg)
|
||||
|
||||
bool IRAM_ATTR esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events)
|
||||
{
|
||||
isp_hist_ctlr_t hist_ctlr = (isp_hist_ctlr_t)arg;
|
||||
isp_proc_handle_t proc = hist_ctlr->isp_proc;
|
||||
|
||||
uint32_t hist_events = isp_hal_check_clear_intr_event(&proc->hal, ISP_LL_EVENT_HIST_MASK);
|
||||
|
||||
bool need_yield = false;
|
||||
|
||||
if (hist_events & ISP_LL_EVENT_HIST_MASK) {
|
||||
if (hist_events & ISP_LL_EVENT_HIST_FDONE) {
|
||||
isp_hist_ctlr_t hist_ctlr = proc->hist_ctlr;
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS];
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS] = {};
|
||||
isp_ll_hist_get_histogram_value(proc->hal.hw, hist_value);
|
||||
// Get the statistics result
|
||||
esp_isp_hist_evt_data_t edata = {};
|
||||
@ -251,25 +249,20 @@ static void IRAM_ATTR s_isp_hist_default_isr(void *arg)
|
||||
// Send the event data to the queue, overwrite the legacy one if exist
|
||||
xQueueOverwriteFromISR(hist_ctlr->evt_que, &edata.hist_result, &high_task_awake);
|
||||
need_yield |= high_task_awake == pdTRUE;
|
||||
/* If started continuous sampling, then trigger the next hist sample */
|
||||
if (hist_ctlr->fsm == ISP_FSM_START) {
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
|
||||
isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (need_yield) {
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
return need_yield;
|
||||
}
|
||||
|
||||
esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
|
||||
ESP_RETURN_ON_FALSE(hist_ctlr->fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "detector isn't in the init state");
|
||||
|
||||
ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
|
||||
#if CONFIG_ISP_ISR_IRAM_SAFE
|
||||
if (cbs->on_statistics_done) {
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_env_change callback not in IRAM");
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_statistics_done callback not in IRAM");
|
||||
}
|
||||
if (user_data) {
|
||||
ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
|
||||
|
||||
@ -327,3 +327,102 @@ TEST_CASE("ISP AE controller exhausted allocation", "[isp]")
|
||||
}
|
||||
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
|
||||
}
|
||||
|
||||
static bool test_isp_hist_default_on_statistics_done_cb(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_evt_data_t *edata, void *user_data)
|
||||
{
|
||||
(void) hist_ctlr;
|
||||
(void) edata;
|
||||
(void) user_data;
|
||||
// Do nothing
|
||||
return false;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
TEST_CASE("ISP HIST driver basic function", "[isp]")
|
||||
{
|
||||
esp_isp_processor_cfg_t isp_config = {
|
||||
.clk_hz = 80 * 1000 * 1000,
|
||||
.input_data_source = ISP_INPUT_DATA_SOURCE_CSI,
|
||||
.input_data_color_type = ISP_COLOR_RAW8,
|
||||
.output_data_color_type = ISP_COLOR_RGB565,
|
||||
};
|
||||
isp_proc_handle_t isp_proc = NULL;
|
||||
TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc));
|
||||
TEST_ESP_OK(esp_isp_enable(isp_proc));
|
||||
|
||||
isp_hist_ctlr_t hist_ctlr = NULL;
|
||||
isp_hist_result_t hist_res = {};
|
||||
|
||||
/* Test when sum of weight is not 256 */
|
||||
esp_isp_hist_config_t hist_config_error = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.windows_weight = {{5, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}},
|
||||
};
|
||||
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_isp_new_hist_controller(isp_proc, &hist_config_error, &hist_ctlr));
|
||||
|
||||
esp_isp_hist_config_t hist_config = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.rgb_coefficient.coeff_r = 33,
|
||||
.rgb_coefficient.coeff_g = 33,
|
||||
.rgb_coefficient.coeff_b = 34,
|
||||
.windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}},
|
||||
};
|
||||
TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr));
|
||||
|
||||
/* Register HIST callback */
|
||||
esp_isp_hist_cbs_t hist_cb = {
|
||||
.on_statistics_done = test_isp_hist_default_on_statistics_done_cb,
|
||||
};
|
||||
TEST_ESP_OK(esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cb, NULL));
|
||||
/* Enabled the hist controller */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_enable(hist_ctlr));
|
||||
/* Start continuous HIST statistics */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_start_continuous_statistics(hist_ctlr));
|
||||
TEST_ESP_ERR(ESP_ERR_INVALID_STATE, esp_isp_hist_controller_get_oneshot_statistics(hist_ctlr, 0, &hist_res));
|
||||
/* Stop continuous HIST statistics */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_stop_continuous_statistics(hist_ctlr));
|
||||
TEST_ESP_ERR(ESP_ERR_TIMEOUT, esp_isp_hist_controller_get_oneshot_statistics(hist_ctlr, 1, &hist_res));
|
||||
/* Disable the hist controller */
|
||||
TEST_ESP_OK(esp_isp_hist_controller_disable(hist_ctlr));
|
||||
/* Delete the hist controller and free the resources */
|
||||
TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr));
|
||||
|
||||
TEST_ESP_OK(esp_isp_disable(isp_proc));
|
||||
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
|
||||
}
|
||||
|
||||
TEST_CASE("ISP HIST controller exhausted allocation", "[isp]")
|
||||
{
|
||||
esp_isp_processor_cfg_t isp_config = {
|
||||
.clk_hz = 80 * 1000 * 1000,
|
||||
.input_data_source = ISP_INPUT_DATA_SOURCE_CSI,
|
||||
.input_data_color_type = ISP_COLOR_RAW8,
|
||||
.output_data_color_type = ISP_COLOR_RGB565,
|
||||
};
|
||||
isp_proc_handle_t isp_proc = NULL;
|
||||
TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc));
|
||||
|
||||
esp_isp_hist_config_t hist_config = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.rgb_coefficient.coeff_r = 33,
|
||||
.rgb_coefficient.coeff_g = 33,
|
||||
.rgb_coefficient.coeff_b = 34,
|
||||
.windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}},
|
||||
};
|
||||
|
||||
isp_hist_ctlr_t hist_ctlr[SOC_ISP_HIST_CTLR_NUMS + 1] = {};
|
||||
for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) {
|
||||
TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[i]));
|
||||
}
|
||||
|
||||
TEST_ASSERT(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[SOC_ISP_HIST_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
|
||||
|
||||
for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) {
|
||||
TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr[i]));
|
||||
}
|
||||
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
|
||||
}
|
||||
|
||||
@ -1635,43 +1635,13 @@ static inline void isp_ll_hist_clk_enable(isp_dev_t *hw, bool enable)
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] window_weight array for window weight
|
||||
*/
|
||||
static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_WINDOW_NUMS])
|
||||
static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_t window_weight[SOC_ISP_HIST_BLOCK_X_NUMS][SOC_ISP_HIST_BLOCK_Y_NUMS])
|
||||
{
|
||||
int idx = 0;
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_00, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_01, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_02, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight0, hist_weight_03, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_04, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_10, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_11, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight1, hist_weight_12, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_13, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_14, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_20, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight2, hist_weight_21, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_22, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_23, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_24, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight3, hist_weight_30, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_31, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_32, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_33, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight4, hist_weight_34, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_40, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_41, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_42, window_weight[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight5, hist_weight_43, window_weight[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_weight6, hist_weight_44, window_weight[idx++]);
|
||||
|
||||
HAL_ASSERT(idx == 25);
|
||||
for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS; i++) {
|
||||
for (int j = 0; j < SOC_ISP_HIST_BLOCK_Y_NUMS; j++) {
|
||||
hw->hist_weight[i / 4].hist_weight_b[3 - (i % 4)] = (window_weight[i][j] * 256) / 100;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1680,78 +1650,33 @@ static inline void isp_ll_hist_set_subwindow_weight(isp_dev_t *hw, const uint32_
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] segment_threshold array for segment threshold
|
||||
*/
|
||||
static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS - 1])
|
||||
static inline void isp_ll_hist_set_segment_threshold(isp_dev_t *hw, const uint32_t segment_threshold[SOC_ISP_HIST_INTERVAL_NUMS])
|
||||
{
|
||||
int idx = 0;
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_0_1, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_1_2, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_2_3, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg0, hist_seg_3_4, segment_threshold[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_4_5, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_5_6, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_6_7, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg1, hist_seg_7_8, segment_threshold[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_8_9, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_9_10, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_10_11, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg2, hist_seg_11_12, segment_threshold[idx++]);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_12_13, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_13_14, segment_threshold[idx++]);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg3, hist_seg_14_15, segment_threshold[idx++]);
|
||||
|
||||
HAL_ASSERT(idx == 15);
|
||||
for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_seg[i / 4], hist_seg_b[3 - (i % 4)], segment_threshold[i])
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram x offset
|
||||
* @brief Set histogram window range
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] x_offset value for x offset
|
||||
*/
|
||||
static inline void isp_ll_hist_set_x_offset(isp_dev_t *hw, uint32_t x_offset)
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] x_start Top left pixel x axis value
|
||||
* @param[in] x_bsize Block size on x axis
|
||||
* @param[in] y_start Top left pixel y axis value
|
||||
* @param[in] y_bsize Block size on y axis
|
||||
*/
|
||||
static inline void isp_ll_hist_set_window_range(isp_dev_t *hw, int x_start, int x_bsize, int y_start, int y_bsize)
|
||||
{
|
||||
hw->hist_offs.hist_x_offs = x_offset;
|
||||
hw->hist_offs.hist_x_offs = x_start;
|
||||
hw->hist_offs.hist_y_offs = y_start;
|
||||
hw->hist_size.hist_x_size = x_bsize;
|
||||
hw->hist_size.hist_y_size = y_bsize;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram y offset
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] y_offset value for y offset
|
||||
*/
|
||||
static inline void isp_ll_hist_set_y_offset(isp_dev_t *hw, uint32_t y_offset)
|
||||
{
|
||||
hw->hist_offs.hist_y_offs = y_offset;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram x size
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] x_size value for x size
|
||||
*/
|
||||
static inline void isp_ll_hist_set_window_x_size(isp_dev_t *hw, uint32_t x_size)
|
||||
{
|
||||
hw->hist_size.hist_x_size = x_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set histogram y size
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] y_size value for y size
|
||||
*/
|
||||
static inline void isp_ll_hist_set_window_y_size(isp_dev_t *hw, uint32_t y_size)
|
||||
{
|
||||
hw->hist_size.hist_y_size = y_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start histogram statistic
|
||||
* @brief Enable / Disable histogram statistic
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[in] enable enable/disable
|
||||
@ -1761,16 +1686,6 @@ static inline void isp_ll_hist_enable(isp_dev_t *hw, bool enable)
|
||||
hw->cntl.hist_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop histogram statistic
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
*/
|
||||
static inline void isp_ll_hist_stop(isp_dev_t *hw)
|
||||
{
|
||||
hw->cntl.hist_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
*
|
||||
@ -1786,27 +1701,27 @@ static inline void isp_ll_hist_get_histogram_value(isp_dev_t *hw, uint32_t *hist
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
* @brief Set histogram sampling mode
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[out] histogram_value pointer to histogram result
|
||||
* @param[in] hist_mode histogram mode
|
||||
*/
|
||||
static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_mode_enum_t hist_mode)
|
||||
static inline void isp_ll_hist_set_mode(isp_dev_t *hw, isp_hist_sampling_mode_t hist_mode)
|
||||
{
|
||||
hw->hist_mode.hist_mode = hist_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get histogram value
|
||||
* @brief Set histogram RGB coefficients, only effect when hist_mode is ISP_HIST_SAMPLING_RGB
|
||||
*
|
||||
* @param[in] hw Hardware instance address
|
||||
* @param[out] histogram_value pointer to histogram result
|
||||
* @param[in] rgb_coeff RGB coefficients
|
||||
*/
|
||||
static inline void isp_ll_hist_set_rgb_coefficient(isp_dev_t *hw, const isp_hist_rgb_coefficient *rgb_coeff)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, rgb_coeff->coeff_r);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, rgb_coeff->coeff_g);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, rgb_coeff->coeff_b);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_r, (rgb_coeff->coeff_r * 256) / 100);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_g, (rgb_coeff->coeff_g * 256) / 100);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hist_coeff, hist_coeff_b, (rgb_coeff->coeff_b * 256) / 100);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -188,6 +188,17 @@ uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t m
|
||||
*/
|
||||
void isp_hal_sharpen_config(isp_hal_context_t *hal, isp_hal_sharpen_cfg_t *config);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Histogram
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Configure Histogram window
|
||||
*
|
||||
* @param[in] hal Context of the HAL layer
|
||||
* @param[in] window Window info, see `isp_window_t`
|
||||
*/
|
||||
void isp_hal_hist_window_config(isp_hal_context_t *hal, const isp_window_t *window);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -33,8 +33,7 @@ typedef struct {
|
||||
} isp_coordinate_t;
|
||||
|
||||
/**
|
||||
* @brief ISP window type
|
||||
*
|
||||
* @brief The top left and bottom right coordinates of ISP full window
|
||||
*/
|
||||
typedef struct {
|
||||
isp_coordinate_t top_left; ///< The top left point coordinate
|
||||
@ -238,37 +237,35 @@ typedef struct {
|
||||
/*---------------------------------------------------------------
|
||||
HIST
|
||||
---------------------------------------------------------------*/
|
||||
#if SOC_ISP_HIST_WINDOW_NUMS
|
||||
#define ISP_HIST_WINDOW_NUM SOC_ISP_HIST_WINDOW_NUMS // The HIST window number for sampling
|
||||
#if (SOC_ISP_HIST_BLOCK_X_NUMS && SOC_ISP_HIST_BLOCK_Y_NUMS)
|
||||
#define ISP_HIST_BLOCK_X_NUM SOC_ISP_HIST_BLOCK_X_NUMS // The AF window number for sampling
|
||||
#define ISP_HIST_BLOCK_Y_NUM SOC_ISP_HIST_BLOCK_Y_NUMS // The AF window number for sampling
|
||||
#else
|
||||
#define ISP_HIST_WINDOW_NUM 0
|
||||
#define ISP_HIST_BLOCK_X_NUM 0
|
||||
#define ISP_HIST_BLOCK_Y_NUM 0
|
||||
#endif
|
||||
|
||||
#if SOC_ISP_HIST_SEGMENT_NUMS
|
||||
#if (SOC_ISP_HIST_SEGMENT_NUMS && SOC_ISP_HIST_INTERVAL_NUMS)
|
||||
#define ISP_HIST_SEGMENT_NUMS SOC_ISP_HIST_SEGMENT_NUMS // The segment of histogram
|
||||
#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The interval of histogram
|
||||
#else
|
||||
#define ISP_HIST_SEGMENT_NUMS 0
|
||||
#endif
|
||||
|
||||
#if SOC_ISP_HIST_INTERVAL_NUMS
|
||||
#define ISP_HIST_INTERVAL_NUMS SOC_ISP_HIST_INTERVAL_NUMS // The segment of histogram
|
||||
#else
|
||||
#define ISP_HIST_INTERVAL_NUMS 0
|
||||
#define ISP_HIST_INTERVAL_NUMS 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ISP histogram mode.
|
||||
*/
|
||||
typedef enum {
|
||||
ISP_HIST_RGB_B, ///< histogram mode for B component for RGB
|
||||
ISP_HIST_RGB_GB, ///< histogram mode for GB component for RGB
|
||||
ISP_HIST_RGB_GR, ///< histogram mode for GR component for RGB
|
||||
ISP_HIST_RGB_R, ///< histogram mode for R component for RGB
|
||||
ISP_HIST_RGB, ///< histogram mode for RGB
|
||||
ISP_HIST_YUV_Y, ///< histogram mode for Y component for YUV
|
||||
ISP_HIST_YUV_U, ///< histogram mode for U component for YUV
|
||||
ISP_HIST_YUV_V, ///< histogram mode for V component for YUV
|
||||
} isp_hist_mode_enum_t;
|
||||
ISP_HIST_SAMPLING_RAW_RGB_B, ///< histogram mode for B component of raw image
|
||||
ISP_HIST_SAMPLING_RAW_RGB_GB, ///< histogram mode for GB component of raw image
|
||||
ISP_HIST_SAMPLING_RAW_RGB_GR, ///< histogram mode for GR component of raw image
|
||||
ISP_HIST_SAMPLING_RAW_RGB_R, ///< histogram mode for R component of raw image
|
||||
ISP_HIST_SAMPLING_RGB, ///< histogram mode for RGB
|
||||
ISP_HIST_SAMPLING_YUV_Y, ///< histogram mode for Y component for YUV
|
||||
ISP_HIST_SAMPLING_YUV_U, ///< histogram mode for U component for YUV
|
||||
ISP_HIST_SAMPLING_YUV_V, ///< histogram mode for V component for YUV
|
||||
} isp_hist_sampling_mode_t;
|
||||
|
||||
/**
|
||||
* @brief ISP histogram r,g,b coefficient
|
||||
@ -283,7 +280,7 @@ typedef struct {
|
||||
* @brief ISP histogram result.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< histogram value.
|
||||
uint32_t hist_value[ISP_HIST_SEGMENT_NUMS]; ///< Histogram value, represents the number of pixels that the histogram window's brightness results fall into the segment X.
|
||||
} isp_hist_result_t;
|
||||
|
||||
|
||||
|
||||
@ -169,17 +169,18 @@ bool isp_hal_ccm_set_matrix(const isp_hal_context_t *hal, bool saturation, const
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR, put in iram
|
||||
Histogram
|
||||
---------------------------------------------------------------*/
|
||||
uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t mask)
|
||||
void isp_hal_hist_window_config(isp_hal_context_t *hal, const isp_window_t *window)
|
||||
{
|
||||
uint32_t triggered_events = isp_ll_get_intr_status(hal->hw) & mask;
|
||||
uint32_t hist_x_start = window->top_left.x;
|
||||
uint32_t hist_x_bsize = (window->btm_right.x - window-> top_left.x) / SOC_ISP_HIST_BLOCK_X_NUMS;
|
||||
|
||||
if (triggered_events) {
|
||||
isp_ll_clear_intr(hal->hw, triggered_events);
|
||||
}
|
||||
uint32_t hist_y_start = window->top_left.y;
|
||||
uint32_t hist_y_bsize = (window->btm_right.y - window->top_left.y) / SOC_ISP_HIST_BLOCK_Y_NUMS;
|
||||
|
||||
isp_ll_hist_set_window_range(hal->hw, hist_x_start, hist_x_bsize, hist_y_start, hist_y_bsize);
|
||||
|
||||
return triggered_events;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
@ -213,3 +214,17 @@ void isp_hal_sharpen_config(isp_hal_context_t *hal, isp_hal_sharpen_cfg_t *confi
|
||||
isp_ll_sharp_set_template(hal->hw, default_template);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
INTR, put in iram
|
||||
---------------------------------------------------------------*/
|
||||
uint32_t isp_hal_check_clear_intr_event(const isp_hal_context_t *hal, uint32_t mask)
|
||||
{
|
||||
uint32_t triggered_events = isp_ll_get_intr_status(hal->hw) & mask;
|
||||
|
||||
if (triggered_events) {
|
||||
isp_ll_clear_intr(hal->hw, triggered_events);
|
||||
}
|
||||
|
||||
return triggered_events;
|
||||
}
|
||||
|
||||
@ -923,9 +923,17 @@ config SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS
|
||||
int
|
||||
default 24
|
||||
|
||||
config SOC_ISP_HIST_WINDOW_NUMS
|
||||
config SOC_ISP_HIST_CTLR_NUMS
|
||||
int
|
||||
default 25
|
||||
default 1
|
||||
|
||||
config SOC_ISP_HIST_BLOCK_X_NUMS
|
||||
int
|
||||
default 5
|
||||
|
||||
config SOC_ISP_HIST_BLOCK_Y_NUMS
|
||||
int
|
||||
default 5
|
||||
|
||||
config SOC_ISP_HIST_SEGMENT_NUMS
|
||||
int
|
||||
|
||||
@ -1821,6 +1821,25 @@ typedef union {
|
||||
uint32_t val;
|
||||
} isp_hist_size_reg_t;
|
||||
|
||||
/** Type of hist_seg register
|
||||
* histogram bin control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hist_seg: R/W;
|
||||
* default:
|
||||
* 16, 32, 48, 64,
|
||||
* 80, 96, 112, 128,
|
||||
* 144, 160, 176, 192,
|
||||
* 208, 224, 240
|
||||
* this field configures threshold of histogram
|
||||
*/
|
||||
uint8_t hist_seg_b[4];
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_seg_reg_t;
|
||||
|
||||
|
||||
/** Type of hist_seg0 register
|
||||
* histogram bin control register 0
|
||||
*/
|
||||
@ -1918,6 +1937,20 @@ typedef union {
|
||||
uint32_t val;
|
||||
} isp_hist_seg3_reg_t;
|
||||
|
||||
/** Type of hist_weight register
|
||||
* histogram sub-window weight register 0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** histogram weight : RO; bitpos: [31:0];
|
||||
* weight[12] default 232, others default 1
|
||||
* this field represents the weight of histogram subwindow, sum of all weight should be 256
|
||||
*/
|
||||
uint8_t hist_weight_b[4];
|
||||
};
|
||||
uint32_t val;
|
||||
} isp_hist_weight_reg_t;
|
||||
|
||||
/** Type of hist_weight0 register
|
||||
* histogram sub-window weight register 0
|
||||
*/
|
||||
@ -3227,17 +3260,8 @@ typedef struct {
|
||||
volatile isp_hist_coeff_reg_t hist_coeff;
|
||||
volatile isp_hist_offs_reg_t hist_offs;
|
||||
volatile isp_hist_size_reg_t hist_size;
|
||||
volatile isp_hist_seg0_reg_t hist_seg0;
|
||||
volatile isp_hist_seg1_reg_t hist_seg1;
|
||||
volatile isp_hist_seg2_reg_t hist_seg2;
|
||||
volatile isp_hist_seg3_reg_t hist_seg3;
|
||||
volatile isp_hist_weight0_reg_t hist_weight0;
|
||||
volatile isp_hist_weight1_reg_t hist_weight1;
|
||||
volatile isp_hist_weight2_reg_t hist_weight2;
|
||||
volatile isp_hist_weight3_reg_t hist_weight3;
|
||||
volatile isp_hist_weight4_reg_t hist_weight4;
|
||||
volatile isp_hist_weight5_reg_t hist_weight5;
|
||||
volatile isp_hist_weight6_reg_t hist_weight6;
|
||||
volatile isp_hist_seg_reg_t hist_seg[4];
|
||||
volatile isp_hist_weight_reg_t hist_weight[7];
|
||||
volatile isp_hist_binn_reg_t hist_binn[16];
|
||||
volatile isp_mem_aux_ctrl_0_reg_t mem_aux_ctrl_0;
|
||||
volatile isp_mem_aux_ctrl_1_reg_t mem_aux_ctrl_1;
|
||||
|
||||
@ -355,9 +355,11 @@
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5
|
||||
#define SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24
|
||||
#define SOC_ISP_HIST_WINDOW_NUMS 25
|
||||
#define SOC_ISP_HIST_SEGMENT_NUMS 16
|
||||
#define SOC_ISP_HIST_INTERVAL_NUMS 15
|
||||
#define SOC_ISP_HIST_CTLR_NUMS 1U
|
||||
#define SOC_ISP_HIST_BLOCK_X_NUMS 5
|
||||
#define SOC_ISP_HIST_BLOCK_Y_NUMS 5
|
||||
#define SOC_ISP_HIST_SEGMENT_NUMS 16
|
||||
#define SOC_ISP_HIST_INTERVAL_NUMS 15
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
|
||||
|
||||
@ -153,6 +153,28 @@ If the configurations in :cpp:type:`esp_isp_ae_config_t` is specified, users can
|
||||
|
||||
You can use the created handle to do driver enable / disable the ISP AE driver and ISP AE environment detector setup.
|
||||
|
||||
Install ISP histogram (HIST) Driver
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
ISP histogram (HIST) driver requires the configuration that specified by :cpp:type:`esp_isp_hist_config_t`.
|
||||
|
||||
If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP HISTG processor. This function will return an ISP HIST processor handle if it runs correctly. You can take following code as reference.
|
||||
|
||||
.. code:: c
|
||||
|
||||
esp_isp_hist_config_t hist_cfg = {
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.rgb_coefficient.coeff_r = 33,
|
||||
.rgb_coefficient.coeff_g = 33,
|
||||
.rgb_coefficient.coeff_b = 34,
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}},
|
||||
};
|
||||
isp_hist_ctlr_t hist_ctlr_ctlr = NULL;
|
||||
ESP_ERROR_CHECK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr));
|
||||
|
||||
You can use the created handle to do driver enable / disable the ISP HIST driver setup.
|
||||
|
||||
Uninstall ISP Driver
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
@ -173,6 +195,11 @@ UnInstall ISP AE Driver
|
||||
|
||||
If a previously installed ISP AE processor is no longer needed, it's recommended to free the resource by calling :cpp:func:`esp_isp_del_ae_controller`, it will also release the underlying hardware.
|
||||
|
||||
UnInstall ISP HIST Driver
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
If a previously installed ISP HIST processor is no longer needed, it's recommended to free the resource by calling :cpp:func:`esp_isp_del_hist_controller`, it will also release the underlying hardware.
|
||||
|
||||
|
||||
.. _isp-enable-disable:
|
||||
|
||||
@ -417,6 +444,8 @@ Aside from the above oneshot API, the ISP histogram driver also provides a way t
|
||||
|
||||
Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__
|
||||
|
||||
Note that the sum of all subwindows's weight should be 100, the sum of all RGB coefficients should be 100, and segment_threshold must be 0 ~ 256.
|
||||
|
||||
.. code:: c
|
||||
|
||||
static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data)
|
||||
@ -427,29 +456,23 @@ Note that if you want to use the continuous statistics, you need to register the
|
||||
return true;
|
||||
}
|
||||
|
||||
isp_hist_ctlr_t hist_ctrlr = NULL;
|
||||
isp_hist_ctlr_t hist_ctlr = NULL;
|
||||
esp_isp_hist_config_t hist_cfg = {
|
||||
.first_window_x_offs = 0,
|
||||
.first_window_y_offs = 0,
|
||||
.window_x_size = 800 / 25,
|
||||
.window_y_size = 640 / 25,
|
||||
.rgb_coefficient = {
|
||||
.coeff_b = 85,
|
||||
.coeff_g = 85,
|
||||
.coeff_r = 85,
|
||||
},
|
||||
.hist_windows_weight = {[0 ... ISP_HIST_WINDOW_NUM - 1] = 10},
|
||||
.hist_segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.hist_mode = ISP_HIST_RGB,
|
||||
.segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
|
||||
.rgb_coefficient.coeff_r = 33,
|
||||
.rgb_coefficient.coeff_g = 33,
|
||||
.rgb_coefficient.coeff_b = 34,
|
||||
.hist_mode = ISP_HIST_SAMPLING_RGB,
|
||||
.windows_weight = {{4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}, {4, 4, 4, 4, 4}},
|
||||
};
|
||||
|
||||
esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctrlr);
|
||||
esp_isp_new_hist_controller(isp_proc, &hist_cfg, &hist_ctlr);
|
||||
esp_isp_hist_cbs_t hist_cbs = {
|
||||
.on_statistics_done = s_hist_scheme_on_statistics_done_callback,
|
||||
};
|
||||
|
||||
esp_isp_hist_register_event_callbacks(hist_ctrlr, &hist_cbs, hist_ctrlr);
|
||||
esp_isp_hist_controller_enable(hist_ctrlr);
|
||||
esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cbs, hist_ctlr);
|
||||
esp_isp_hist_controller_enable(hist_ctlr);
|
||||
|
||||
|
||||
.. _isp_bf:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user