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fix(mspi): Refactor mspi ll/soc for c5 and c61

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C.S.M 2024-07-15 11:39:35 +08:00
parent e5e146365b
commit bc80476411
34 changed files with 13196 additions and 10355 deletions
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100
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
View File

@ -18,19 +18,8 @@
#endif
#include "hal/spi_flash_ll.h"
#include "rom/spi_flash.h"
#if CONFIG_IDF_TARGET_ESP32
# include "soc/spi_struct.h"
# include "soc/spi_reg.h"
/* SPI flash controller */
# define SPIFLASH SPI1
# define SPI0 SPI0
#else
# include "hal/spimem_flash_ll.h"
# include "soc/spi_mem_struct.h"
# include "soc/spi_mem_reg.h"
/* SPI flash controller */
# define SPIFLASH SPIMEM1
# define SPI0 SPIMEM0
#if !CONFIG_IDF_TARGET_ESP32
#include "hal/spimem_flash_ll.h"
#endif
// This dependency will be removed in the future. IDF-5025
@ -587,61 +576,43 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
{
assert(mosi_len <= 32);
assert(miso_len <= 32);
uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
uint32_t old_user_reg = SPIFLASH.user.val;
uint32_t old_user1_reg = SPIFLASH.user1.val;
uint32_t old_user2_reg = SPIFLASH.user2.val;
// Clear ctrl regs.
SPIFLASH.ctrl.val = 0;
uint32_t old_ctrl_reg = 0;
uint32_t old_user_reg = 0;
uint32_t old_user1_reg = 0;
uint32_t old_user2_reg = 0;
spi_flash_ll_get_common_command_register_info(&SPIMEM_LL_APB, &old_ctrl_reg, &old_user_reg, &old_user1_reg, &old_user2_reg);
SPIMEM_LL_APB.ctrl.val = 0;
#if CONFIG_IDF_TARGET_ESP32
spi_flash_ll_set_wp_level(&SPIFLASH, true);
spi_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
#else
spimem_flash_ll_set_wp_level(&SPIFLASH, true);
spimem_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
#endif
//command phase
SPIFLASH.user.usr_command = 1;
SPIFLASH.user2.usr_command_bitlen = 7;
SPIFLASH.user2.usr_command_value = command;
spi_flash_ll_set_command(&SPIMEM_LL_APB, command, 8);
//addr phase
SPIFLASH.user.usr_addr = addr_len > 0;
SPIFLASH.user1.usr_addr_bitlen = addr_len - 1;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.addr = (addr_len > 0)? (address << (32-addr_len)) : 0;
#else
SPIFLASH.addr = address;
#endif
spi_flash_ll_set_addr_bitlen(&SPIMEM_LL_APB, addr_len);
spi_flash_ll_set_usr_address(&SPIMEM_LL_APB, address, addr_len);
//dummy phase
uint32_t total_dummy = dummy_len;
if (miso_len > 0) {
total_dummy += g_rom_spiflash_dummy_len_plus[1];
}
SPIFLASH.user.usr_dummy = total_dummy > 0;
SPIFLASH.user1.usr_dummy_cyclelen = total_dummy - 1;
spi_flash_ll_set_dummy(&SPIMEM_LL_APB, total_dummy);
//output data
SPIFLASH.user.usr_mosi = mosi_len > 0;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
#else
SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
#endif
SPIFLASH.data_buf[0] = mosi_data;
spi_flash_ll_set_mosi_bitlen(&SPIMEM_LL_APB, mosi_len);
spi_flash_ll_set_buffer_data(&SPIMEM_LL_APB, &mosi_data, mosi_len / 8);
//input data
SPIFLASH.user.usr_miso = miso_len > 0;
#if CONFIG_IDF_TARGET_ESP32
SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
#else
SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
#endif
spi_flash_ll_set_miso_bitlen(&SPIMEM_LL_APB, miso_len);
SPIFLASH.cmd.usr = 1;
while (SPIFLASH.cmd.usr != 0) {
spi_flash_ll_user_start(&SPIMEM_LL_APB, false);
while(!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
}
SPIFLASH.ctrl.val = old_ctrl_reg;
SPIFLASH.user.val = old_user_reg;
SPIFLASH.user1.val = old_user1_reg;
SPIFLASH.user2.val = old_user2_reg;
spi_flash_ll_set_common_command_register_info(&SPIMEM_LL_APB, old_ctrl_reg, old_user_reg, old_user1_reg, old_user2_reg);
uint32_t ret = SPIFLASH.data_buf[0];
uint32_t output_data = 0;
spi_flash_ll_get_buffer_data(&SPIMEM_LL_APB, &output_data, miso_len / 8);
uint32_t ret = output_data;
if (miso_len < 32) {
//set unused bits to 0
ret &= ~(UINT32_MAX << miso_len);
@ -793,28 +764,9 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
#endif //XMC_SUPPORT
FORCE_INLINE_ATTR void bootloader_mspi_reset(void)
{
#if CONFIG_IDF_TARGET_ESP32
SPI1.slave.sync_reset = 0;
SPI0.slave.sync_reset = 0;
SPI1.slave.sync_reset = 1;
SPI0.slave.sync_reset = 1;
SPI1.slave.sync_reset = 0;
SPI0.slave.sync_reset = 0;
#else
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
#endif
}
esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
{
bootloader_mspi_reset();
spi_flash_ll_sync_reset();
// Seems that sync_reset cannot make host totally idle.'
// Sending an extra(useless) command to make the host idle in order to send reset command.
bootloader_execute_flash_command(0x05, 0, 0, 0);
@ -844,7 +796,7 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
{
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPIMEM_LL_CACHE);
#if CONFIG_IDF_TARGET_ESP32
if (spi_ctrl & SPI_FREAD_QIO) {
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;

57
components/hal/esp32/include/hal/spi_flash_ll.h
View File

@ -48,6 +48,9 @@ extern "C" {
// On ESP32, we extent 4 bits to occupy `Continuous Read Mode` bits. (same to origin code.)
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (4)
#define SPIMEM_LL_APB SPI1
#define SPIMEM_LL_CACHE SPI0
/// type to store pre-calculated register value in above layers
typedef typeof(SPI1.clock.val) spi_flash_ll_clock_reg_t;
@ -130,6 +133,7 @@ static inline void spi_flash_ll_set_write_protect(spi_dev_t *dev, bool wp)
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -166,6 +170,7 @@ static inline void spi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -301,6 +306,7 @@ static inline void spi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -342,6 +348,7 @@ static inline int spi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -354,6 +361,7 @@ static inline void spi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, int bit_len)
{
// The blank region should be all ones
@ -362,7 +370,9 @@ static inline void spi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, i
dev->slv_wr_status = UINT32_MAX;
} else {
uint32_t padding_ones = UINT32_MAX >> bit_len;
dev->addr = (addr << (32 - bit_len)) | padding_ones;
if (bit_len != 0) {
dev->addr = (addr << (32 - bit_len)) | padding_ones;
}
}
}
@ -467,6 +477,51 @@ static inline uint32_t spi_flash_ll_get_ctrl_val(spi_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spi_flash_ll_sync_reset(void)
{
SPI1.slave.sync_reset = 0;
SPI0.slave.sync_reset = 0;
SPI1.slave.sync_reset = 1;
SPI0.slave.sync_reset = 1;
SPI1.slave.sync_reset = 0;
SPI0.slave.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spi_flash_ll_get_common_command_register_info(spi_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spi_flash_ll_set_common_command_register_info(spi_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

6
components/hal/esp32c2/include/hal/spi_flash_ll.h
View File

@ -42,6 +42,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -92,6 +95,9 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32c2/include/hal/spimem_flash_ll.h
View File

@ -321,6 +321,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -346,6 +347,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -499,6 +501,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -539,6 +542,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -562,6 +566,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -667,6 +672,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32c3/include/hal/spi_flash_ll.h
View File

@ -42,6 +42,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -92,6 +95,10 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32c3/include/hal/spimem_flash_ll.h
View File

@ -323,6 +323,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -348,6 +349,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -501,6 +503,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -541,6 +544,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -564,6 +568,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -682,6 +687,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

47
components/hal/esp32c5/include/hal/psram_ctrlr_ll.h
View File

@ -18,7 +18,6 @@
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/spi_mem_struct.h"
#include "soc/spi1_mem_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/clk_tree_defs.h"
#include "rom/opi_flash.h"
@ -53,9 +52,9 @@ static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitl
{
(void)mspi_id;
HAL_ASSERT(cmd_bitlen > 0);
SPIMEM0.cache_sctrl.sram_usr_wcmd = 1;
SPIMEM0.sram_dwr_cmd.sram_usr_wr_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_dwr_cmd, sram_usr_wr_cmd_value, cmd_val);
SPIMEM0.mem_cache_sctrl.mem_cache_sram_usr_wcmd = 1;
SPIMEM0.mem_sram_dwr_cmd.mem_cache_sram_usr_wr_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.mem_sram_dwr_cmd, mem_cache_sram_usr_wr_cmd_value, cmd_val);
}
/**
@ -70,9 +69,9 @@ static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitl
{
(void)mspi_id;
HAL_ASSERT(cmd_bitlen > 0);
SPIMEM0.cache_sctrl.sram_usr_rcmd = 1;
SPIMEM0.sram_drd_cmd.sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_drd_cmd, sram_usr_rd_cmd_value, cmd_val);
SPIMEM0.mem_cache_sctrl.mem_cache_sram_usr_rcmd = 1;
SPIMEM0.mem_sram_drd_cmd.mem_cache_sram_usr_rd_cmd_bitlen = cmd_bitlen - 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.mem_sram_drd_cmd, mem_cache_sram_usr_rd_cmd_value, cmd_val);
}
/**
@ -86,7 +85,7 @@ static inline void psram_ctrlr_ll_set_addr_bitlen(uint32_t mspi_id, uint32_t add
{
(void)mspi_id;
HAL_ASSERT(addr_bitlen > 0);
SPIMEM0.cache_sctrl.sram_addr_bitlen = addr_bitlen - 1;
SPIMEM0.mem_cache_sctrl.mem_sram_addr_bitlen = addr_bitlen - 1;
}
/**
@ -100,8 +99,8 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_
{
(void)mspi_id;
HAL_ASSERT(dummy_n > 0);
SPIMEM0.cache_sctrl.usr_rd_sram_dummy = 1;
SPIMEM0.cache_sctrl.sram_rdummy_cyclelen = dummy_n - 1;
SPIMEM0.mem_cache_sctrl.mem_usr_rd_sram_dummy = 1;
SPIMEM0.mem_cache_sctrl.mem_sram_rdummy_cyclelen = dummy_n - 1;
}
/**
@ -113,7 +112,7 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_bus_clock(uint32_t mspi_id, uint32_t clock_conf)
{
SPIMEM0.sram_clk.val = clock_conf;
SPIMEM0.mem_sram_clk.val = clock_conf;
}
/**
@ -143,21 +142,21 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode)
{
typeof (SPIMEM0.cache_sctrl) cache_sctrl;
cache_sctrl.val = SPIMEM0.cache_sctrl.val;
typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl;
mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val;
cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
mem_cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
switch (read_mode) {
case PSRAM_HAL_CMD_SPI:
cache_sctrl.usr_sram_dio = 1;
mem_cache_sctrl.mem_usr_sram_dio = 1;
break;
case PSRAM_HAL_CMD_QPI:
cache_sctrl.usr_sram_qio = 1;
mem_cache_sctrl.mem_usr_sram_qio = 1;
break;
default:
abort();
}
SPIMEM0.cache_sctrl.val = cache_sctrl.val;
SPIMEM0.mem_cache_sctrl.val = mem_cache_sctrl.val;
}
/**
@ -171,8 +170,8 @@ static inline void psram_ctrlr_ll_set_cs_setup(uint32_t mspi_id, uint32_t setup_
{
(void)mspi_id;
HAL_ASSERT(setup_n > 0);
SPIMEM0.spi_smem_ac.reg_smem_cs_setup = 1;
SPIMEM0.spi_smem_ac.reg_smem_cs_setup_time = setup_n - 1;
SPIMEM0.smem_ac.smem_cs_setup = 1;
SPIMEM0.smem_ac.smem_cs_setup_time = setup_n - 1;
}
/**
@ -186,8 +185,8 @@ static inline void psram_ctrlr_ll_set_cs_hold(uint32_t mspi_id, uint32_t hold_n)
{
(void)mspi_id;
HAL_ASSERT(hold_n > 0);
SPIMEM0.spi_smem_ac.reg_smem_cs_hold = 1;
SPIMEM0.spi_smem_ac.reg_smem_cs_hold_time = hold_n - 1;
SPIMEM0.smem_ac.smem_cs_hold = 1;
SPIMEM0.smem_ac.smem_cs_hold_time = hold_n - 1;
}
/**
@ -201,7 +200,7 @@ static inline void psram_ctrlr_ll_set_cs_hold_delay(uint32_t mspi_id, uint32_t h
{
(void)mspi_id;
HAL_ASSERT(hold_delay_n > 0);
SPIMEM0.spi_smem_ac.reg_smem_cs_hold_delay = hold_delay_n - 1;
SPIMEM0.smem_ac.smem_cs_hold_delay = hold_delay_n - 1;
}
/**
@ -243,8 +242,8 @@ static inline void psram_ctrlr_ll_common_transaction_base(uint32_t mspi_id, esp_
__attribute__((always_inline))
static inline void psram_ctrlr_ll_set_cs_pin(uint32_t mspi_id, psram_ll_cs_id_t cs_id)
{
SPIMEM0.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
SPIMEM0.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
SPIMEM1.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
SPIMEM1.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
}
/**

7
components/hal/esp32c5/include/hal/spi_flash_ll.h
View File

@ -45,6 +45,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -95,6 +98,10 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

89
components/hal/esp32c5/include/hal/spimem_flash_ll.h
View File

@ -18,7 +18,6 @@
#include <sys/param.h> // For MIN/MAX
#include <stdbool.h>
#include <string.h>
#include "sdkconfig.h" // TODO: remove
#include "soc/spi_periph.h"
#include "soc/spi_mem_struct.h"
@ -212,7 +211,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
*/
static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
{
dev->flash_sus_ctrl.frd_sus_2b = 0;
dev->flash_sus_ctrl.fmem_rd_sus_2b = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
}
@ -237,7 +236,7 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
*/
static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay)
{
SPIMEM0.ctrl2.cs_hold_delay = cs_hold_delay;
SPIMEM0.ctrl2.mem_cs_hold_delay = cs_hold_delay;
}
/**
@ -256,14 +255,19 @@ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool
/**
* This function is used to set dummy phase when auto suspend is enabled.
*
* @note This function is only used when timing tuning is enabled.
* @note This function is only used when timing tuning is enabled. This function is only used in quad flash
*
* @param dev Beginning address of the peripheral registers.
* @param extra_dummy extra dummy length. Get from timing tuning.
*/
static inline void spimem_flash_ll_set_wait_idle_dummy_phase(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
// Not supported on this chip.
if (extra_dummy > 0) {
dev->flash_waiti_ctrl.waiti_dummy_cyclelen = extra_dummy - 1;
dev->flash_waiti_ctrl.waiti_dummy = 1;
} else {
dev->flash_waiti_ctrl.waiti_dummy = 0;
}
}
/**
@ -287,7 +291,7 @@ static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time)
{
dev->sus_status.spi0_lock_en = 1;
SPIMEM0.fsm.lock_delay_time = lock_time;
SPIMEM0.mem_fsm.mem_lock_delay_time = lock_time;
}
/**
@ -329,6 +333,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -354,6 +359,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -507,6 +513,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -547,6 +554,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -561,8 +569,8 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
dev->cache_fctrl.cache_usr_addr_4byte = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
}
/**
@ -582,6 +590,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -608,14 +617,23 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
// Not supported on esp32c5
}
/**
* Set CS setup time
*
* @param dev Beginning address of the peripheral registers.
* @param cs_setup_time CS setup time
*/
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
{
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
// Not supported on esp32c5
}
static inline void spimem_flash_ll_set_extra_dummy(spi_mem_dev_t *dev, uint32_t extra_dummy)
{
//for compatibility
}
/**
@ -675,7 +693,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
dev->ctrl.wp_reg = level;
}
/**
@ -688,6 +706,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32c6/include/hal/spi_flash_ll.h
View File

@ -43,6 +43,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -93,6 +96,10 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32c6/include/hal/spimem_flash_ll.h
View File

@ -324,6 +324,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -349,6 +350,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -502,6 +504,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -542,6 +545,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -577,6 +581,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -701,6 +706,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

4
components/hal/esp32c61/include/hal/mmu_ll.h
View File

@ -71,7 +71,7 @@ __attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
(void)mmu_id;
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE);
return (page_size_code == 0) ? MMU_PAGE_64KB : \
(page_size_code == 1) ? MMU_PAGE_32KB : \
(page_size_code == 2) ? MMU_PAGE_16KB : \
@ -90,7 +90,7 @@ static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
(size == MMU_PAGE_32KB) ? 1 : \
(size == MMU_PAGE_16KB) ? 2 : \
(size == MMU_PAGE_8KB) ? 3 : 0;
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE, reg_val);
}
/**

16
components/hal/esp32c61/include/hal/spi_flash_encrypted_ll.h
View File

@ -61,7 +61,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type);
REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_XTS_DESTINATION, type);
}
/**
@ -72,7 +72,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
// Desired block should not be larger than the block size.
REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5);
REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_XTS_LINESIZE, size >> 5);
}
/**
@ -97,7 +97,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr);
REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
}
/**
@ -105,7 +105,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1);
REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_XTS_TRIGGER, 1);
}
/**
@ -113,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) {
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
}
}
@ -122,8 +122,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/
static inline void spi_flash_encrypt_ll_done(void)
{
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) {
REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_XTS_RELEASE);
while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
}
}
@ -132,7 +132,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY);
REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_XTS_DESTROY);
}
/**

7
components/hal/esp32c61/include/hal/spi_flash_ll.h
View File

@ -45,6 +45,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -95,6 +98,10 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

71
components/hal/esp32c61/include/hal/spimem_flash_ll.h
View File

@ -210,7 +210,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool
*/
static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
{
dev->flash_sus_ctrl.frd_sus_2b = 0;
dev->flash_sus_ctrl.fmem_rd_sus_2b = 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
}
@ -235,7 +235,7 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
*/
static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay)
{
SPIMEM0.ctrl2.cs_hold_delay = cs_hold_delay;
SPIMEM0.mem_ctrl2.mem_cs_hold_delay = cs_hold_delay;
}
/**
@ -285,7 +285,7 @@ static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time)
{
dev->sus_status.spi0_lock_en = 1;
SPIMEM0.fsm.lock_delay_time = lock_time;
SPIMEM0.mem_fsm.mem_lock_delay_time = lock_time;
}
/**
@ -327,6 +327,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -495,7 +496,7 @@ static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll
static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_miso = bitlen > 0;
dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0;
dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0;
}
/**
@ -505,10 +506,11 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0;
}
/**
@ -545,6 +547,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -559,7 +562,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
*/
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
{
dev->cache_fctrl.usr_addr_4byte = 0;
dev->cache_fctrl.cache_usr_addr_4byte = 0;
dev->rd_status.wb_mode = extra_addr;
}
@ -571,7 +574,7 @@ static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_
*/
static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr)
{
dev->addr = addr;
dev->addr.usr_addr_value = addr;
}
/**
@ -580,6 +583,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -606,14 +610,12 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
*/
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
// Not supported on esp32c61
}
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
{
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
// Not supported on esp32c61
}
/**
@ -687,7 +689,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
{
dev->ctrl.wp = level;
dev->ctrl.wp_reg = level;
}
/**
@ -700,6 +702,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.mem_ctrl2.mem_sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.mem_ctrl2.mem_sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.mem_ctrl2.mem_sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32h2/include/hal/spi_flash_ll.h
View File

@ -43,6 +43,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -93,6 +96,10 @@ typedef union {
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32h2/include/hal/spimem_flash_ll.h
View File

@ -325,6 +325,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -350,6 +351,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -523,6 +525,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -563,6 +566,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -598,6 +602,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -703,6 +708,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32p4/include/hal/spi_flash_ll.h
View File

@ -43,6 +43,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -95,6 +98,10 @@ typedef union {
#define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@ -335,6 +335,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -360,6 +361,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -512,6 +514,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -552,6 +555,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
unsigned chip_version = efuse_hal_chip_revision();
@ -591,6 +595,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -774,6 +779,51 @@ static inline void spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t freq
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; spimem_ctrlr_ll_set_core_clock(__VA_ARGS__)
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32s2/include/hal/spi_flash_ll.h
View File

@ -42,6 +42,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
@ -95,6 +98,10 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32s2/include/hal/spimem_flash_ll.h
View File

@ -264,6 +264,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -289,6 +290,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -441,6 +443,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -481,6 +484,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user1.usr_addr_bitlen = (bitlen - 1);
@ -504,6 +508,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -616,6 +621,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32s3/include/hal/spi_flash_ll.h
View File

@ -41,6 +41,9 @@ typedef union {
spimem_flash_ll_clock_reg_t spimem;
} spi_flash_ll_clock_reg_t;
#define SPIMEM_LL_APB SPIMEM1
#define SPIMEM_LL_CACHE SPIMEM0
#ifdef GPSPI_BUILD
#define spi_flash_ll_reset(dev) gpspi_flash_ll_reset((spi_dev_t*)dev)
#define spi_flash_ll_cmd_is_done(dev) gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
@ -92,6 +95,10 @@ typedef union {
#define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev)
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
#endif

50
components/hal/esp32s3/include/hal/spimem_flash_ll.h
View File

@ -326,6 +326,7 @@ static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
{
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
@ -351,6 +352,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
* @param buffer Buffer holding the data
* @param length Length of data in bytes.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
{
// Load data registers, word at a time
@ -519,6 +521,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of output, in bits.
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
dev->user.usr_mosi = bitlen > 0;
@ -559,6 +562,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param bitlen Length of the address, in bits
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
{
// set the correct address length here (24-length or 32-length address),
@ -584,6 +588,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
* @param dev Beginning address of the peripheral registers.
* @param addr Address to send
*/
__attribute__((always_inline))
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
(void)bitlen;
@ -704,6 +709,51 @@ static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev)
return dev->ctrl.val;
}
/**
* @brief Reset whole memory spi
*/
static inline void spimem_flash_ll_sync_reset(void)
{
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
SPIMEM1.ctrl2.sync_reset = 1;
SPIMEM0.ctrl2.sync_reset = 1;
SPIMEM1.ctrl2.sync_reset = 0;
SPIMEM0.ctrl2.sync_reset = 0;
}
/**
* @brief Get common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
{
*ctrl_reg = dev->ctrl.val;
*user_reg = dev->user.val;
*user1_reg = dev->user1.val;
*user2_reg = dev->user2.val;
}
/**
* @brief Set common command related registers
*
* @param ctrl_reg ctrl_reg
* @param user_reg user_reg
* @param user1_reg user1_reg
* @param user2_reg user2_reg
*/
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
{
dev->ctrl.val = ctrl_reg;
dev->user.val = user_reg;
dev->user1.val = user1_reg;
dev->user2.val = user2_reg;
}
#ifdef __cplusplus
}
#endif

30
components/soc/esp32c5/include/soc/spi1_mem_struct.h
View File

@ -393,10 +393,10 @@ typedef union {
*/
typedef union {
struct {
/** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0;
/** usr_mosi_bit_len : R/W; bitpos: [9:0]; default: 0;
* The length in bits of write-data. The register value shall be (bit_num-1).
*/
uint32_t usr_mosi_dbitlen:10;
uint32_t usr_mosi_bit_len:10;
uint32_t reserved_10:22;
};
uint32_t val;
@ -410,7 +410,7 @@ typedef union {
/** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0;
* The length in bits of read-data. The register value shall be (bit_num-1).
*/
uint32_t usr_miso_dbitlen:10;
uint32_t usr_miso_bit_len:10;
uint32_t reserved_10:22;
};
uint32_t val;
@ -1232,9 +1232,9 @@ typedef union {
} spi_mem_date_reg_t;
typedef struct {
typedef struct spi1_mem_dev_s {
volatile spi_mem_cmd_reg_t cmd;
volatile spi_mem_addr_reg_t addr;
volatile uint32_t addr;
volatile spi_mem_ctrl_reg_t ctrl;
volatile spi_mem_ctrl1_reg_t ctrl1;
volatile spi_mem_ctrl2_reg_t ctrl2;
@ -1250,22 +1250,7 @@ typedef struct {
volatile spi_mem_tx_crc_reg_t tx_crc;
volatile spi_mem_cache_fctrl_reg_t cache_fctrl;
uint32_t reserved_040[6];
volatile spi_mem_w0_reg_t w0;
volatile spi_mem_w1_reg_t w1;
volatile spi_mem_w2_reg_t w2;
volatile spi_mem_w3_reg_t w3;
volatile spi_mem_w4_reg_t w4;
volatile spi_mem_w5_reg_t w5;
volatile spi_mem_w6_reg_t w6;
volatile spi_mem_w7_reg_t w7;
volatile spi_mem_w8_reg_t w8;
volatile spi_mem_w9_reg_t w9;
volatile spi_mem_w10_reg_t w10;
volatile spi_mem_w11_reg_t w11;
volatile spi_mem_w12_reg_t w12;
volatile spi_mem_w13_reg_t w13;
volatile spi_mem_w14_reg_t w14;
volatile spi_mem_w15_reg_t w15;
volatile uint32_t data_buf[16]; /*data buffer*/
volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd;
@ -1287,9 +1272,8 @@ typedef struct {
volatile spi_mem_date_reg_t date;
} spi1_mem_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(spi1_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
_Static_assert(sizeof(spi1_mem_dev_t) == 0x400, "Invalid size of spi1_mem_dev_t structure");
#endif
#ifdef __cplusplus

3907
components/soc/esp32c5/include/soc/spi_mem_c_reg.h Normal file
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2972
components/soc/esp32c5/include/soc/spi_mem_c_struct.h Normal file
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3902
components/soc/esp32c5/include/soc/spi_mem_reg.h
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1074
components/soc/esp32c5/include/soc/spi_mem_struct.h
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File diff suppressed because it is too large Load Diff

94
components/soc/esp32c61/include/soc/spi1_mem_reg.h
View File

@ -14,7 +14,7 @@ extern "C" {
/** SPI_MEM_CMD_REG register
* SPI1 memory command register
*/
#define SPI_MEM_CMD_REG (DR_REG_SPI_MEM_BASE + 0x0)
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
* The current status of SPI1 master FSM.
*/
@ -158,7 +158,7 @@ extern "C" {
/** SPI_MEM_ADDR_REG register
* SPI1 address register
*/
#define SPI_MEM_ADDR_REG (DR_REG_SPI_MEM_BASE + 0x4)
#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)
/** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
* In user mode, it is the memory address. other then the bit0-bit23 is the memory
* address, the bit24-bit31 are the byte length of a transfer.
@ -171,7 +171,7 @@ extern "C" {
/** SPI_MEM_CTRL_REG register
* SPI1 control register.
*/
#define SPI_MEM_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x8)
#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)
/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
* In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
* level of SPI bus is output by the MSPI controller.
@ -317,11 +317,11 @@ extern "C" {
/** SPI_MEM_CTRL1_REG register
* SPI1 control1 register.
*/
#define SPI_MEM_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xc)
#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc)
/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
* SPI clock is alwasy on.
* SPI clock is always on.
*/
#define SPI_MEM_CLK_MODE 0x00000003U
#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
@ -339,7 +339,7 @@ extern "C" {
/** SPI_MEM_CTRL2_REG register
* SPI1 control2 register.
*/
#define SPI_MEM_CTRL2_REG (DR_REG_SPI_MEM_BASE + 0x10)
#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)
/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
* The FSM will be reset.
*/
@ -351,7 +351,7 @@ extern "C" {
/** SPI_MEM_CLOCK_REG register
* SPI1 clock division control register.
*/
#define SPI_MEM_CLOCK_REG (DR_REG_SPI_MEM_BASE + 0x14)
#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)
/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
*/
@ -385,7 +385,7 @@ extern "C" {
/** SPI_MEM_USER_REG register
* SPI1 user register.
*/
#define SPI_MEM_USER_REG (DR_REG_SPI_MEM_BASE + 0x18)
#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)
/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
* the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/
@ -483,7 +483,7 @@ extern "C" {
/** SPI_MEM_USER1_REG register
* SPI1 user1 register.
*/
#define SPI_MEM_USER1_REG (DR_REG_SPI_MEM_BASE + 0x1c)
#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c)
/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
* The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1).
@ -503,7 +503,7 @@ extern "C" {
/** SPI_MEM_USER2_REG register
* SPI1 user2 register.
*/
#define SPI_MEM_USER2_REG (DR_REG_SPI_MEM_BASE + 0x20)
#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)
/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
* The value of command.
*/
@ -522,7 +522,7 @@ extern "C" {
/** SPI_MEM_MOSI_DLEN_REG register
* SPI1 send data bit length control register.
*/
#define SPI_MEM_MOSI_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x24)
#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)
/** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
* The length in bits of write-data. The register value shall be (bit_num-1).
*/
@ -534,7 +534,7 @@ extern "C" {
/** SPI_MEM_MISO_DLEN_REG register
* SPI1 receive data bit length control register.
*/
#define SPI_MEM_MISO_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x28)
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28)
/** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
* The length in bits of read-data. The register value shall be (bit_num-1).
*/
@ -546,7 +546,7 @@ extern "C" {
/** SPI_MEM_RD_STATUS_REG register
* SPI1 status register.
*/
#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_MEM_BASE + 0x2c)
#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c)
/** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/
@ -579,7 +579,7 @@ extern "C" {
/** SPI_MEM_MISC_REG register
* SPI1 misc register
*/
#define SPI_MEM_MISC_REG (DR_REG_SPI_MEM_BASE + 0x34)
#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34)
/** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
* SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
* device, such as flash, external RAM and so on.
@ -614,7 +614,7 @@ extern "C" {
/** SPI_MEM_TX_CRC_REG register
* SPI1 TX CRC data register.
*/
#define SPI_MEM_TX_CRC_REG (DR_REG_SPI_MEM_BASE + 0x38)
#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38)
/** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
* For SPI1, the value of crc32.
*/
@ -626,7 +626,7 @@ extern "C" {
/** SPI_MEM_CACHE_FCTRL_REG register
* SPI1 bit mode control register.
*/
#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_MEM_BASE + 0x3c)
#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c)
/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
* For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
*/
@ -686,7 +686,7 @@ extern "C" {
/** SPI_MEM_W0_REG register
* SPI1 memory data buffer0
*/
#define SPI_MEM_W0_REG (DR_REG_SPI_MEM_BASE + 0x58)
#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58)
/** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -698,7 +698,7 @@ extern "C" {
/** SPI_MEM_W1_REG register
* SPI1 memory data buffer1
*/
#define SPI_MEM_W1_REG (DR_REG_SPI_MEM_BASE + 0x5c)
#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5c)
/** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -710,7 +710,7 @@ extern "C" {
/** SPI_MEM_W2_REG register
* SPI1 memory data buffer2
*/
#define SPI_MEM_W2_REG (DR_REG_SPI_MEM_BASE + 0x60)
#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60)
/** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -722,7 +722,7 @@ extern "C" {
/** SPI_MEM_W3_REG register
* SPI1 memory data buffer3
*/
#define SPI_MEM_W3_REG (DR_REG_SPI_MEM_BASE + 0x64)
#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64)
/** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -734,7 +734,7 @@ extern "C" {
/** SPI_MEM_W4_REG register
* SPI1 memory data buffer4
*/
#define SPI_MEM_W4_REG (DR_REG_SPI_MEM_BASE + 0x68)
#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68)
/** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -746,7 +746,7 @@ extern "C" {
/** SPI_MEM_W5_REG register
* SPI1 memory data buffer5
*/
#define SPI_MEM_W5_REG (DR_REG_SPI_MEM_BASE + 0x6c)
#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6c)
/** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -758,7 +758,7 @@ extern "C" {
/** SPI_MEM_W6_REG register
* SPI1 memory data buffer6
*/
#define SPI_MEM_W6_REG (DR_REG_SPI_MEM_BASE + 0x70)
#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70)
/** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -770,7 +770,7 @@ extern "C" {
/** SPI_MEM_W7_REG register
* SPI1 memory data buffer7
*/
#define SPI_MEM_W7_REG (DR_REG_SPI_MEM_BASE + 0x74)
#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74)
/** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -782,7 +782,7 @@ extern "C" {
/** SPI_MEM_W8_REG register
* SPI1 memory data buffer8
*/
#define SPI_MEM_W8_REG (DR_REG_SPI_MEM_BASE + 0x78)
#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78)
/** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -794,7 +794,7 @@ extern "C" {
/** SPI_MEM_W9_REG register
* SPI1 memory data buffer9
*/
#define SPI_MEM_W9_REG (DR_REG_SPI_MEM_BASE + 0x7c)
#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7c)
/** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -806,7 +806,7 @@ extern "C" {
/** SPI_MEM_W10_REG register
* SPI1 memory data buffer10
*/
#define SPI_MEM_W10_REG (DR_REG_SPI_MEM_BASE + 0x80)
#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80)
/** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -818,7 +818,7 @@ extern "C" {
/** SPI_MEM_W11_REG register
* SPI1 memory data buffer11
*/
#define SPI_MEM_W11_REG (DR_REG_SPI_MEM_BASE + 0x84)
#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84)
/** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -830,7 +830,7 @@ extern "C" {
/** SPI_MEM_W12_REG register
* SPI1 memory data buffer12
*/
#define SPI_MEM_W12_REG (DR_REG_SPI_MEM_BASE + 0x88)
#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88)
/** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -842,7 +842,7 @@ extern "C" {
/** SPI_MEM_W13_REG register
* SPI1 memory data buffer13
*/
#define SPI_MEM_W13_REG (DR_REG_SPI_MEM_BASE + 0x8c)
#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8c)
/** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -854,7 +854,7 @@ extern "C" {
/** SPI_MEM_W14_REG register
* SPI1 memory data buffer14
*/
#define SPI_MEM_W14_REG (DR_REG_SPI_MEM_BASE + 0x90)
#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90)
/** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -866,7 +866,7 @@ extern "C" {
/** SPI_MEM_W15_REG register
* SPI1 memory data buffer15
*/
#define SPI_MEM_W15_REG (DR_REG_SPI_MEM_BASE + 0x94)
#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94)
/** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@ -878,7 +878,7 @@ extern "C" {
/** SPI_MEM_FLASH_WAITI_CTRL_REG register
* SPI1 wait idle control register
*/
#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x98)
#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98)
/** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
* 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
* Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
@ -937,7 +937,7 @@ extern "C" {
/** SPI_MEM_FLASH_SUS_CTRL_REG register
* SPI1 flash suspend control register
*/
#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x9c)
#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9c)
/** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
* program erase resume bit, program erase suspend operation will be triggered when
* the bit is set. The bit will be cleared once the operation done.1: enable 0:
@ -1035,7 +1035,7 @@ extern "C" {
/** SPI_MEM_FLASH_SUS_CMD_REG register
* SPI1 flash suspend command register
*/
#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI_MEM_BASE + 0xa0)
#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xa0)
/** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
* Program/Erase suspend command.
*/
@ -1055,7 +1055,7 @@ extern "C" {
/** SPI_MEM_SUS_STATUS_REG register
* SPI1 flash suspend status register
*/
#define SPI_MEM_SUS_STATUS_REG (DR_REG_SPI_MEM_BASE + 0xa4)
#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xa4)
/** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
* The status of flash suspend, only used in SPI1.
*/
@ -1144,7 +1144,7 @@ extern "C" {
/** SPI_MEM_FLASH_WAITI_CTRL1_REG register
* SPI1 wait idle control register
*/
#define SPI_MEM_FLASH_WAITI_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xac)
#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xac)
/** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0;
* SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.
*/
@ -1153,7 +1153,7 @@ extern "C" {
#define SPI_MEM_WAITI_IDLE_DELAY_TIME_V 0x000003FFU
#define SPI_MEM_WAITI_IDLE_DELAY_TIME_S 0
/** SPI_MEM_WAITI_IDLE_DELAY_TIME_EN : R/W; bitpos: [10]; default: 0;
* Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable.
* Enable SPI1 wait idle gap time count function. 1: Enable. 0: Disable.
*/
#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN (BIT(10))
#define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_M (SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V << SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S)
@ -1163,7 +1163,7 @@ extern "C" {
/** SPI_MEM_INT_ENA_REG register
* SPI1 interrupt enable register
*/
#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_MEM_BASE + 0xc0)
#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0)
/** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
* The enable bit for SPI_MEM_PER_END_INT interrupt.
*/
@ -1210,7 +1210,7 @@ extern "C" {
/** SPI_MEM_INT_CLR_REG register
* SPI1 interrupt clear register
*/
#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_MEM_BASE + 0xc4)
#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4)
/** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
* The clear bit for SPI_MEM_PER_END_INT interrupt.
*/
@ -1257,7 +1257,7 @@ extern "C" {
/** SPI_MEM_INT_RAW_REG register
* SPI1 interrupt raw register
*/
#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_MEM_BASE + 0xc8)
#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8)
/** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
* command (0x7A) is sent and flash is resumed successfully. 0: Others.
@ -1301,7 +1301,7 @@ extern "C" {
#define SPI_MEM_MST_ST_END_INT_RAW_S 4
/** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
* The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
* chip is loosing power and RTC module sends out brown out close flash request to
* chip is losing power and RTC module sends out brown out close flash request to
* SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
* and MSPI returns to idle state. 0: Others.
*/
@ -1313,7 +1313,7 @@ extern "C" {
/** SPI_MEM_INT_ST_REG register
* SPI1 interrupt status register
*/
#define SPI_MEM_INT_ST_REG (DR_REG_SPI_MEM_BASE + 0xcc)
#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc)
/** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
* The status bit for SPI_MEM_PER_END_INT interrupt.
*/
@ -1360,7 +1360,7 @@ extern "C" {
/** SPI_MEM_DDR_REG register
* SPI1 DDR control register
*/
#define SPI_MEM_DDR_REG (DR_REG_SPI_MEM_BASE + 0xd4)
#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4)
/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
* 1: in ddr mode, 0 in sdr mode
*/
@ -1469,7 +1469,7 @@ extern "C" {
/** SPI_MEM_TIMING_CALI_REG register
* SPI1 timing control register
*/
#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_MEM_BASE + 0x180)
#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180)
/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
* The bit is used to enable timing auto-calibration for all reading operations.
*/
@ -1488,7 +1488,7 @@ extern "C" {
/** SPI_MEM_CLOCK_GATE_REG register
* SPI1 clk_gate register
*/
#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_MEM_BASE + 0x200)
#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200)
/** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Register clock gate enable signal. 1: Enable. 0: Disable.
*/
@ -1500,7 +1500,7 @@ extern "C" {
/** SPI_MEM_DATE_REG register
* Version control register
*/
#define SPI_MEM_DATE_REG (DR_REG_SPI_MEM_BASE + 0x3fc)
#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400;
* Version control register
*/

14
components/soc/esp32c61/include/soc/spi1_mem_struct.h
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@ -334,7 +334,7 @@ typedef union {
/** clk_mode : R/W; bitpos: [1:0]; default: 0;
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
* SPI clock is alwasy on.
* SPI clock is always on.
*/
uint32_t clk_mode:2;
/** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
@ -721,7 +721,7 @@ typedef union {
*/
uint32_t waiti_idle_delay_time:10;
/** waiti_idle_delay_time_en : R/W; bitpos: [10]; default: 0;
* Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable.
* Enable SPI1 wait idle gap time count function. 1: Enable. 0: Disable.
*/
uint32_t waiti_idle_delay_time_en:1;
uint32_t reserved_11:21;
@ -1149,7 +1149,7 @@ typedef union {
uint32_t reserved_5:5;
/** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
* chip is loosing power and RTC module sends out brown out close flash request to
* chip is losing power and RTC module sends out brown out close flash request to
* SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
* and MSPI returns to idle state. 0: Others.
*/
@ -1232,7 +1232,7 @@ typedef union {
} spi_mem_date_reg_t;
typedef struct {
typedef struct spi1_mem_dev_s {
volatile spi_mem_cmd_reg_t cmd;
volatile spi_mem_addr_reg_t addr;
volatile spi_mem_ctrl_reg_t ctrl;
@ -1250,7 +1250,7 @@ typedef struct {
volatile spi_mem_tx_crc_reg_t tx_crc;
volatile spi_mem_cache_fctrl_reg_t cache_fctrl;
uint32_t reserved_040[6];
volatile spi_mem_buffer_reg_t word[16];
volatile uint32_t data_buf[16];
volatile spi_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
volatile spi_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
volatile spi_mem_flash_sus_cmd_reg_t flash_sus_cmd;
@ -1270,11 +1270,11 @@ typedef struct {
volatile spi_mem_clock_gate_reg_t clock_gate;
uint32_t reserved_204[126];
volatile spi_mem_date_reg_t date;
} spi_mem_dev_t;
} spi1_mem_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
_Static_assert(sizeof(spi1_mem_dev_t) == 0x400, "Invalid size of spi1_mem_dev_t structure");
#endif
#ifdef __cplusplus

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