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411 Commits

Author SHA1 Message Date
morris
5f550b2a13 rmt,gptimer: don't support rc_fast clock source for c6 and h2 
The RC_FAST clock source on ESP32C6 and ESP32H2 can't be calibrated.
Which makes it impossible to work stable for peripherals like timer, RMT
 2022-09-14 14:40:28 +00:00
wanlei
96aa2792f8 spi_master:fix error when use spi_bus_add_device more than 3 device 
update gpio_sig at `spics_out` array in each spi_periph.c of chips later than s2
then `spi_bus_add_device` can correctly distribute gpio_signals for cs_signal

Closes https://github.com/espressif/esp-idf/issues/8876
 2022-09-05 12:10:22 +08:00
songruojing
9d515185d0 esp32c6: clean up existing soc files and header file inclusion in IDF to be compatible with the new chip 2022-09-01 12:28:06 +08:00
Song Ruo Jing
6a60ecf780 soc_caps: Introduce SOC_LEDC_SUPPORTED and SOC_I2C_SUPPORTED caps to IDF 
Wrap the ledc, i2c source files with the new caps in CMakeLists and linker.lf.
This could avoid potential source file not found warning during linking time.
 2022-08-31 20:43:22 +08:00
Michael (XIAO Xufeng)
746f4b814c uart: move frequency of clock sources out of HAL 2022-08-15 18:55:43 +00:00
Geng Yuchao
0a1d8c1e09 Fix soc caps define for all chips 2022-08-08 20:50:28 +08:00
jingli
ee3423834e kconfig: refactor xtal freq kconfig to common configuration item 2022-08-05 19:12:29 +08:00
wuzhenghui
7cb9304b65 Clean IRAM and DRAM address space conversion macros 2022-07-29 17:07:39 +08:00
wuzhenghui
21a4eda4d4 Use the entire sharedbuffer space as the heap of the D/IRAM attribute 2022-07-29 10:51:47 +08:00
morris
d94432fea8 systimer: refactor hal to accomodate more xtal choices 2022-07-25 16:08:52 +08:00
morris
741b031e83 soc: added SOC_TOUCH_SENSE_SUPPORTED macro 2022-07-22 00:12:36 +00:00
laokaiyao
edee3ee3cd i2s: add slot sequence table 
Closes: https://github.com/espressif/esp-idf/issues/9208

When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
 2022-07-21 15:52:39 +08:00
morris
4154eaec93 sdm: clean up soc/hal/ll code 2022-07-20 14:59:50 +08:00
Armando (Dou Yiwen)
9f6f61345b Merge branch 'feature/adc_driver_ng' into 'master' 
ADC Driver NG

Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979

See merge request espressif/esp-idf!17960
 2022-07-19 21:28:31 +08:00
Cao Sen Miao
53580a62b5 I2C: Fullfill the I2C clock tree, and support 26M XTAL on ESP32-C2 2022-07-19 11:41:42 +08:00
Armando
5b523a3313 esp_adc: new esp_adc component and adc drivers 2022-07-15 18:31:00 +08:00
Jiang Jiang Jian
3630713e5f Merge branch 'docs/esp32c2_sys_feature_api_guides' into 'master' 
docs: update system API-guides for ESP32-C2

Closes IDF-4202, IDF-4213, and IDF-4222

See merge request espressif/esp-idf!18979
 2022-07-12 10:59:12 +08:00
Marius Vikhammer
d62421619c docs: update system API-guides for ESP32-C2 2022-07-12 09:32:43 +08:00
songruojing
b3d8db3ae2 bootloader, esp_system: esp32c2 console uart to support 26MHz xtal 
Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h
 2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
5b54ae76d4 esp_timer, hal: add support for non-integer systimer frequency 
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:

1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
   actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.

For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.

This introduced two possible issues:

1. Overflow when multiplying systimer counter by 5
   - Should not be an issue, since systimer counter is 52-bit, so
     counter * 5 is no more than 55-bit.
2. The code needs to perform:
   - divide by 5: when converting from microseconds to ticks
   - divide by 52: when converting from ticks to microseconds
   The latter potentially introduces a performance issue for the
   esp_timer_get_time function.
 2022-07-11 12:24:37 +08:00
GengYuchao
d145c337e0 Enable rpa_moudle reset function 2022-07-05 20:50:31 +08:00
morris
7863c1bc45 Merge branch 'bugfix/fix_rtc_freq_err_for_h2_beta1' into 'master' 
Bugfix/fix rtc freq err for h2 beta1

See merge request espressif/esp-idf!18682
 2022-07-04 16:46:17 +08:00
Omar Chebib
cd48baf979 Refactor: move regi2c_*.h header files from esp_hw_support to soc component 
When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
 2022-06-30 09:40:44 +00:00
GengYuchao
10fd1daa10 Add ETM clk gate defines for h2 2022-06-30 17:02:00 +08:00
Armando
31b3f31ef4 ext_mem: make memory region check strict 2022-06-28 14:17:44 +08:00
Sachin Parekh
6cfc9c365f esp32h2: Enable ECC accelerator 2022-06-23 12:59:13 +05:30
Ivan Grokhotkov
3973db7664
soc: make register access macros compatible with C++20 
In C++20, using the result of an assignment to a 'volatile' value is
deprecated.

Breaking change: register "setter" or modification macros can no
longer be used as expressions.

Closes https://github.com/espressif/esp-idf/issues/9170
 2022-06-17 18:09:22 +02:00
Omar Chebib
752026a174 Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master' 
G0: RISC-V targets have now an independent G0 layer

See merge request espressif/esp-idf!17926
 2022-06-16 11:53:39 +08:00
laokaiyao
28b8fc6a7e i2s: update documents for driver-NG 2022-06-15 10:30:04 +08:00
Darian
e213e66ba3 Merge branch 'refactor/esp_hw_support_cpu' into 'master' 
esp_hw_support: Add new esp_cpu.h abstraction

Closes IDF-4769

See merge request espressif/esp-idf!17091
 2022-06-14 21:11:30 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
 2022-06-14 15:00:53 +08:00
Darian Leung
61eb7baa6b esp_hw_support: Add esp_cpu.h abstraction and API 
This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:

- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)

Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
        builds for esp_cpu.h
 2022-06-14 14:30:58 +08:00
songruojing
c8752cee6a clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem 2022-06-13 17:47:50 +08:00
Cao Sen Miao
6589daabb9 MMU: Add configurable mmu page size support on ESP32C2 2022-06-08 19:34:31 +08:00
Geng Yuchao
8012af37d1 Fix soc caps for BT 2022-06-03 21:45:40 +08:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
Island
74b7a3fc83 Merge branch 'feature/final_h2_bluedroid_skc_common' into 'master' 
Feature/final h2 bluedroid skc common

See merge request espressif/esp-idf!17710
 2022-05-30 21:20:52 +08:00
Jiang Jiang Jian
2bc5d58807 Merge branch 'feature/support_sleep_for_esp32c2' into 'master' 
esp32c2: support power management

Closes IDF-4440 and IDF-4617

See merge request espressif/esp-idf!18174
 2022-05-30 17:57:18 +08:00
satish.solanke
3a42007680 Bluedroid porting changes for esp32h2 
created common Kconfig for common flag of nimbble and Bluedroid

fix compile error

created common cfg file for controller

fix the compilation error on tip of master

added common controller flags and fixed compilation error

sdkconfig rename for target specific
 2022-05-30 08:42:45 +00:00
Jiang Jiang Jian
f3922f1b7f Merge branch 'feature/flash_mmap_refactor' into 'master' 
flash mmap: abstract R/W of MMU table instead of reg access

See merge request espressif/esp-idf!16882
 2022-05-29 13:56:37 +08:00
jingli
ae127b04cd fix ld err since esp32c2 do not suport config gpio of spi flash via efuse 2022-05-27 19:29:38 +08:00
songruojing
74c99a8a07 rtc_clk: Add alias for the clock tree related enum and macros for backwards compatibility 2022-05-24 22:59:51 +08:00
songruojing
729d70129a clk_tree: add initial docs for clock tree 2022-05-24 22:59:51 +08:00
morris
b26cd91537 doc: added clk_tree definitions to doc 2022-05-24 22:59:51 +08:00
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in 
soc/clk_tree_defs.h
 2022-05-24 22:59:41 +08:00
jiangguangming
42bc0b0643 soc: remove unused MMU related macros 2022-05-20 16:46:28 +08:00
Michael (XIAO Xufeng)
234628b3ea pm: putting dbias and pd_cur code into same function 2022-05-14 02:35:11 +08:00
Jing Li
ac0d16cdc8 Merge branch 'bugfix/fix_cannot_lslp_again_after_ulp_wakeup' into 'master' 
sleep: fix cannot lightsleep again after a wakeup from ULP

Closes IDFGH-4396

See merge request espressif/esp-idf!17970
 2022-05-13 22:25:23 +08:00
jingli
abb6bb1181 esp_hw_support/sleep: fix cannot enable sleep reject in some cases 
When enable sleep reject before this fix, we have two limitations:
1. it must be light sleep
2. RTC GPIO wakeup source must be set

We require light sleep because `esp_deep_sleep_start` function has
been declared with "noreturn" attribute, So developers don't expect
that this function may return (due to an error or a sleep reject).
But the requirement for RTC GPIO wakeup source is not reasonable for
all chips. This requirement exists because ESP32 only supports RTC GPIO
and SDIO sleep reject sources. But later chips support all sleep reject
sources.

This fix brings the following changes:
for ESP32: RTC GPIO and SDIO sleep reject sources can be enabled
           when corresponding wakeup source is set.

for later chips: all sleep reject sources can be enabled when
                 corresponding wakeup source is set.
 2022-05-12 19:09:57 +08:00
Marius Vikhammer
c8617fe965 docs: fix all doxygen warnings 
Doxygen warnings would previously not result in a failed pipeline.
Fixed this as well as all current warnings.
 2022-05-12 14:50:03 +08:00
Michael (XIAO Xufeng)
36074b9812 pm: add powerdown for int_8m on ESP32-C2 and ESP32-H2 
Also move the xtal fpu logic to sleep_modes.c
 2022-05-11 11:36:34 +08:00
morris
523c51818c Merge branch 'feature/c2_soc_hwsupport_code' into 'master' 
ESP32-C2 (729) RTC update (Clock, PM)

Closes IDF-3833 and IDF-4874

See merge request espressif/esp-idf!17311
 2022-05-11 11:23:57 +08:00
zlq
6336f8191e C2 rtc code 2022-05-09 17:50:54 +08:00
morris
722fde218d uart: add default source clock for all targets 2022-05-09 11:26:30 +08:00
Armando (Dou Yiwen)
03aeac1dde Merge branch 'refactor/adc_hal_common_layer' into 'master' 
adc: create common adc hal layer

See merge request espressif/esp-idf!17577
 2022-05-08 15:45:56 +08:00
Armando
49747bb486 adc: create common adc hal layer 2022-05-07 19:20:44 +08:00
morris
2fb43820c2 driver_ng: implement new rmt driver 
The legacy driver can't handle the breaking change between esp chips

very well.

And it's not elegant to extend new feature like DMA, ETM.

The new driver can return a opaque handle for each RMT channel.

An obvious transaction concept was also introduced.

TX and RX functionalities are splited out.
 2022-05-07 10:34:50 +00:00
morris
3f66660444 Merge branch 'feature/bringup_esp32c2eco1' into 'master' 
esp32c2：ECO1 ROM update

Closes IDF-4933

See merge request espressif/esp-idf!17723
 2022-05-06 18:06:26 +08:00
Simon
0b00831703 Merge branch 'bugfix/i2c_timeout_issue' into 'master' 
I2C: Patch for solving watchdog timeout issue

Closes IDFGH-6923, IDFGH-6463, and IDFGH-5558

See merge request espressif/esp-idf!17956
 2022-05-06 10:38:38 +08:00
Armando (Dou Yiwen)
76be0c2624 Merge branch 'bugfix/fix_esp32_mmu_init_issue' into 'master' 
mmu: add ll functions for mmu unmap

Closes OCD-526 and IDF-4962

See merge request espressif/esp-idf!17868
 2022-05-05 22:21:18 +08:00
wuzhenghui
17b3d139d5 hal: use systimer HAL IMPL in ESP32C2 ROM 2022-05-05 17:41:11 +08:00
Cao Sen Miao
9a9f10e4c9 I2C: patch for solving watchdog timeout issue 2022-05-05 14:36:49 +08:00
morris
9ab4abfb46 hw_support: move rtc_ctrl from driver to hw_support 2022-04-29 14:28:09 +08:00
Armando
b748a4fe5e mmu: improve vaddr range check 2022-04-27 11:35:07 +08:00
Armando
e09787d851 mmu: fix macro MMU_ENTRY_NUM and add new macro MMU_MAX_PADDR_PAGE_NUM 2022-04-27 11:35:07 +08:00
Cao Sen Miao
4418a855ba spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2 2022-04-26 15:22:37 +08:00
morris
4280164be4 rmt: add more clock source caps 2022-04-21 13:59:47 +00:00
morris
373d9b3dbc Merge branch 'feature/default_clk_for_gptimer' into 'master' 
clk_tree: added default clock source for peripherals (GPTimer, RMT, LCD, TempSensor)

Closes IDF-4894

See merge request espressif/esp-idf!17759
 2022-04-19 18:02:40 +08:00
songruojing
534346f4bb ledc: Provide support for esp32c2 and esp32h2 
LEDC examples, unit test, and programming guide are all updated.
 2022-04-14 08:15:14 +00:00
morris
f32a89826c clk_tree: added default clock source for peripheral 2022-04-14 15:44:56 +08:00
songruo
60bb5c913d clk_tree: prework of introducing clk subsystem control 
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
   upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
   Modify the NGed drivers to adopt new clock ids
 2022-04-11 12:09:06 +08:00
Mahavir Jain
4350e6fef8 Merge branch 'feature/security_soc_capabilities' into 'master' 
soc: add security features related capabilities

Closes IDF-4854

See merge request espressif/esp-idf!17632
 2022-04-01 21:55:59 +08:00
Song Ruo Jing
e13bb580c7 Merge branch 'refactor/gpio_unit_test' into 'master' 
gpio: Clean up unit tests and enable ci ut on some previously disabled test cases

Closes IDF-4620

See merge request espressif/esp-idf!17417
 2022-04-01 18:38:19 +08:00
Mahavir Jain
74005ed2f5 soc: add capability macros for security features 
- Security features covers "secure boot", "flash encryption" etc.
- ECO revision specific modifications still need to be handled
through kconfig itself, as soc_caps.h is processed before ECO revision
selection
- This will simplify addition of security features for newer chips by
using these SOC capability macros
 2022-04-01 09:38:34 +00:00
songruojing
8d84033b8c gpio: Clean up unit tests and enable ci ut on some previously disabled test cases 
Eliminate UT_T1_GPIO runner requirement by routing internally through gpio matrix and by setting gpio pins to GPIO_MODE_INPUT_OUTPUT mode for all interrupt related test cases.
 2022-03-30 15:11:08 +08:00
wuzhenghui
4652f77a7c esp32h2beta2:update rom layout table 2022-03-29 14:13:06 +08:00
Kevin (Lao Kaiyao)
ba9d3fe819 Merge branch 'refactor/i2s_major_refactoring_for_ng' into 'master' 
🔨i2s: Major refactoring for driver-NG

Closes IDF-4781 and IDF-4779

See merge request espressif/esp-idf!17484
 2022-03-23 15:32:46 +08:00
laokaiyao
f17edba20b i2s: extract std/pdm/tdm modes 
Type structures of these modes are defined. Driver and HAL layer are modified to fit these concepts.
 2022-03-22 10:14:45 +08:00
Mahavir Jain
bcc4883c25 soc: add capability macros for crypto peripherals 
Closes IDF-4790
 2022-03-22 02:06:30 +00:00
Armando (Dou Yiwen)
36457b1346 Merge branch 'refactor/adc_unify_adc_unit' into 'master' 
adc: adc single driver NG pre-step - unify adc_ll_num_t and adc_unit_t

See merge request espressif/esp-idf!17408
 2022-03-18 20:29:36 +08:00
Armando
386363cafd adc: unify adc_ll_num_t and adc_unit_t 2022-03-18 11:36:50 +08:00
Rahul Tank
f376bb5d05 Add support in Nimble for ESP32H2 2022-03-14 11:57:53 +05:30
Michael (XIAO Xufeng)
aab535fe4a Merge branch 'bugfix/regi2c_ctrl_spinlock_s2' into 'master' 
hw_support: fixed regi2c not protected by lock on ESP32S2

See merge request espressif/esp-idf!16653
 2022-03-13 02:47:53 +08:00
Michael (XIAO Xufeng)
d5bdf95580 hw_support: fixed regi2c not protected by lock on ESP32S2 2022-03-13 00:24:08 +08:00
Armando (Dou Yiwen)
6ed3ffbbf1 Merge branch 'refactor/remove_redundant_rom_cache_dependency' into 'master' 
cache: remove redundant rom cache dependency in bootloader

Closes IDF-4523

See merge request espressif/esp-idf!17077
 2022-03-12 10:11:39 +08:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
morris
9f55712c03 rmt: document and improve LL driver 2022-03-09 10:58:12 +08:00
Simon
4bf4a020a6 Merge branch 'refactor/abstract_temperature_sensor' into 'master' 
temperature_sensor: Refactor temperature sensor to new APIs (follow rule of driverNG) and support esp32s3

Closes IDF-3665, IDF-3367, and IDF-1793

See merge request espressif/esp-idf!16787
 2022-03-07 20:17:39 +08:00
Cao Sen Miao
b248046bcb Temperature_sensor: Create new temperature sensor API 2022-03-04 18:13:35 +08:00
songruojing
c8c137f2b7 esp32h2: support GPIO peripheral, IO_MUX, GPIO matrix. 
Generic GPIO example is supported as well.
 2022-03-04 11:25:05 +08:00
songruojing
24a60c12c6 uart: Provide support for esp32c2 and esp32h2 
UART examples, unit test, and programming guide are all updated.
 2022-03-02 11:29:13 +08:00
laokaiyao
7da023ceae i2c: support esp32c2 2022-02-23 15:19:37 +08:00
songruojing
c1dedb33fa esp_system: replace the range comparsion for reset reason in perip clk init with specific reset reason check, also add a test case in LEDC to check for the perip clk not being disabled after cpu reset 2022-02-09 15:54:34 +08:00
Michael (XIAO Xufeng)
c1b30491dd Merge branch 'feature/esp32c3_uart_add_wakeup_event' into 'master' 
UART: add uart wakeup event for esp32c3 and esp32s3

Closes IDF-3416

See merge request espressif/esp-idf!14482
 2022-02-04 17:23:29 +00:00
Mahavir Jain
68f67db984 Merge branch 'feature/efuse_esp8684' into 'master' 
efuse(esp32c2): Support eFuse key APIs

Closes IDF-3818

See merge request espressif/esp-idf!16290
 2022-02-01 11:30:00 +00:00
KonstantinKondrashov
ebdc52d4e2 efuse(esp32c2): Support eFuse key APIs 2022-02-01 17:30:31 +08:00
Song Ruo Jing
3821a09f83 Merge branch 'bugfix/ledc_consecutive_fade' into 'master' 
ledc: Bugfixes for issues related to fade protection on ESP32

Closes IDFGH-4918 and IDFGH-5565

See merge request espressif/esp-idf!14568
 2022-01-26 06:00:59 +00:00
laokaiyao
c4cfb654d2 uart: support light sleep on esp32s3 2022-01-25 17:43:02 +08:00
songruojing
68e12f7092 ledc: Add ledc_fade_stop API to support stopping the fade operation. 
Note that ESP32 cannot support this new feature.
 2022-01-25 11:19:20 +08:00
Omar Chebib
bb730292d4 i2c: fix the controller count in the header description 
Closes https://github.com/espressif/esp-idf/issues/8133
 2022-01-13 18:25:41 +08:00
laokaiyao
cd10bb7fa2 esp32h2: fix apb freq bug 2022-01-10 12:43:31 +08:00
morris
24acdf23ee soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
morris
8cdcb4e291 rmt: move RMT item definition from soc to driver 2022-01-06 21:43:12 +08:00
Michael (XIAO Xufeng)
46f8d868d3 soc: updated soc_caps about rtc_io and the format 2022-01-01 03:13:45 +08:00
laokaiyao
af4e448928 i2s: impove the clock division calculation 
Reported from: https://esp32.com/viewtopic.php?f=25&t=24542&p=87595#p87595
 2021-12-29 10:13:13 +08:00
morris
b170aba93a timer: fix wrong kconfig soc caps 2021-12-23 11:39:32 +08:00
morris
e8c5f8656b fast_gpio: fix wrong initial occupy mask 2021-12-17 15:49:44 +08:00
Armando
4dc0d6b2fe adc: support adc dma driver on all chips 2021-12-16 00:19:15 +00:00
Cao Sen Miao
e81841318f CI: Enable ESP8684 build stage CI on master 2021-12-13 19:18:47 +08:00
Cao Sen Miao
463cf2cf1c ESP8684: Clean up ESP8684 code, remove useless code, update headers 2021-12-09 18:36:39 +08:00
Marius Vikhammer
97d11c709d soc: Merge soc_caps for H2 rev1 and rev2 
These files were identical.
 2021-12-06 12:37:11 +08:00
Marius Vikhammer
c6d60615c6 build-system: include soc_caps defines into kconfig 
Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into
a format that can be included in kconfig.
 2021-12-06 12:37:07 +08:00
laokaiyao
f21020ce04 esp32h2: update reg and struct for beta2 2021-11-24 12:34:17 +08:00
wuzhenghui
388615add0 update esp32h2beta2 chip_id to 14 2021-11-24 12:30:43 +08:00
wuzhenghui
968c42d88c 822 FPGA rnv init 2021-11-24 12:30:17 +08:00
Omar Chebib
aa2ca7dd94 LEDC: improved support for ESP32-C3 and refactored divisor calculation 
As ESP32C3 does not have support for REF_TICK source clock, it is now not
possible to select it anymore.
Auto cfg clock has been improved for all boards.
 2021-11-11 12:21:15 +08:00
morris
83d16aa00c gdma: support IRAM interrupt 2021-11-08 16:14:51 +08:00
Cao Sen Miao
36f6d16b8d ESP8684: add soc, riscv, newlib support 2021-11-06 17:33:44 +08:00
Wu Zheng Hui
001c29b077 bootloader: Simplify multi-chip control logic of the cache 2021-10-21 18:09:37 +08:00
morris
e2275b1f63 gptimer: clean up hal and ll for driver-ng 2021-10-20 18:40:08 +08:00
Jiang Jiang Jian
f5ae8b0533 Merge branch 'feature/ledc_use_rtc8m_or_xtal_lightsleep' into 'master' 
support RTC8M and XTAL power domain in light sleep mode

Closes IDF-3419

See merge request espressif/esp-idf!15152
 2021-09-27 04:02:29 +00:00
morris
20ef511d0a Merge branch 'bugfix/fix_reg_name_charactor_err' into 'master' 
bugfix: fix reg name character error

See merge request espressif/esp-idf!14169
 2021-09-18 07:10:57 +00:00
Jiang Jiang Jian
3b48b7e663 Merge branch 'Fix/update_reset_reason' into 'master' 
update reset reason for c3/s3/h2

See merge request espressif/esp-idf!14747
 2021-09-18 07:03:50 +00:00
Wu Zheng Hui
85651b4791 efuse: remove DIS_RTC_RAM_BOOT efuse bit 2021-09-18 14:58:43 +08:00
Wu Zheng Hui
27241e8213 Merge branch 'bugfix/fix_efuse_err_address' into 'master' 
fix efuse err address in block0

See merge request espressif/esp-idf!14790
 2021-09-17 02:17:09 +00:00
Wu Zheng Hui
1080e4f6a2 rename APB_CTRL ro SYS_CON 
save
 2021-09-16 20:57:57 +08:00
wuzhenghui
61b2c2d458 fix h2 efuse err address in block0 2021-09-16 20:08:59 +08:00
Li Shuai
58292a7d22 Power Management: add XTAL power domain to control whether external 40MHz xtal is powered down during sleep 2021-09-16 14:43:43 +08:00
Li Shuai
f5b39a7cde esp_hw_support: No voltage drop during light sleep to ensure stable output clock of rtc8m oscillator 2021-09-16 14:40:46 +08:00
wuzhenghui
b2c028085a fix reg name character error 2021-09-15 21:51:20 +08:00
Armando (Dou Yiwen)
13b63cd9d2 Merge branch 'feature/support_adc_calibration_s3' into 'master' 
adc: support adc calibration on s3

Closes IDF-1950, IDF-3730, and IDF-3036

See merge request espressif/esp-idf!15031
 2021-09-14 08:51:03 +00:00
morris
502e132e5d Merge branch 'feature/fast_gpio_c3' into 'master' 
fast gpio support on esp32-c3

Closes IDF-3783

See merge request espressif/esp-idf!14986
 2021-09-14 06:09:34 +00:00
Armando
c45c6f52f1 adc: support adc efuse-based calibration on esp32s3 2021-09-14 11:42:50 +08:00
Li Shuai
e44ead5356 Power Management: add RTC8M power domain to control whether internal 8m oscillator is powered down during sleep 2021-09-13 17:36:54 +08:00
morris
6cec256a34 fast_gpio: driver support on esp32c3 2021-09-06 19:39:09 +08:00
Sachin Parekh
fd5a7df404 esp32h2: Replicated HMAC JTAG downstream enable mode implementation 2021-09-06 11:06:50 +05:30
morris
2e0ffbd543 Merge branch 'bugfix/fix-driver-8_16bit-reg-access' into 'master' 
bugfix/driver: fix and cleanup soc/ll stuffs

Closes IDF-3722

See merge request espressif/esp-idf!14829
 2021-08-30 10:27:05 +00:00
Michael (XIAO Xufeng)
d910d42a8d Merge branch 'bugfix/soc_interrupt_source' into 'master' 
soc: remove outdated description of interrupts on RISCV CPUs

See merge request espressif/esp-idf!14974
 2021-08-30 09:38:24 +00:00
Michael (XIAO Xufeng)
59cedcb748 soc: remove outdated description of interrupts on RISCV CPUs 2021-08-30 17:38:16 +08:00
SalimTerryLi
892f5e7df3
timer_group: fix wrongly generated reg header that introduced in 443845fd54 2021-08-30 13:51:25 +08:00
SalimTerryLi
874a720286
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one 
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
 2021-08-30 13:50:58 +08:00
wuzhenghui
32abe5ce42 fix apb freq err temporarily 2021-08-27 19:59:33 +08:00
sly
11dfd802e0 esp32h2: add rtc clock support 2021-08-26 11:25:39 +08:00
wuzhenghui
6ab495b4dc esp32h2: chip env support 
brownout init fixed
 2021-08-25 11:02:47 +08:00
morris
0c41837b06 Merge branch 'refactor/timer_group-reg_file-update' into 'master' 
refactor/timer_group update reg headers for c3 and s2

Closes IDF-3690

See merge request espressif/esp-idf!14761
 2021-08-23 04:30:59 +00:00
morris
bb87fd8f08 Merge branch 'refactor/pcnt_driver_esp32s3' into 'master' 
pcnt: soc update and hal refactor

See merge request espressif/esp-idf!14698
 2021-08-20 04:23:15 +00:00
SalimTerryLi
443845fd54
timer_group: update reg headers for c3&s2&h2 and fix direct 8/16bit reg access 2021-08-19 18:56:32 +08:00
wuzhenghui
f913a10a22 update reset reason for c3/s3/h2 2021-08-13 17:45:53 +08:00
morris
1656cee69d i2s: correct soc info 
1. remove non-exist I2S instance
2. update soc_caps.h, i2s_ll.h
 2021-08-10 21:06:59 +08:00
suda-morris
9920271c21 pcnt: update pcnt soc data for all targets 2021-08-10 17:19:21 +08:00
Michael (XIAO Xufeng)
947980ecac Merge branch 'bugfix/uart_set_pin_use_iomux' into 'master' 
uart: uart_set_pin function will now use IOMUX whenever possible

Closes IDF-3183

See merge request espressif/esp-idf!14318
 2021-08-05 04:17:29 +00:00
Omar Chebib
779e7400b0 uart: uart_set_pin function will now use IOMUX whenever possible 
By using IOMUX instead of GPIO Matrix for UART, it is now possible
on ESP32 boards to use the UART as a wake up source even if it is
not used as a console.
For other boards where this issue was not present, using IOMUX has
the advantage to be faster than using GPIO matrix, so a highest
baudrate can be used
 2021-08-04 12:48:30 +08:00
laokaiyao
3c57a6ac36 driver/i2s: refactor ll and hal 2021-08-04 10:20:03 +08:00
laokaiyao
d51b85989b doc/i2s: update i2s programming guide on s3 & c3 2021-08-04 10:20:03 +08:00
Konstantin Kondrashov
4972605b16 esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt 2021-08-03 14:35:29 +08:00
Cao Sen Miao
69ad24c943 temp_sensor: add docs for esp32c3 2021-07-21 13:34:52 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Shu Chen
75bd02bd46 esp32h2: add some more fixes and TODOs 2021-07-01 20:36:39 +08:00
Shu Chen
ee23a489b9 esp32h2: code clean up 2021-07-01 19:53:50 +08:00
Shu Chen
205cd469e9 esp32h2: update driver/hal/soc components to support esp32h2 2021-07-01 19:53:11 +08:00
Shu Chen
983cca8b27 esp32h2: copy driver/hal/soc components from esp32c3 
Copy the esp32c3 code without any change:
 * components/driver/esp32h2
 * components/esp32h2
 * components/hal/esp32h2
 * components/soc/esp32h2
 2021-07-01 19:53:11 +08:00