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esp32h2beta2:update rom layout table

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wuzhenghui 2022-03-17 11:47:22 +08:00 committed by laokaiyao
parent 7968230e76
commit 4652f77a7c
4 changed files with 8 additions and 43 deletions
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47
components/esp_rom/include/esp32h2/rom/rom_layout.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -20,9 +12,6 @@
extern "C" {
#endif
#define SUPPORT_BTDM 1
#define SUPPORT_WIFI 1
/* Structure and functions for returning ROM global layout
*
* This is for address symbols defined in the linker script, which may change during ECOs.
@ -32,8 +21,6 @@ typedef struct {
void *dram0_rtos_reserved_start;
void *stack_sentry;
void *stack;
void *stack_sentry_app;
void *stack_app;
/* BTDM data */
void *data_start_btdm;
@ -47,31 +34,9 @@ typedef struct {
void *bss_start_interface_btdm;
void *bss_end_interface_btdm;
/* Other DRAM ranges */
#if SUPPORT_BTDM || SUPPORT_WIFI
void *dram_start_phyrom;
void *dram_end_phyrom;
#endif
#if SUPPORT_WIFI
void *dram_start_coexist;
void *dram_end_coexist;
void *dram_start_net80211;
void *dram_end_net80211;
void *dram_start_pp;
void *dram_end_pp;
void *data_start_interface_coexist;
void *data_end_interface_coexist;
void *bss_start_interface_coexist;
void *bss_end_interface_coexist;
void *data_start_interface_net80211;
void *data_end_interface_net80211;
void *bss_start_interface_net80211;
void *bss_end_interface_net80211;
void *data_start_interface_pp;
void *data_end_interface_pp;
void *bss_start_interface_pp;
void *bss_end_interface_pp;
#endif
void *dram_start_usbdev_rom;
void *dram_end_usbdev_rom;
void *dram_start_uart_rom;

1
components/heap/port/memory_layout_utils.c
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@ -17,6 +17,7 @@
#define ROM_HAS_LAYOUT_TABLE 1
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rom_layout.h"
#define ROM_HAS_LAYOUT_TABLE 1
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/rom_layout.h"
#define ROM_HAS_LAYOUT_TABLE 1

2
components/soc/esp32h2/include/soc/soc.h
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@ -208,7 +208,7 @@
#define SOC_DEBUG_HIGH 0x28000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fcebf10
#define SOC_ROM_STACK_START 0x3fcdf120
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.

1
tools/ci/check_copyright_ignore.txt
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@ -586,7 +586,6 @@ components/esp_rom/include/esp32h2/rom/libc_stubs.h
components/esp_rom/include/esp32h2/rom/lldesc.h
components/esp_rom/include/esp32h2/rom/md5_hash.h
components/esp_rom/include/esp32h2/rom/miniz.h
components/esp_rom/include/esp32h2/rom/rom_layout.h
components/esp_rom/include/esp32h2/rom/rsa_pss.h
components/esp_rom/include/esp32h2/rom/sha.h
components/esp_rom/include/esp32h2/rom/tjpgd.h