alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

soc: add capability macros for security features

Browse Source 
- Security features covers "secure boot", "flash encryption" etc.
- ECO revision specific modifications still need to be handled
through kconfig itself, as soc_caps.h is processed before ECO revision
selection
- This will simplify addition of security features for newer chips by
using these SOC capability macros
This commit is contained in:
Mahavir Jain 2022-03-31 17:43:50 +05:30 committed by BOT
parent 813fa1e4ae
commit 74005ed2f5
12 changed files with 241 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@ -75,10 +75,6 @@ config SOC_CCOMP_TIMER_SUPPORTED
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
@ -115,6 +111,14 @@ config SOC_SHA_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_ADC_RTC_CTRL_SUPPORTED
bool
default y
@ -571,6 +575,14 @@ config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_SECURE_BOOT_V1
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32

12
components/soc/esp32/include/soc/soc_caps.h
View File

@ -78,7 +78,6 @@
#define SOC_CPU_CORES_NUM 2
#define SOC_ULP_SUPPORTED 1
#define SOC_CCOMP_TIMER_SUPPORTED 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
@ -88,6 +87,8 @@
#define SOC_AES_SUPPORTED 1
#define SOC_MPI_SUPPORTED 1
#define SOC_SHA_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1
#define SOC_SECURE_BOOT_SUPPORTED 1
/*-------------------------- ADC CAPS ----------------------------------------*/
/**
@ -319,6 +320,15 @@
#define SOC_AES_SUPPORT_AES_192 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- Secure Boot CAPS----------------------------*/
/*
* ESP32 ECO3 revision also supports `SOC_SECURE_BOOT_V2_RSA` but for that we will need selected ECO
* version from `Kconfig`, which is not possible while generating `Kconfig.soc_caps.in` from this header.
* Hence, for now we are handling this special capability in bootloader "security" configuration itself.
*/
#define SOC_SECURE_BOOT_V1 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)

40
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -35,14 +35,6 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
bool
default y
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default n
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default n
@ -59,14 +51,6 @@ config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default n
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default n
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_SHA_SUPPORTED
bool
default n
@ -75,6 +59,14 @@ config SOC_ECC_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_ADC_DIG_CTRL_SUPPORTED
bool
default y
@ -431,10 +423,26 @@ config SOC_TOUCH_SENSOR_NUM
int
default 0
config SOC_SECURE_BOOT_V2_ECC
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default n
config SOC_UART_NUM
int
default 2

13
components/soc/esp32c2/include/soc/soc_caps.h
View File

@ -33,16 +33,15 @@
#define SOC_WIFI_SUPPORTED 0 // Enable during bringup, IDF-3905
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 0
#define SOC_EFUSE_KEY_PURPOSE_FIELD 0
#define SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK 1
#define SOC_RTC_FAST_MEM_SUPPORTED 0
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 0
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_SHA_SUPPORTED 0 // This will be enabled with IDF-3830
#define SOC_ECC_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1
#define SOC_SECURE_BOOT_SUPPORTED 1
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
@ -224,8 +223,14 @@
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0U) /*! No touch sensors on ESP32-C2 */
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_ECC 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 0 // This will be enabled with IDF-3899
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C2 has 2 UARTs

48
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -43,10 +43,6 @@ config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_XT_WDT_SUPPORTED
bool
default y
@ -59,14 +55,6 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@ -79,10 +67,6 @@ config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default n
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
@ -119,6 +103,14 @@ config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
@ -607,10 +599,34 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_UART_NUM
int
default 2

17
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -35,16 +35,12 @@
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_WIFI_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
#define SOC_SIGMADELTA_SUPPORTED 1
@ -54,6 +50,11 @@
#define SOC_SHA_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1
/* Secure boot is only supported in ESP32-C3 revision > ECO3. We check ECO revision in
* bootloader "security" configuration and accordingly prevent its usage for ECO2 and
* earlier revisions */
#define SOC_SECURE_BOOT_SUPPORTED 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
@ -291,8 +292,16 @@
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C3 has 2 UARTs

40
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -47,10 +47,6 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@ -67,10 +63,6 @@ config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default n
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
@ -107,6 +99,14 @@ config SOC_ECC_SUPPORTED
bool
default n
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
@ -591,10 +591,34 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_UART_NUM
int
default 2

13
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -44,12 +44,10 @@
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
#define SOC_SIGMADELTA_SUPPORTED 1
@ -59,6 +57,9 @@
#define SOC_HMAC_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_ECC_SUPPORTED 0 // This will be enabled with IDF-3397
#define SOC_FLASH_ENC_SUPPORTED 1
#define SOC_SECURE_BOOT_SUPPORTED 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
@ -302,8 +303,16 @@
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-H2 has 2 UARTs

56
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -59,14 +59,6 @@ config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@ -79,14 +71,6 @@ config SOC_CACHE_SUPPORT_WRAP
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
@ -103,10 +87,6 @@ config SOC_XT_WDT_SUPPORTED
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
@ -143,6 +123,14 @@ config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_ADC_RTC_CTRL_SUPPORTED
bool
default y
@ -707,10 +695,38 @@ config SOC_AES_SUPPORT_GCM
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 64
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_AES_CRYPTO_DMA
bool
default y

16
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -53,18 +53,13 @@
#define SOC_ULP_SUPPORTED 1
#define SOC_CCOMP_TIMER_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
#define SOC_SIGMADELTA_SUPPORTED 1
@ -74,6 +69,8 @@
#define SOC_SHA_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1
#define SOC_SECURE_BOOT_SUPPORTED 1
/*-------------------------- ADC CAPS ----------------------------------------*/
@ -332,8 +329,17 @@
#define SOC_AES_SUPPORT_DMA (1)
#define SOC_AES_SUPPORT_GCM (1)
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
/* Has "crypto DMA", which is shared with SHA */
#define SOC_AES_CRYPTO_DMA (1)

56
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -135,14 +135,6 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@ -151,10 +143,6 @@ config SOC_SDMMC_HOST_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
@ -163,14 +151,6 @@ config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
@ -219,6 +199,14 @@ config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_APPCPU_HAS_CLOCK_GATING_BUG
bool
default y
@ -839,10 +827,38 @@ config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 64
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_WIFI_HW_TSF
bool
default y

16
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -44,15 +44,10 @@
#define SOC_CCOMP_TIMER_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_SDMMC_HOST_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
@ -65,6 +60,8 @@
#define SOC_SHA_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1
#define SOC_SECURE_BOOT_SUPPORTED 1
/*-------------------------- SOC CAPS ----------------------------------------*/
@ -364,10 +361,17 @@
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1)
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)