MMU: Add configurable mmu page size support on ESP32C2

2024-10-05 20:47:46 -04:00 · 2022-06-01 10:14:48 +08:00 · 2022-06-01 10:14:48 +08:00 · 6589daabb9
commit 6589daabb9
parent f173016d86
37 changed files with 153 additions and 132 deletions
--- a/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
+++ b/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
@ -21,20 +21,18 @@ extern "C" {
 #define FLASH_SECTOR_SIZE 0x1000
 #define FLASH_BLOCK_SIZE 	0x10000
 #define MMAP_ALIGNED_MASK 	0x0000FFFF
+#define MMU_FLASH_MASK    (~(SPI_FLASH_MMU_PAGE_SIZE - 1))

-//This will be replaced with a kconfig, TODO: IDF-3821
-#define MMU_PAGE_SIZE                   0x10000
-#define MMU_FLASH_MASK                  (~(MMU_PAGE_SIZE - 1))
 /**
- * MMU mapping must always be in the unit of a MMU_PAGE_SIZE
+ * MMU mapping must always be in the unit of a SPI_FLASH_MMU_PAGE_SIZE
 * This macro is a helper for you to get needed page nums to be mapped. e.g.:
- * Let's say MMU_PAGE_SIZE is 64KB.
+ * Let's say SPI_FLASH_MMU_PAGE_SIZE is 64KB.
 * - v_start = 0x4200_0004
 * - size = 4 * 64KB
 *
 * You should map from 0x4200_0000, then map 5 pages.
 */
-#define GET_REQUIRED_MMU_PAGES(size, v_start)    ((size + (v_start - (v_start & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE)
+#define GET_REQUIRED_MMU_PAGES(size, v_start)    ((size + (v_start - (v_start & MMU_FLASH_MASK)) + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE)

 /* SPI commands (actual on-wire commands not SPI controller bitmasks)
   Suitable for use with the bootloader_execute_flash_command static function.
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@ -137,7 +137,11 @@ static const char *TAG = "bootloader_flash";
   63th block for bootloader_flash_read
 */
 #define MMU_BLOCK0_VADDR  SOC_DROM_LOW
-#define MMU_SIZE          (0x3f0000)
+#ifdef SOC_MMU_PAGE_SIZE_CONFIGURABLE
+#define MMU_SIZE          (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
+#else
+#define MMU_SIZE          (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
+#endif
 #define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK63_VADDR
 #endif
@ -196,7 +200,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
 #if CONFIG_IDF_TARGET_ESP32
    uint32_t count = GET_REQUIRED_MMU_PAGES(size, src_paddr);
    int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_paddr_aligned, 64, count);
-    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, count * MMU_PAGE_SIZE);
+    ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, count * SPI_FLASH_MMU_PAGE_SIZE);
    if (e != 0) {
        ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
        Cache_Read_Enable(0);
@ -303,12 +307,12 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
            //---------------Do mapping------------------------
            ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
 #if CONFIG_IDF_TARGET_ESP32
-            //Should never fail if we only map a MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
+            //Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
            int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
            assert(e == 0);
 #else
            uint32_t actual_mapped_len = 0;
-            mmu_hal_map_region(0, MMU_TARGET_FLASH0, FLASH_READ_VADDR, map_at, MMU_PAGE_SIZE - 1, &actual_mapped_len);
+            mmu_hal_map_region(0, MMU_TARGET_FLASH0, FLASH_READ_VADDR, map_at, SPI_FLASH_MMU_PAGE_SIZE - 1, &actual_mapped_len);
 #endif
            current_read_mapping = map_at;

--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@ -772,12 +772,12 @@ static void set_cache_and_start_app(
    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
    drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
 #if CONFIG_IDF_TARGET_ESP32
-    uint32_t drom_page_count = (drom_size + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
+    uint32_t drom_page_count = (drom_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
    rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
    rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
-    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * MMU_PAGE_SIZE);
+    ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
 #else
    uint32_t actual_mapped_len = 0;
    mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
@ -791,12 +791,12 @@ static void set_cache_and_start_app(
    //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
    irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
 #if CONFIG_IDF_TARGET_ESP32
-    uint32_t irom_page_count = (irom_size + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
+    uint32_t irom_page_count = (irom_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
    rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
    ESP_EARLY_LOGV(TAG, "rc=%d", rc);
    rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
    ESP_LOGV(TAG, "rc=%d", rc);
-    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * MMU_PAGE_SIZE);
+    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * SPI_FLASH_MMU_PAGE_SIZE);
 #else
    mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
    ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
--- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
+++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
@ -263,6 +263,8 @@ esp_err_t bootloader_init(void)
    cache_hal_init();
    //reset mmu
    mmu_hal_init();
+    // config mmu page size
+    mmu_ll_set_page_size(0, SPI_FLASH_MMU_PAGE_SIZE);
    // config clock
    bootloader_clock_configure();
    // initialize console, from now on, we can use esp_log
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@ -119,6 +119,45 @@ menu "Hardware Settings"
                so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
    endmenu

+    menu "MMU Config"
+        # This Config is used for configure the MMU.
+        # Be configured based on flash size selection.
+        # Invisible to users.
+
+        config MMU_PAGE_SIZE_16KB
+            bool
+            default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_1MB
+            default n
+
+        config MMU_PAGE_SIZE_32KB
+            bool
+            default y if IDF_TARGET_ESP32C2 && ESPTOOLPY_FLASHSIZE_2MB
+            default n
+
+        config MMU_PAGE_SIZE_64KB
+            bool
+            default y if !MMU_PAGE_SIZE_32KB && !MMU_PAGE_SIZE_16KB
+            default n
+
+        config MMU_PAGE_MODE
+            string
+            default "16KB" if MMU_PAGE_SIZE_16KB
+            default "32KB" if MMU_PAGE_SIZE_32KB
+            default "64KB" if MMU_PAGE_SIZE_64KB
+
+        config MMU_PAGE_SIZE
+            # Some chips support different flash MMU page sizes: 64k, 32k, 16k.
+            # Since the number of MMU pages is limited, the maximum flash size supported
+            # for each page size is reduced proportionally: 4 MB, 2MB, 1MB. To make best
+            # use of small flash sizes (reducing the wasted space due to alignment), we
+            # need to use the smallest possible MMU page size for the given flash size.
+            hex
+            default 0x4000 if MMU_PAGE_SIZE_16KB
+            default 0x8000 if MMU_PAGE_SIZE_32KB
+            default 0x10000 if MMU_PAGE_SIZE_64KB
+
+    endmenu
+
    # Insert chip-specific HW config
    orsource "./port/$IDF_TARGET/Kconfig.hw_support"

--- a/components/esp_hw_support/port/esp32s2/mmu_psram.c
+++ b/components/esp_hw_support/port/esp32s2/mmu_psram.c
@ -12,7 +12,7 @@
 #include "soc/ext_mem_defs.h"
 #include "soc/extmem_reg.h"

-#define MMU_PAGE_SIZE    0x10000
+#define MMU_PAGE_SIZE (0x10000)
 #define MMU_PAGE_TO_BYTES(page_id)      ((page_id) * MMU_PAGE_SIZE)
 #define BYTES_TO_MMU_PAGE(bytes)        ((bytes) / MMU_PAGE_SIZE)

@ -46,6 +46,8 @@ uint32_t rodata_flash_end_page_get(void);
 #endif  //#if CONFIG_SPIRAM_RODATA

 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
+// Helper macro to make a MMU entry invalid
+#define INVALID_PHY_PAGE          0xffff
 //TODO IDF-4387
 static uint32_t page0_mapped = 0;
 static uint32_t page0_page = INVALID_PHY_PAGE;
--- a/components/esp_hw_support/port/esp32s3/spiram.c
+++ b/components/esp_hw_support/port/esp32s3/spiram.c
@ -27,8 +27,8 @@


 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
+#define MMU_PAGE_SIZE (0x10000)

-#define MMU_PAGE_SIZE    0x10000
 #define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1))

 #if CONFIG_SPIRAM_SPEED_40M
@ -222,6 +222,8 @@ static uint32_t rodata_end_page = 0;
 #endif

 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
+// Helper macro to make a MMU entry invalid
+#define INVALID_PHY_PAGE          0xffff
 static uint32_t page0_mapped = 0;
 static uint32_t page0_page = INVALID_PHY_PAGE;
 #endif
--- a/components/esp_rom/include/esp32s2/rom/cache.h
+++ b/components/esp_rom/include/esp32s2/rom/cache.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef _ROM_CACHE_H_
 #define _ROM_CACHE_H_
@ -38,7 +30,6 @@ extern "C" {
 #define TAG_SIZE                        4
 #define MAX_TAG_BLOCK_SIZE              (MAX_TAG_BLOCK_ITEMS * TAG_SIZE)

-#define INVALID_PHY_PAGE 0xffff
 #define ESP_CACHE_TEMP_ADDR DROM0_ADDRESS_LOW
 #define CACHE_MAX_OPERATION_SIZE BUS_ADDR_SIZE

--- a/components/esp_system/ld/esp32c2/sections.ld.in
+++ b/components/esp_system/ld/esp32c2/sections.ld.in
@ -146,7 +146,7 @@ SECTIONS
    . = . + SIZEOF(.flash.text);
    /* Prepare the alignment of the section above. Few bytes (0x20) must be
     * added for the mapping header. */
-    . = ALIGN(0x10000) + 0x20;
+    . = ALIGN(_esp_mmu_block_size) + 0x20;
    _rodata_reserved_start = .;
  } > default_rodata_seg

--- a/components/esp_system/ld/ld.common
+++ b/components/esp_system/ld/ld.common
@ -22,3 +22,5 @@ _esp_memprot_align_size = CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE;
 #else
 _esp_memprot_align_size = 0;
 #endif
+
+_esp_mmu_block_size = (CONFIG_MMU_PAGE_SIZE);
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@ -70,6 +70,7 @@
 #include "soc/periph_defs.h"
 #include "esp_cpu.h"
 #include "esp_private/esp_clk.h"
+#include "esp_spi_flash.h"

 #if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX
 #include "esp_private/trax.h"
@ -93,9 +94,6 @@
 #define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_HIGH
 #endif

-//This will be replaced with a kconfig, TODO: IDF-3821
-//Besides, the MMU setting will be abstracted later. So actually we don't need this define in the future
-#define MMU_PAGE_SIZE    0x10000
 //This dependency will be removed in the future
 #include "soc/ext_mem_defs.h"

@ -349,12 +347,12 @@ void IRAM_ATTR call_start_cpu0(void)
    /* Configure the Cache MMU size for instruction and rodata in flash. */
    extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
    extern int _rodata_reserved_start;
-    uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
-    uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
+    uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(SPI_FLASH_MMU_PAGE_SIZE - 1);
+    uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);

 #if CONFIG_IDF_TARGET_ESP32S3
    extern int _rodata_reserved_end;
-    uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE) * sizeof(uint32_t);
+    uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t);
 #endif

    Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
--- a/components/esptool_py/project_include.cmake
+++ b/components/esptool_py/project_include.cmake
@ -32,8 +32,13 @@ set(esptool_elf2image_args
    --flash_size ${ESPFLASHSIZE}
    )

+set(MMU_PAGE_SIZE ${CONFIG_MMU_PAGE_MODE})
+
 if(NOT BOOTLOADER_BUILD)
    list(APPEND esptool_elf2image_args --elf-sha256-offset 0xb0)
+    if(CONFIG_IDF_TARGET_ESP32C2)
+        list(APPEND esptool_elf2image_args --flash-mmu-page-size ${MMU_PAGE_SIZE})
+    endif()
 endif()

 if(NOT CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION AND
--- a/components/fatfs/test_fatfs_host/sdkconfig/sdkconfig.h
+++ b/components/fatfs/test_fatfs_host/sdkconfig/sdkconfig.h
@ -13,3 +13,4 @@
 #define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1

 #define CONFIG_FATFS_VOLUME_COUNT 2
+#define CONFIG_MMU_PAGE_SIZE 0X10000 // 64KB
--- a/components/hal/esp32/include/hal/mmu_ll.h
+++ b/components/hal/esp32/include/hal/mmu_ll.h
@ -36,12 +36,12 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
 /**
 * Set MMU page size
 *
- * @param size  See `mmu_page_size_t`
+ * @param size  MMU page size
 *
 * @note On esp32, only supports `MMU_PAGE_64KB`
 */
 __attribute__((always_inline))
-static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
 {
    HAL_ASSERT(size == MMU_PAGE_64KB);
 }
--- a/components/hal/esp32c2/include/hal/cache_ll.h
+++ b/components/hal/esp32c2/include/hal/cache_ll.h
@ -12,6 +12,7 @@
 #include "soc/ext_mem_defs.h"
 #include "hal/cache_types.h"
 #include "hal/assert.h"
+#include "sdkconfig.h"

 #ifdef __cplusplus
 extern "C" {
@ -53,9 +54,9 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
    cache_bus_mask_t mask = 0;

    uint32_t vaddr_end = vaddr_start + len;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
        mask |= CACHE_BUS_IBUS0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
        mask |= CACHE_BUS_DBUS0;
    } else {
        HAL_ASSERT(0);      //Out of region
--- a/components/hal/esp32c2/include/hal/mmu_ll.h
+++ b/components/hal/esp32c2/include/hal/mmu_ll.h
@ -8,16 +8,25 @@

 #pragma once

+#include <stdbool.h>
 #include "soc/extmem_reg.h"
 #include "soc/ext_mem_defs.h"
 #include "hal/assert.h"
 #include "hal/mmu_types.h"
+#include "sdkconfig.h"


 #ifdef __cplusplus
 extern "C" {
 #endif

+/**
+ * @brief The real MMU page size get from Kconfig.
+ *
+ * @note Only used in this file
+ */
+#define MMU_LL_PAGE_SIZE                   (CONFIG_MMU_PAGE_SIZE)
+
 /**
 * Get MMU page size
 *
@ -36,10 +45,10 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
 /**
 * Set MMU page size
 *
- * @param size  See `mmu_page_size_t`
+ * @param size  MMU page size
 */
 __attribute__((always_inline))
-static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
 {
    uint8_t reg_val = (size == MMU_PAGE_16KB) ? 0 : (size == MMU_PAGE_32KB) ? 1 : 2;
    REG_SET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE, reg_val);
@ -60,7 +69,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 {
    (void)mmu_id;
    uint32_t vaddr_end = vaddr_start + len;
-    return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+    return (ADDRESS_IN_IRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_IRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_DRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE));
 }

 /**
@ -93,7 +102,7 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
            HAL_ASSERT(shift_code);
    }

-    return ((vaddr & MMU_VADDR_MASK) >> shift_code);
+    return ((vaddr & MMU_VADDR_MASK(page_size)) >> shift_code);
 }

 /**
--- a/components/hal/esp32c3/include/hal/mmu_ll.h
+++ b/components/hal/esp32c3/include/hal/mmu_ll.h
@ -36,12 +36,12 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
 /**
 * Set MMU page size
 *
- * @param size  See `mmu_page_size_t`
+ * @param size  MMU page size
 *
 * @note On esp32c3, only supports `MMU_PAGE_64KB`
 */
 __attribute__((always_inline))
-static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
 {
    HAL_ASSERT(size == MMU_PAGE_64KB);
 }
--- a/components/hal/esp32h2/include/hal/mmu_ll.h
+++ b/components/hal/esp32h2/include/hal/mmu_ll.h
@ -36,12 +36,12 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
 /**
 * Set MMU page size
 *
- * @param size  See `mmu_page_size_t`
+ * @param size  MMU page size
 *
 * @note On esp32h2, only supports `MMU_PAGE_64KB`
 */
 __attribute__((always_inline))
-static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
 {
    HAL_ASSERT(size == MMU_PAGE_64KB);
 }
--- a/components/hal/esp32s2/include/hal/mmu_ll.h
+++ b/components/hal/esp32s2/include/hal/mmu_ll.h
@ -36,12 +36,12 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
 /**
 * Set MMU page size
 *
- * @param size  See `mmu_page_size_t`
+ * @param size  MMU page size
 *
 * @note On esp32s2, only supports `MMU_PAGE_64KB`
 */
 __attribute__((always_inline))
-static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
 {
    HAL_ASSERT(size == MMU_PAGE_64KB);
 }
--- a/components/hal/esp32s3/include/hal/mmu_ll.h
+++ b/components/hal/esp32s3/include/hal/mmu_ll.h
@ -36,12 +36,12 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
 /**
 * Set MMU page size
 *
- * @param size  See `mmu_page_size_t`
+ * @param size  MMU page size
 *
 * @note On esp32s3, only supports `MMU_PAGE_64KB`
 */
 __attribute__((always_inline))
-static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
 {
    HAL_ASSERT(size == MMU_PAGE_64KB);
 }
--- a/components/hal/include/hal/mmu_hal.h
+++ b/components/hal/include/hal/mmu_hal.h
@ -40,7 +40,7 @@ uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num);
 * @param bytes     length in byte
 *
 * @return
- *         length in MMU_PAGE_SIZE
+ *         length in CONFIG_MMU_PAGE_SIZE
 */
 uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes);

@ -54,7 +54,7 @@ uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes);
 * @param len          length to be mapped, in bytes
 * @param[out] out_len actual mapped length
 *
- * @note vaddr and paddr should be aligned with the MMU_PAGE_SIZE, see `mmu_ll.h`
+ * @note vaddr and paddr should be aligned with the mmu page size, see CONFIG_MMU_PAGE_SIZE
 */
 void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len);
 #endif
--- a/components/hal/include/hal/mmu_types.h
+++ b/components/hal/include/hal/mmu_types.h
@ -15,9 +15,9 @@ extern "C" {
 * MMU Page size
 */
 typedef enum {
-    MMU_PAGE_16KB,
-    MMU_PAGE_32KB,
-    MMU_PAGE_64KB,
+    MMU_PAGE_16KB = 0x4000,
+    MMU_PAGE_32KB = 0x8000,
+    MMU_PAGE_64KB = 0x10000,
 } mmu_page_size_t;

 /**
--- a/components/soc/esp32/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32/include/soc/ext_mem_defs.h
@ -13,7 +13,6 @@
 extern "C" {
 #endif

-
 #define IRAM0_CACHE_ADDRESS_LOW     0x400D0000
 #define IRAM0_CACHE_ADDRESS_HIGH    0x40400000

--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@ -535,6 +535,10 @@ config SOC_PM_SUPPORT_BT_WAKEUP
    bool
    default y

+config SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    bool
+    default y
+
 config SOC_PM_SUPPORT_CPU_PD
    bool
    default n
--- a/components/soc/esp32c2/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32c2/include/soc/ext_mem_defs.h
@ -14,33 +14,30 @@ extern "C" {

 #include <stdint.h>

-//TODO IDF-3821, for now it's always 64KB
-#define MMU_PAGE_MODE			        2
-
 /*IRAM0 is connected with Cache IBUS0*/
 #define IRAM0_ADDRESS_LOW               0x40000000
-#define IRAM0_ADDRESS_HIGH              IRAM0_CACHE_ADDRESS_HIGH
+#define IRAM0_ADDRESS_HIGH(page_size)              IRAM0_CACHE_ADDRESS_HIGH(page_size)
 #define IRAM0_CACHE_ADDRESS_LOW         0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH        (IRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
+#define IRAM0_CACHE_ADDRESS_HIGH(page_size)        (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 64)) // MMU has 64 pages

 /*DRAM0 is connected with Cache DBUS0*/
 #define DRAM0_ADDRESS_LOW               0x3C000000
 #define DRAM0_ADDRESS_HIGH              0x40000000
 #define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
-#define DRAM0_CACHE_ADDRESS_HIGH        (DRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
-#define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH
+#define DRAM0_CACHE_ADDRESS_HIGH(page_size)        (DRAM0_CACHE_ADDRESS_LOW + ((page_size) * 64))
+#define DRAM0_CACHE_OPERATION_HIGH(page_size)      DRAM0_CACHE_ADDRESS_HIGH(page_size)
 #define ESP_CACHE_TEMP_ADDR             0x3C000000

-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH)
+#define BUS_SIZE(bus_name, page_size)                 (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr, page_size)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) <= bus_name##_ADDRESS_HIGH(page_size))

-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define ADDRESS_IN_IRAM0(vaddr, page_size)            ADDRESS_IN_BUS(IRAM0, vaddr, page_size)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr, page_size)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr, page_size)
+#define ADDRESS_IN_DRAM0(vaddr, page_size)            ADDRESS_IN_BUS(DRAM0, vaddr, page_size)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr, page_size)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr, page_size)

-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+#define BUS_IRAM0_CACHE_SIZE(page_size)              BUS_SIZE(IRAM0_CACHE, page_size)
+#define BUS_DRAM0_CACHE_SIZE(page_size)              BUS_SIZE(DRAM0_CACHE, page_size)

 #define CACHE_IBUS                      0
 #define CACHE_IBUS_MMU_START            0
@ -84,14 +81,10 @@ extern "C" {
 * valid bit is BIT(6), so value bits are 0x3f
 */
 #define MMU_VALID_VAL_MASK 		        0x3f
-/**
- * Helper macro to make a MMU entry invalid
- * Check this! IDF-3821
- */
-#define INVALID_PHY_PAGE                0x7f
+
 /**
 * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
 * 64 * 64KB, means MMU can support 4MB paddr at most
 */
 #define MMU_MAX_PADDR_PAGE_NUM    64
@ -99,7 +92,7 @@ extern "C" {
 * This is the mask used for mapping. e.g.:
 * 0x4200_0000 & MMU_VADDR_MASK
 */
-#define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1)
+#define MMU_VADDR_MASK(page_size)                 ((page_size) * 64 - 1)
 //MMU entry num
 #define MMU_ENTRY_NUM  64

--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@ -269,6 +269,8 @@

 #define SOC_PM_SUPPORT_BT_WAKEUP        (1)

+/*-------------------------- MMU CAPS ----------------------------------------*/
+#define SOC_MMU_PAGE_SIZE_CONFIGURABLE  (1)
 #define SOC_PM_SUPPORT_CPU_PD           (0)

 #define SOC_PM_SUPPORT_WIFI_PD          (0)
--- a/components/soc/esp32c3/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32c3/include/soc/ext_mem_defs.h
@ -79,13 +79,9 @@ extern "C" {
 * valid bit is BIT(8), so value bits are 0xff
 */
 #define MMU_VALID_VAL_MASK 0xff
-/**
- * Helper macro to make a MMU entry invalid
- */
-#define INVALID_PHY_PAGE 0xffff
 /**
 * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
 * 256 * 64KB, means MMU can support 16MB paddr at most
 */
 #define MMU_MAX_PADDR_PAGE_NUM    256
--- a/components/soc/esp32h2/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32h2/include/soc/ext_mem_defs.h
@ -79,13 +79,9 @@ extern "C" {
 * valid bit is BIT(8), so value bits are 0xff
 */
 #define MMU_VALID_VAL_MASK 0xff
-/**
- * Helper macro to make a MMU entry invalid
- */
-#define INVALID_PHY_PAGE 0xffff
 /**
 * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
 * 256 * 64KB, means MMU can support 16MB paddr at most
 */
 #define MMU_MAX_PADDR_PAGE_NUM    256
--- a/components/soc/esp32s2/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32s2/include/soc/ext_mem_defs.h
@ -87,7 +87,6 @@ extern "C" {
 #define PRO_CACHE_DBUS2_MMU_START       0x500
 #define PRO_CACHE_DBUS2_MMU_END         0x600

-// #define MMU_SIZE                        0x600
 #define ICACHE_MMU_SIZE                 0x300
 #define DCACHE_MMU_SIZE                 0x300

@ -110,7 +109,7 @@ extern "C" {
 #define MMU_VALID_VAL_MASK 0x3fff
 /**
 * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
 * 16384 * 64KB, means MMU can support 1GB paddr at most
 */
 #define MMU_MAX_PADDR_PAGE_NUM    16384
--- a/components/soc/esp32s3/include/soc/ext_mem_defs.h
+++ b/components/soc/esp32s3/include/soc/ext_mem_defs.h
@ -79,13 +79,9 @@ extern "C" {
 * valid bit is BIT(14), so value bits are 0x3fff
 */
 #define MMU_VALID_VAL_MASK 0x3fff
-/**
- * Helper macro to make a MMU entry invalid
- */
-#define INVALID_PHY_PAGE 0xffff
 /**
 * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `MMU_MAX_PADDR_PAGE_NUM * CONFIG_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
 * 16384 * 64KB, means MMU can support 1GB paddr at most
 */
 #define MMU_MAX_PADDR_PAGE_NUM    16384
--- a/components/spi_flash/flash_mmap.c
+++ b/components/spi_flash/flash_mmap.c
@ -12,6 +12,7 @@
 #include <freertos/FreeRTOS.h>
 #include <freertos/task.h>
 #include <freertos/semphr.h>
+#include "soc/mmu.h"
 #include "sdkconfig.h"
 #include "esp_attr.h"
 #include "esp_spi_flash.h"
@ -24,33 +25,20 @@
 #include "soc/dport_reg.h"
 #include "esp32/rom/cache.h"
 #include "esp32/spiram.h"
-#include "soc/mmu.h"
-// TODO: IDF-3821
-#define INVALID_PHY_PAGE 0xffff
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/cache.h"
 #include "esp_private/mmu_psram.h"
 #include "soc/extmem_reg.h"
-#include "soc/ext_mem_defs.h"
-#include "soc/mmu.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/spiram.h"
 #include "soc/extmem_reg.h"
-#include "soc/ext_mem_defs.h"
-#include "soc/mmu.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/cache.h"
-#include "soc/ext_mem_defs.h"
-#include "soc/mmu.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/cache.h"
-#include "soc/ext_mem_defs.h"
-#include "soc/mmu.h"
 #elif CONFIG_IDF_TARGET_ESP32C2
 #include "esp32c2/rom/cache.h"
-#include "soc/ext_mem_defs.h"
-#include "soc/mmu.h"
 #endif

 #ifndef NDEBUG
@ -62,6 +50,7 @@
 #define IROM0_PAGES_NUM (SOC_MMU_IROM0_PAGES_END - SOC_MMU_IROM0_PAGES_START)
 #define DROM0_PAGES_NUM (SOC_MMU_DROM0_PAGES_END - SOC_MMU_DROM0_PAGES_START)
 #define PAGES_LIMIT ((SOC_MMU_IROM0_PAGES_END > SOC_MMU_DROM0_PAGES_END) ? SOC_MMU_IROM0_PAGES_END:SOC_MMU_DROM0_PAGES_END)
+#define INVALID_PHY_PAGE(page_size)                ((page_size) - 1)

 #if !CONFIG_SPI_FLASH_ROM_IMPL

@ -125,7 +114,7 @@ esp_err_t IRAM_ATTR spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_
                         const void** out_ptr, spi_flash_mmap_handle_t* out_handle)
 {
    esp_err_t ret;
-    if (src_addr & INVALID_PHY_PAGE) {
+    if (src_addr & INVALID_PHY_PAGE(CONFIG_MMU_PAGE_SIZE)) {
        return ESP_ERR_INVALID_ARG;
    }
    if ((src_addr + size) > spi_flash_get_chip_size()) {
--- a/components/spi_flash/include/esp_spi_flash.h
+++ b/components/spi_flash/include/esp_spi_flash.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef ESP_SPI_FLASH_H
 #define ESP_SPI_FLASH_H
@ -26,12 +18,13 @@
 extern "C" {
 #endif

+#include "sdkconfig.h"
 #define ESP_ERR_FLASH_OP_FAIL    (ESP_ERR_FLASH_BASE + 1)
 #define ESP_ERR_FLASH_OP_TIMEOUT (ESP_ERR_FLASH_BASE + 2)

 #define SPI_FLASH_SEC_SIZE  4096    /**< SPI Flash sector size */

-#define SPI_FLASH_MMU_PAGE_SIZE 0x10000 /**< Flash cache MMU mapping page size */
+#define SPI_FLASH_MMU_PAGE_SIZE CONFIG_MMU_PAGE_SIZE /**< Flash cache MMU mapping page size */

 typedef enum {
    FLASH_WRAP_MODE_8B = 0,
--- a/components/spi_flash/partition.c
+++ b/components/spi_flash/partition.c
@ -78,7 +78,7 @@ static esp_err_t load_partitions(void)
    esp_rom_md5_init(&context);
 #endif

-    uint32_t partition_align_pg_size = (ESP_PARTITION_TABLE_OFFSET) & ~(0x10000 - 1);
+    uint32_t partition_align_pg_size = (ESP_PARTITION_TABLE_OFFSET) & ~(CONFIG_MMU_PAGE_SIZE - 1);
    uint32_t partition_pad = ESP_PARTITION_TABLE_OFFSET - partition_align_pg_size;

 #if CONFIG_IDF_TARGET_LINUX
--- a/components/spi_flash/partition_target.c
+++ b/components/spi_flash/partition_target.c
@ -181,9 +181,9 @@ esp_err_t esp_partition_mmap(const esp_partition_t *partition, size_t offset, si
        return ESP_ERR_NOT_SUPPORTED;
    }
    size_t phys_addr = partition->address + offset;
-    // offset within 64kB block
-    size_t region_offset = phys_addr & 0xffff;
-    size_t mmap_addr = phys_addr & 0xffff0000;
+    // offset within mmu page size block
+    size_t region_offset = phys_addr & (CONFIG_MMU_PAGE_SIZE - 1);
+    size_t mmap_addr = phys_addr & ~(CONFIG_MMU_PAGE_SIZE - 1);
    esp_err_t rc = spi_flash_mmap(mmap_addr, size + region_offset, memory, out_ptr, out_handle);
    // adjust returned pointer to point to the correct offset
    if (rc == ESP_OK) {
--- a/components/spiffs/test_spiffs_host/sdkconfig/sdkconfig.h
+++ b/components/spiffs/test_spiffs_host/sdkconfig/sdkconfig.h
@ -29,6 +29,7 @@
 #define CONFIG_ESPTOOLPY_FLASHSIZE "8MB"
 //currently use the legacy implementation, since the stubs for new HAL are not done yet
 #define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
+#define CONFIG_MMU_PAGE_SIZE 0X10000 // 64KB

 #undef _Static_assert
 #define _Static_assert(cond, message)
--- a/components/wear_levelling/test_wl_host/sdkconfig/sdkconfig.h
+++ b/components/wear_levelling/test_wl_host/sdkconfig/sdkconfig.h
@ -11,3 +11,4 @@
 #define CONFIG_ESPTOOLPY_FLASHSIZE "8MB"
 //currently use the legacy implementation, since the stubs for new HAL are not done yet
 #define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
+#define CONFIG_MMU_PAGE_SIZE 0X10000 // 64KB
--- a/tools/ci/check_copyright_ignore.txt
+++ b/tools/ci/check_copyright_ignore.txt
@ -582,7 +582,6 @@ components/esp_rom/include/esp32h2/rom/tjpgd.h
 components/esp_rom/include/esp32h2/rom/uart.h
 components/esp_rom/include/esp32s2/rom/aes.h
 components/esp_rom/include/esp32s2/rom/bigint.h
-components/esp_rom/include/esp32s2/rom/cache.h
 components/esp_rom/include/esp32s2/rom/crc.h
 components/esp_rom/include/esp32s2/rom/digital_signature.h
 components/esp_rom/include/esp32s2/rom/efuse.h
@ -1528,7 +1527,6 @@ components/soc/include/soc/usb_periph.h
 components/soc/lldesc.c
 components/soc/soc_include_legacy_warn.c
 components/spi_flash/cache_utils.h
-components/spi_flash/include/esp_spi_flash.h
 components/spi_flash/include/esp_spi_flash_counters.h
 components/spi_flash/include/spi_flash_chip_boya.h
 components/spi_flash/include/spi_flash_chip_driver.h