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cache/mmu: implememnt cache and mmu hal APIs in bootloader

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This commit is contained in:
Armando 2022-02-11 15:30:54 +08:00
parent 8b902739ac
commit c1cbd7bbf6
70 changed files with 2314 additions and 466 deletions
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1
components/bootloader/subproject/main/ld/esp32/bootloader.ld
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@ -65,6 +65,7 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

2
components/bootloader/subproject/main/ld/esp32c2/bootloader.ld
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@ -52,6 +52,8 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

8
components/bootloader/subproject/main/ld/esp32c3/bootloader.ld
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@ -11,8 +11,8 @@
MEMORY
{
iram_seg (RWX) : org = 0x403CE000, len = 0x2000
iram_loader_seg (RWX) : org = 0x403D0000, len = 0x6000
iram_seg (RWX) : org = 0x403CE000, len = 0x1600
iram_loader_seg (RWX) : org = 0x403CF600, len = 0x6A00
dram_seg (RW) : org = 0x3FCD6000, len = 0x4000
}
@ -27,7 +27,7 @@ SECTIONS
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*liblog.a:(.literal .text .literal.* .text.*)
*libgcc.a:(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
@ -52,6 +52,8 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

2
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
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@ -50,6 +50,8 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

2
components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
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@ -52,6 +52,8 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

6
components/bootloader/subproject/main/ld/esp32s3/bootloader.ld
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@ -11,8 +11,8 @@
MEMORY
{
iram_seg (RWX) : org = 0x403B6000, len = 0x4000
iram_loader_seg (RWX) : org = 0x403BA000, len = 0x6000
iram_seg (RWX) : org = 0x403B6000, len = 0x3000
iram_loader_seg (RWX) : org = 0x403B9000, len = 0x7000
dram_seg (RW) : org = 0x3FCD0000, len = 0x4000
}
@ -52,6 +52,8 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

31
components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
View File

@ -22,6 +22,20 @@ extern "C" {
#define FLASH_BLOCK_SIZE 0x10000
#define MMAP_ALIGNED_MASK 0x0000FFFF
//This will be replaced with a kconfig, TODO: IDF-3821
#define MMU_PAGE_SIZE 0x10000
#define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1))
/**
* MMU mapping must always be in the unit of a MMU_PAGE_SIZE
* This macro is a helper for you to get needed page nums to be mapped. e.g.:
* Let's say MMU_PAGE_SIZE is 64KB.
* - v_start = 0x4200_0004
* - size = 4 * 64KB
*
* You should map from 0x4200_0000, then map 5 pages.
*/
#define GET_REQUIRED_MMU_PAGES(size, v_start) ((size + (v_start - (v_start & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE)
/* SPI commands (actual on-wire commands not SPI controller bitmasks)
Suitable for use with the bootloader_execute_flash_command static function.
*/
@ -133,23 +147,6 @@ esp_err_t bootloader_flash_erase_sector(size_t sector);
*/
esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size);
/* Cache MMU block size */
#define MMU_BLOCK_SIZE 0x10000
/* Cache MMU address mask (MMU tables ignore bits which are zero) */
#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1))
/**
* @brief Calculate the number of cache pages to map
* @param size size of data to map
* @param vaddr virtual address where data will be mapped
* @return number of cache MMU pages required to do the mapping
*/
static inline uint32_t bootloader_cache_pages_to_map(uint32_t size, uint32_t vaddr)
{
return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / MMU_BLOCK_SIZE;
}
/**
* @brief Execute a user command on the flash
*

167
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
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@ -42,7 +42,6 @@
#define ESP_BOOTLOADER_SPIFLASH_QE_GD_SR2 BIT1 // QE position when you write 8 bits(for SR2) at one time.
#define ESP_BOOTLOADER_SPIFLASH_QE_SR1_2BYTE BIT9 // QE position when you write 16 bits at one time.
#ifndef BOOTLOADER_BUILD
/* Normal app version maps to esp_spi_flash.h operations...
*/
@ -116,23 +115,11 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
/* Bootloader version, uses ROM functions only */
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#include "soc/cache_memory.h"
#endif
#include "esp_rom_spiflash.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
static const char *TAG = "bootloader_flash";
#if CONFIG_IDF_TARGET_ESP32
@ -171,60 +158,75 @@ uint32_t bootloader_mmap_get_free_pages(void)
return MMU_FREE_PAGES;
}
const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
{
if (mapped) {
ESP_LOGE(TAG, "tried to bootloader_mmap twice");
ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice");
return NULL; /* can't map twice */
}
if (size > MMU_SIZE) {
ESP_LOGE(TAG, "bootloader_mmap excess size %x", size);
ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
return NULL;
}
uint32_t src_addr_aligned = src_addr & MMU_FLASH_MASK;
uint32_t count = bootloader_cache_pages_to_map(size, src_addr);
uint32_t src_paddr_aligned = src_paddr & MMU_FLASH_MASK;
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
uint32_t size_after_paddr_aligned = (src_paddr - src_paddr_aligned) + size;
/**
* @note 1
* Will add here a check to make sure the vaddr is on read-only and executable buses, since we use others for psram
* Now simply check if it's valid vaddr, didn't check if it's readable, writable or executable.
* TODO: IDF-4710
*/
if (mmu_ll_check_valid_ext_vaddr_region(0, MMU_BLOCK0_VADDR, size_after_paddr_aligned) == 0) {
ESP_EARLY_LOGE(TAG, "vaddr not valid");
return NULL;
}
//-------------stop cache to do the MMU mapping--------------
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Disable(0);
Cache_Flush(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
uint32_t autoload = Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
#else // access rodata with DCache
uint32_t autoload = Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
#endif
ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x",
src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
#if CONFIG_IDF_TARGET_ESP32
int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
#elif CONFIG_IDF_TARGET_ESP32S2
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
#else
int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
cache_hal_disable(CACHE_TYPE_ALL);
#endif
if (e != 0) {
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
//---------------Do mapping------------------------
ESP_EARLY_LOGD(TAG, "rodata starts from paddr=0x%08x, size=0x%x, will be mapped to vaddr=0x%08x", src_paddr, size, MMU_BLOCK0_VADDR);
#if CONFIG_IDF_TARGET_ESP32
uint32_t count = GET_REQUIRED_MMU_PAGES(size, src_paddr);
int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_paddr_aligned, 64, count);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, count * MMU_PAGE_SIZE);
if (e != 0) {
ESP_EARLY_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
Cache_Read_Enable(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
Cache_Resume_ICache(autoload);
#else // access rodata with DCache
Cache_Resume_DCache(autoload);
#endif
return NULL;
}
#else
/**
* This hal won't return error, it assumes the inputs are valid. The related check should be done in `bootloader_mmap()`.
* See above comments (note 1) about IDF-4710
*/
uint32_t actual_mapped_len = 0;
mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_BLOCK0_VADDR, src_paddr_aligned, size_after_paddr_aligned, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", src_paddr_aligned, MMU_BLOCK0_VADDR, actual_mapped_len);
#endif
/**
* If after mapping, your code stucks, it possibly means that some of the buses are not enabled, check `cache_ll_l1_enable_bus()`
* For now, keep this unchanged.
*/
//-------------enable cache--------------
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
Cache_Resume_ICache(autoload);
#else // access rodata with DCache
Cache_Resume_DCache(autoload);
#else
cache_hal_enable(CACHE_TYPE_ALL);
#endif
mapped = true;
return (void *)(MMU_BLOCK0_VADDR + (src_addr - src_addr_aligned));
return (void *)(MMU_BLOCK0_VADDR + (src_paddr - src_paddr_aligned));
}
void bootloader_munmap(const void *mapping)
@ -235,15 +237,9 @@ void bootloader_munmap(const void *mapping)
Cache_Read_Disable(0);
Cache_Flush(0);
mmu_init(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
//TODO, save the autoload value.
Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
Cache_MMU_Init();
#else // access rodata with DCache
Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
Cache_MMU_Init();
#else
cache_hal_disable(CACHE_TYPE_ALL);
mmu_hal_init();
#endif
mapped = false;
current_read_mapping = UINT32_MAX;
@ -269,18 +265,16 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Disable(0);
Cache_Flush(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
uint32_t autoload = Cache_Suspend_ICache();
#else // access rodata with DCache
uint32_t autoload = Cache_Suspend_DCache();
#else
cache_hal_disable(CACHE_TYPE_ALL);
#endif
esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
Cache_Resume_ICache(autoload);
#else // access rodata with DCache
Cache_Resume_DCache(autoload);
#else
cache_hal_enable(CACHE_TYPE_ALL);
#endif
return spi_to_esp_err(r);
@ -294,44 +288,35 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
uint32_t word_src = src_addr + word * 4; /* Read this offset from flash */
uint32_t map_at = word_src & MMU_FLASH_MASK; /* Map this 64KB block from flash */
uint32_t *map_ptr;
/* Move the 64KB mmu mapping window to fit map_at */
if (map_at != current_read_mapping) {
/* Move the 64KB mmu mapping window to fit map_at */
//----------Stop cache for mapping----------------
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Disable(0);
Cache_Flush(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
uint32_t autoload = Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
#else // access rodata with DCache
uint32_t autoload = Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
#else
cache_hal_disable(CACHE_TYPE_ALL);
#endif
ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
//---------------Do mapping------------------------
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
#if CONFIG_IDF_TARGET_ESP32
//Should never fail if we only map a MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
#elif CONFIG_IDF_TARGET_ESP32S2
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
#else // map rodata with DBus
int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
assert(e == 0);
#else
uint32_t actual_mapped_len = 0;
mmu_hal_map_region(0, MMU_TARGET_FLASH0, FLASH_READ_VADDR, map_at, MMU_PAGE_SIZE - 1, &actual_mapped_len);
#endif
if (e != 0) {
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
Cache_Resume_ICache(autoload);
#else // access rodata with DCache
Cache_Resume_DCache(autoload);
#endif
return ESP_FAIL;
}
current_read_mapping = map_at;
//-------------enable cache-------------------------
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
Cache_Resume_ICache(autoload);
#else // access rodata with DCache
Cache_Resume_DCache(autoload);
#else
cache_hal_enable(CACHE_TYPE_ALL);
#endif
}
map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at));

141
components/bootloader_support/src/bootloader_utility.c
View File

@ -19,56 +19,46 @@
#include "esp32/rom/cache.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/crc.h"
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h"
#include "esp32c3/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/crc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#include "esp32c2/rom/efuse.h"
#include "esp32c2/rom/crc.h"
#include "esp32c2/rom/rtc.h"
#include "esp32c2/rom/uart.h"
#include "esp32c2/rom/gpio.h"
#include "esp32c2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#else // CONFIG_IDF_TARGET_*
#error "Unsupported IDF_TARGET"
#endif
#include "esp_rom_spiflash.h"
#include "soc/soc.h"
#include "esp_cpu.h"
#include "soc/rtc.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_periph.h"
#include "soc/rtc_periph.h"
#include "soc/timer_periph.h"
#include "hal/mmu_hal.h"
#include "hal/cache_types.h"
#include "hal/cache_ll.h"
#include "hal/cache_hal.h"
#include "esp_cpu.h"
#include "esp_image_format.h"
#include "esp_secure_boot.h"
#include "esp_flash_encrypt.h"
@ -716,99 +706,74 @@ static void set_cache_and_start_app(
{
int rc __attribute__((unused));
ESP_LOGD(TAG, "configure drom and irom and start");
ESP_EARLY_LOGD(TAG, "configure drom and irom and start");
//-----------------------Disable Cache to do the mapping---------
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Disable(0);
Cache_Flush(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
uint32_t autoload = Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
#else // access rodata with DCache
uint32_t autoload = Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
#else
cache_hal_disable(CACHE_TYPE_ALL);
#endif
/* Clear the MMU entries that are already set up,
* so the new app only has the mappings it creates.
*/
#if CONFIG_IDF_TARGET_ESP32
for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
}
#else
for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
}
#endif
mmu_hal_init();
//-----------------------MAP DROM--------------------------
uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK;
uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr);
ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d",
drom_addr_aligned, drom_load_addr_aligned, drom_size, drom_page_count);
ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", drom_addr, drom_load_addr, drom_size);
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
#if CONFIG_IDF_TARGET_ESP32
uint32_t drom_page_count = (drom_size + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
#elif CONFIG_IDF_TARGET_ESP32S2
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
#else // map rodata with DBUS
rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count, 0);
#endif
ESP_LOGV(TAG, "rc=%d", rc);
#if CONFIG_IDF_TARGET_ESP32
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr_aligned, 64, drom_page_count);
ESP_LOGV(TAG, "rc=%d", rc);
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, drom_page_count * MMU_PAGE_SIZE);
#else
uint32_t actual_mapped_len = 0;
mmu_hal_map_region(0, MMU_TARGET_FLASH0, drom_load_addr_aligned, drom_addr_aligned, drom_size, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
#endif
//-----------------------MAP IROM--------------------------
uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK;
uint32_t irom_page_count = bootloader_cache_pages_to_map(irom_size, irom_load_addr);
ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d",
irom_addr_aligned, irom_load_addr_aligned, irom_size, irom_page_count);
ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08x, vaddr=0x%08x, size=0x%x", irom_addr, irom_load_addr, irom_size);
//The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
#if CONFIG_IDF_TARGET_ESP32
uint32_t irom_page_count = (irom_size + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
#else // access text with IBUS
#if CONFIG_IDF_TARGET_ESP32S2
uint32_t iram1_used = 0;
if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
iram1_used = 1;
}
if (iram1_used) {
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
}
#endif
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count, 0);
#endif
ESP_LOGV(TAG, "rc=%d", rc);
#if CONFIG_IDF_TARGET_ESP32
ESP_EARLY_LOGV(TAG, "rc=%d", rc);
rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr_aligned, 64, irom_page_count);
ESP_LOGV(TAG, "rc=%d", rc);
DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG,
(DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
(DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 |
DPORT_PRO_CACHE_MASK_DRAM1 );
DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG,
(DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
(DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
DPORT_APP_CACHE_MASK_DRAM1 );
#elif CONFIG_IDF_TARGET_ESP32S2
REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 );
#elif CONFIG_IDF_TARGET_ESP32S3
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, irom_page_count * MMU_PAGE_SIZE);
#else
mmu_hal_map_region(0, MMU_TARGET_FLASH0, irom_load_addr_aligned, irom_addr_aligned, irom_size, &actual_mapped_len);
ESP_EARLY_LOGV(TAG, "after mapping text, starting from paddr=0x%08x and vaddr=0x%08x, 0x%x bytes are mapped", irom_addr_aligned, irom_load_addr_aligned, actual_mapped_len);
#endif
//----------------------Enable corresponding buses----------------
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, drom_load_addr_aligned, drom_size);
cache_ll_l1_enable_bus(0, bus_mask);
bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
cache_ll_l1_enable_bus(0, bus_mask);
#if !CONFIG_FREERTOS_UNICORE
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
#endif
#else // ESP32C3, ESP32H2
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
cache_ll_l1_enable_bus(1, bus_mask);
bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);
cache_ll_l1_enable_bus(1, bus_mask);
#endif
//----------------------Enable Cache----------------
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
Cache_Resume_ICache(autoload);
#else // access rodata with DCache
Cache_Resume_DCache(autoload);
#endif
// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
Cache_Read_Enable(0);
#else
cache_hal_enable(CACHE_TYPE_ALL);
#endif
ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
bootloader_atexit();

32
components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
View File

@ -25,7 +25,6 @@
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32c2/rom/efuse.h"
#include "esp32c2/rom/cache.h"
#include "esp32c2/rom/ets_sys.h"
#include "esp32c2/rom/rtc.h"
#include "bootloader_common.h"
@ -37,6 +36,9 @@
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
#include "hal/mmu_ll.h"
static const char *TAG = "boot.esp32c2";
@ -65,16 +67,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
}
}
static void bootloader_reset_mmu(void)
{
Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
Cache_MMU_Init();
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
{
uint32_t size;
@ -97,10 +89,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
uint32_t autoload = Cache_Suspend_ICache();
cache_hal_disable(CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
Cache_Resume_ICache(autoload);
cache_hal_enable(CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@ -171,10 +163,10 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
static void bootloader_print_mmu_page_size(void)
{
int page_mode = MMU_Get_Page_Mode();
int size = (page_mode == 0 ? 16 :
page_mode == 1 ? 32 :
page_mode == 2 ? 64 : 0);
mmu_page_size_t page_size = mmu_ll_get_page_size(0);
int size = (page_size == MMU_PAGE_16KB ? 16 :
page_size == MMU_PAGE_32KB ? 32 :
page_size == MMU_PAGE_64KB ? 64 : 0);
ESP_LOGI(TAG, "MMU Page Size : %dK", size);
}
@ -272,8 +264,10 @@ esp_err_t bootloader_init(void)
esp_efuse_init_virtual_mode_in_ram();
#endif
#endif
// reset MMU
bootloader_reset_mmu();
//init cache hal
cache_hal_init();
//reset mmu
mmu_hal_init();
// config clock
bootloader_clock_configure();
// initialize console, from now on, we can use esp_log

23
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@ -25,7 +25,6 @@
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/ets_sys.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
@ -37,6 +36,8 @@
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
static const char *TAG = "boot.esp32c3";
@ -72,16 +73,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
}
}
static void bootloader_reset_mmu(void)
{
Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
Cache_MMU_Init();
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
{
uint32_t size;
@ -104,10 +95,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
uint32_t autoload = Cache_Suspend_ICache();
cache_hal_disable(CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
Cache_Resume_ICache(autoload);
cache_hal_enable(CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@ -316,8 +307,10 @@ esp_err_t bootloader_init(void)
esp_efuse_init_virtual_mode_in_ram();
#endif
#endif
// reset MMU
bootloader_reset_mmu();
//init cache hal
cache_hal_init();
//reset mmu
mmu_hal_init();
// config clock
bootloader_clock_configure();
// initialize console, from now on, we can use esp_log

23
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
View File

@ -25,7 +25,6 @@
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/ets_sys.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
@ -36,6 +35,8 @@
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
static const char *TAG = "boot.esp32h2";
@ -71,16 +72,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
}
}
static void bootloader_reset_mmu(void)
{
Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
Cache_MMU_Init();
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
{
uint32_t size;
@ -103,10 +94,10 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
uint32_t autoload = Cache_Suspend_ICache();
cache_hal_disable(CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
Cache_Resume_ICache(autoload);
cache_hal_enable(CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@ -279,8 +270,10 @@ esp_err_t bootloader_init(void)
assert(&_data_start <= &_data_end);
// clear bss section
bootloader_clear_bss_section();
// reset MMU
bootloader_reset_mmu();
//init cache hal
cache_hal_init(); //TODO IDF-4649
//reset mmu
mmu_hal_init();
// config clock
bootloader_clock_configure();
// initialize console, from now on, we can use esp_log

27
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
View File

@ -23,7 +23,6 @@
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "esp32s2/rom/cache.h"
#include "esp_attr.h"
#include "esp_log.h"
@ -36,6 +35,8 @@
#include "soc/rtc.h"
#include "soc/spi_periph.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
static const char *TAG = "boot.esp32s2";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
@ -70,18 +71,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
}
}
static void bootloader_reset_mmu(void)
{
//ToDo: save the autoload value
Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
Cache_MMU_Init();
/* normal ROM boot exits with DROM0 cache unmasked,
but serial bootloader exits with it masked. */
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
{
uint32_t size;
@ -113,12 +102,12 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
uint32_t autoload = Cache_Suspend_ICache();
cache_hal_disable(CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
// TODO: set mode
// TODO: set frequency
Cache_Resume_ICache(autoload);
cache_hal_enable(CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@ -315,8 +304,12 @@ esp_err_t bootloader_init(void)
esp_efuse_init_virtual_mode_in_ram();
#endif
#endif
// reset MMU
bootloader_reset_mmu();
// init cache hal
cache_hal_init();
// reset mmu
mmu_hal_init();
// Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader exits with it masked.
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
// config clock
bootloader_clock_configure();
// initialize console, from now on, we can use esp_log

26
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
View File

@ -24,7 +24,6 @@
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/rtc.h"
#include "bootloader_common.h"
@ -36,6 +35,8 @@
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
static const char *TAG = "boot.esp32s3";
@ -72,18 +73,6 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
}
}
static void bootloader_reset_mmu(void)
{
Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
Cache_MMU_Init();
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS);
#if !CONFIG_FREERTOS_UNICORE
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS);
#endif
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
{
uint32_t size;
@ -115,12 +104,13 @@ static void update_flash_config(const esp_image_header_t *bootloader_hdr)
default:
size = 2;
}
uint32_t autoload = Cache_Suspend_DCache();
cache_hal_disable(CACHE_TYPE_ALL);
// Set flash chip size
esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
// TODO: set mode
// TODO: set frequency
Cache_Resume_DCache(autoload);
cache_hal_enable(CACHE_TYPE_ALL);
}
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
@ -346,8 +336,10 @@ esp_err_t bootloader_init(void)
esp_efuse_init_virtual_mode_in_ram();
#endif
#endif
// reset MMU
bootloader_reset_mmu();
//init cache hal
cache_hal_init();
//reset mmu
mmu_hal_init();
// config clock
bootloader_clock_configure();
// initialize console, from now on, we can use esp_log

11
components/esp_hw_support/port/esp32s2/mmu_psram.c
View File

@ -9,9 +9,10 @@
#include "esp_private/mmu_psram.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/ets_sys.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/extmem_reg.h"
#define MMU_PAGE_SIZE 0x10000
#define MMU_PAGE_TO_BYTES(page_id) ((page_id) * MMU_PAGE_SIZE)
#define BYTES_TO_MMU_PAGE(bytes) ((bytes) / MMU_PAGE_SIZE)
@ -74,10 +75,10 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM0);
uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & BUS_ADDR_MASK) / MMU_PAGE_SIZE;
uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE;
instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu_offset];
instr_start_page &= MMU_ADDRESS_MASK;
instr_start_page &= MMU_VALID_VAL_MASK;
instr_end_page = instr_start_page + instr_page_cnt - 1;
instr_flash2spiram_offs = instr_start_page - page_id;
ESP_EARLY_LOGV(TAG, "Instructions from flash page%d copy to SPIRAM page%d, Offset: %d", instr_start_page, page_id, instr_flash2spiram_offs);
@ -128,10 +129,10 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM0);
uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & BUS_ADDR_MASK) / MMU_PAGE_SIZE;
uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE;
rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset];
rodata_start_page &= MMU_ADDRESS_MASK;
rodata_start_page &= MMU_VALID_VAL_MASK;
rodata_end_page = rodata_start_page + rodata_page_cnt - 1;
rodata_flash2spiram_offs = rodata_start_page - page_id;
ESP_EARLY_LOGV(TAG, "Rodata from flash page%d copy to SPIRAM page%d, Offset: %d", rodata_start_page, page_id, rodata_flash2spiram_offs);

8
components/esp_hw_support/port/esp32s3/spiram.c
View File

@ -25,7 +25,7 @@ we add more types of external RAM memory, this can be made into a more intellige
#include "soc/soc_memory_layout.h"
#include "soc/dport_reg.h"
#include "esp32s3/rom/cache.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/extmem_reg.h"
/**
@ -35,6 +35,8 @@ we add more types of external RAM memory, this can be made into a more intellige
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
#define MMU_PAGE_SIZE 0x10000
#if CONFIG_SPIRAM
static const char *TAG = "spiram";
@ -174,7 +176,7 @@ void instruction_flash_page_info_init(void)
uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START);
instr_start_page &= MMU_ADDRESS_MASK;
instr_start_page &= MMU_VALID_VAL_MASK;
instr_end_page = instr_start_page + instr_page_cnt - 1;
}
@ -200,7 +202,7 @@ void rodata_flash_page_info_init(void)
uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START);
rodata_start_page &= MMU_ADDRESS_MASK;
rodata_start_page &= MMU_VALID_VAL_MASK;
rodata_end_page = rodata_start_page + rodata_page_cnt - 1;
}

24
components/esp_rom/include/esp32c2/rom/cache.h
View File

@ -95,12 +95,6 @@ typedef enum {
CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
} cache_freeze_mode_t;
typedef enum {
CACHE_PAGE_16KB = 0,
CACHE_PAGE_32KB,
CACHE_PAGE_64KB,
} mmu_page_mode_t;
struct cache_mode {
uint32_t cache_size; /*!< cache size in byte */
uint16_t cache_line_size; /*!< cache line size in byte */
@ -608,24 +602,6 @@ void Cache_Set_Default_Mode(void);
*/
void Cache_Enable_Defalut_ICache_Mode(void);
/**
* @brief Set mmu page mode.
*
* @param mmu_page_mode_t
*
* @return None
*/
void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode);
/**
* @brief Get mmu page mode.
*
* @param None
*
* @return page mode
*/
mmu_page_mode_t MMU_Get_Page_Mode(void);
/**
* @brief Enable freeze for ICache.
* Any miss request will be rejected, including cpu miss and preload/autoload miss.

6
components/esp_system/ld/esp32c3/memory.ld.in
View File

@ -23,11 +23,15 @@
#define ESP_BOOTLOADER_RESERVE_RTC 0
#endif
/**
* physical memory is mapped twice to the vritual address (IRAM and DRAM).
* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
*/
#define SRAM_IRAM_START 0x4037C000
#define SRAM_DRAM_START 0x3FC7C000
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END 0x403CF600 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)

4
components/esp_system/ld/esp32s3/memory.ld.in
View File

@ -26,7 +26,7 @@
* 40370000 <- IRAM/Icache -> 40378000 <- D/IRAM (I) -> 403E0000
* 3FC88000 <- D/IRAM (D) -> 3FCF0000 <- DRAM/DCache -> 3FD00000
*
* Startup code uses the IRAM from 0x403BA000 to 0x403E0000, which is not available for static
* Startup code uses the IRAM from 0x403B9000 to 0x403E0000, which is not available for static
* memory, but can only be used after app starts.
*
* D cache use the memory from high address, so when it's configured to 16K/32K, the region
@ -36,7 +36,7 @@
#define SRAM_IRAM_START 0x40370000
#define SRAM_DIRAM_I_START 0x40378000
#define SRAM_IRAM_END 0x403BA000
#define SRAM_IRAM_END 0x403B9000
#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
#define SRAM_DRAM_START 0x3FC88000

2
components/esp_system/port/arch/xtensa/panic_arch.c
View File

@ -20,7 +20,7 @@
#if !CONFIG_IDF_TARGET_ESP32
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/rtc_cntl_reg.h"
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#ifdef CONFIG_IDF_TARGET_ESP32S2

9
components/esp_system/port/cpu_start.c
View File

@ -41,24 +41,20 @@
#include "esp32s3/dport_access.h"
#include "esp_memprot.h"
#include "soc/assist_debug_reg.h"
#include "soc/cache_memory.h"
#include "soc/system_reg.h"
#include "esp32s3/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h"
#include "esp32c3/rom/cache.h"
#include "soc/cache_memory.h"
#include "esp_memprot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rtc.h"
#include "esp32h2/rom/cache.h"
#include "soc/cache_memory.h"
#include "esp_memprot.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rtc.h"
#include "esp32c2/rom/cache.h"
#include "esp32c2/rom/rtc.h"
#include "soc/cache_memory.h"
#include "esp32c2/memprot.h"
#endif
@ -99,6 +95,11 @@
#define ROM_LOG_MODE ESP_EFUSE_ROM_LOG_ON_GPIO_HIGH
#endif
//This will be replaced with a kconfig, TODO: IDF-3821
//Besides, the MMU setting will be abstracted later. So actually we don't need this define in the future
#define MMU_PAGE_SIZE 0x10000
//This dependency will be removed in the future
#include "soc/ext_mem_defs.h"
#include "esp_private/startup_internal.h"
#include "esp_private/system_internal.h"

7
components/hal/CMakeLists.txt
View File

@ -4,10 +4,15 @@ set(srcs "wdt_hal_iram.c"
"mpu_hal.c"
"cpu_hal.c"
"efuse_hal.c"
"${target}/efuse_hal.c")
"${target}/efuse_hal.c"
"mmu_hal.c")
set(includes "${target}/include" "include" "platform_port/include")
if(NOT ${target} STREQUAL "esp32")
list(APPEND srcs "cache_hal.c")
endif()
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
list(APPEND includes "${target}/include/rev1")

110
components/hal/cache_hal.c Normal file
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@ -0,0 +1,110 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/param.h>
#include <stdint.h>
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_attr.h"
#include "hal/assert.h"
#include "hal/cache_hal.h"
#include "hal/cache_types.h"
#include "hal/cache_ll.h"
#include "soc/soc_caps.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#endif
/*------------------------------------------------------------------------------
* Unified Cache Control
* See cache_hal.h for more info about these HAL APIs
* This file is in internal RAM.
* Now this file doesn't compile on ESP32
*----------------------------------------------------------------------------*/
/**
* To know if autoload is enabled or not.
*
* We should have a unified flag for this aim, then we don't need to call following 2 functions
* to know the flag.
*
* Suggest ROM keeping this flag value to BIT(2). Then we can replace following lines to:
* #define DATA_AUTOLOAD_FLAG BIT(2)
* #define INST_AUTOLOAD_FLAG BIT(2)
*/
#define DATA_AUTOLOAD_FLAG Cache_Disable_DCache()
#define INST_AUTOLOAD_FLAG Cache_Disable_ICache()
/**
* Necessary hal contexts, could be maintained by upper layer in the future
*/
typedef struct {
uint32_t data_autoload_flag;
uint32_t inst_autoload_flag;
} cache_hal_context_t;
static cache_hal_context_t ctx;
void cache_hal_init(void)
{
#if SOC_SHARED_IDCACHE_SUPPORTED
ctx.data_autoload_flag = INST_AUTOLOAD_FLAG;
Cache_Enable_ICache(ctx.data_autoload_flag);
#else
ctx.data_autoload_flag = DATA_AUTOLOAD_FLAG;
Cache_Enable_DCache(ctx.data_autoload_flag);
ctx.inst_autoload_flag = INST_AUTOLOAD_FLAG;
Cache_Enable_ICache(ctx.inst_autoload_flag);
#endif
cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK);
cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK);
#if !CONFIG_FREERTOS_UNICORE
cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK);
cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK);
#endif
}
void cache_hal_disable(cache_type_t type)
{
#if SOC_SHARED_IDCACHE_SUPPORTED
Cache_Disable_ICache();
#else
if (type == CACHE_TYPE_DATA) {
Cache_Disable_DCache();
} else if (type == CACHE_TYPE_INSTRUCTION) {
Cache_Disable_ICache();
} else {
Cache_Disable_ICache();
Cache_Disable_DCache();
}
#endif
}
void cache_hal_enable(cache_type_t type)
{
#if SOC_SHARED_IDCACHE_SUPPORTED
Cache_Enable_ICache(ctx.inst_autoload_flag);
#else
if (type == CACHE_TYPE_DATA) {
Cache_Enable_DCache(ctx.data_autoload_flag);
} else if (type == CACHE_TYPE_INSTRUCTION) {
Cache_Enable_ICache(ctx.inst_autoload_flag);
} else {
Cache_Enable_ICache(ctx.inst_autoload_flag);
Cache_Enable_DCache(ctx.data_autoload_flag);
}
#endif
}

138
components/hal/esp32/include/hal/cache_ll.h Normal file
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@ -0,0 +1,138 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include "soc/dport_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
cache_bus_mask_t mask = 0;
uint32_t vaddr_end = vaddr_start + len;
if (vaddr_start >= IROM0_CACHE_ADDRESS_HIGH) {
HAL_ASSERT(false); //out of range
} else if (vaddr_start >= IROM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS2;
} else if (vaddr_start >= IRAM1_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS1;
mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
} else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS0;
mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
} else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) {
HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
mask |= CACHE_BUS_DBUS1;
} else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) {
HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
mask |= CACHE_BUS_DBUS0;
} else {
HAL_ASSERT(false);
}
return mask;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
* @param enable 1: enable; 0: disable
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
(void) mask;
HAL_ASSERT(cache_id == 0 || cache_id == 1);
uint32_t bus_mask = 0;
if (cache_id == 0) {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
} else {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
}
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
* @param enable 1: enable; 0: disable
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
(void) mask;
HAL_ASSERT(cache_id == 0 || cache_id == 1);
uint32_t bus_mask = 0;
if (cache_id == 0) {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
} else {
bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
}
}
#ifdef __cplusplus
}
#endif

73
components/hal/esp32/include/hal/mmu_ll.h Normal file
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@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
//On esp32, MMU Page size is always 64KB
(void)mmu_id;
return MMU_PAGE_64KB;
}
/**
* Set MMU page size
*
* @param size See `mmu_page_size_t`
*
* @note On esp32, only supports `MMU_PAGE_64KB`
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
{
HAL_ASSERT(size == MMU_PAGE_64KB);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
{
(void)mmu_id;
uint32_t vaddr_end = vaddr_start + len;
return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
(ADDRESS_IN_IRAM1_CACHE(vaddr_start) && ADDRESS_IN_IRAM1_CACHE(vaddr_end)) ||
(ADDRESS_IN_IROM0_CACHE(vaddr_start) && ADDRESS_IN_IROM0_CACHE(vaddr_end)) ||
(ADDRESS_IN_DRAM1_CACHE(vaddr_start) && ADDRESS_IN_DRAM1_CACHE(vaddr_end)) ||
(ADDRESS_IN_DROM0_CACHE(vaddr_start) && ADDRESS_IN_DROM0_CACHE(vaddr_end));
}
#ifdef __cplusplus
}
#endif

103
components/hal/esp32c2/include/hal/cache_ll.h Normal file
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@ -0,0 +1,103 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
uint32_t vaddr_end = vaddr_start + len;
if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0;
} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0;
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be disabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
#ifdef __cplusplus
}
#endif

2
components/hal/esp32c2/include/hal/memprot_ll.h
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@ -7,7 +7,7 @@
#pragma once
#include "soc/sensitive_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#ifdef __cplusplus

153
components/hal/esp32c2/include/hal/mmu_ll.h Normal file
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@ -0,0 +1,153 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
(void)mmu_id;
uint32_t page_size_code = REG_GET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE);
return (page_size_code == 0) ? MMU_PAGE_16KB : (page_size_code == 1) ? MMU_PAGE_32KB : MMU_PAGE_64KB;
}
/**
* Set MMU page size
*
* @param size See `mmu_page_size_t`
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
{
uint8_t reg_val = (size == MMU_PAGE_16KB) ? 0 : (size == MMU_PAGE_32KB) ? 1 : 2;
REG_SET_FIELD(EXTMEM_CACHE_CONF_MISC_REG, EXTMEM_CACHE_MMU_PAGE_SIZE, reg_val);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
{
(void)mmu_id;
uint32_t vaddr_end = vaddr_start + len;
return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
}
/**
* To get the MMU table entry id to be mapped
*
* @param mmu_id MMU ID
* @param vaddr virtual address to be mapped
*
* @return
* MMU table entry id
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
(void)mmu_id;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return ((vaddr & MMU_VADDR_MASK) >> shift_code);
}
/**
* Format the paddr to be mappable
*
* @param mmu_id MMU ID
* @param paddr physical address to be mapped
*
* @return
* mmu_val - paddr in MMU table supported format
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
{
(void)mmu_id;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return paddr >> shift_code;
}
/**
* Write to the MMU table to map the virtual memory and the physical memory
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be set into an MMU entry, for physical address
* @param target MMU target physical memory.
*/
__attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
(void)mmu_id;
HAL_ASSERT(target == MMU_TARGET_FLASH0);
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
uint32_t vaddr_end = vaddr_start + len;
if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0;
} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0;
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be disabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
#ifdef __cplusplus
}
#endif

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#pragma once
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/memprot_defs.h"
#include "hal/memprot_types.h"

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
//On esp32c3, MMU Page size is always 64KB
(void)mmu_id;
return MMU_PAGE_64KB;
}
/**
* Set MMU page size
*
* @param size See `mmu_page_size_t`
*
* @note On esp32c3, only supports `MMU_PAGE_64KB`
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
{
HAL_ASSERT(size == MMU_PAGE_64KB);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
{
(void)mmu_id;
uint32_t vaddr_end = vaddr_start + len;
return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
}
/**
* To get the MMU table entry id to be mapped
*
* @param mmu_id MMU ID
* @param vaddr virtual address to be mapped
*
* @return
* MMU table entry id
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
(void)mmu_id;
return ((vaddr & MMU_VADDR_MASK) >> 16);
}
/**
* Format the paddr to be mappable
*
* @param mmu_id MMU ID
* @param paddr physical address to be mapped
*
* @return
* mmu_val - paddr in MMU table supported format
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
{
(void)mmu_id;
return paddr >> 16;
}
/**
* Write to the MMU table to map the virtual memory and the physical memory
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be set into an MMU entry, for physical address
* @param target MMU target physical memory.
*/
__attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
(void)mmu_id;
HAL_ASSERT(target == MMU_TARGET_FLASH0);
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_end`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
uint32_t vaddr_end = vaddr_start + len;
if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end <= IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0;
} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end <= DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0;
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be disabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
}
#ifdef __cplusplus
}
#endif

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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/sensitive_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#ifdef __cplusplus

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
(void)mmu_id;
//On esp32h2, MMU page size is always 64KB
return MMU_PAGE_64KB;
}
/**
* Set MMU page size
*
* @param size See `mmu_page_size_t`
*
* @note On esp32h2, only supports `MMU_PAGE_64KB`
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
{
HAL_ASSERT(size == MMU_PAGE_64KB);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
{
(void)mmu_id;
uint32_t vaddr_end = vaddr_start + len;
return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
}
/**
* To get the MMU table entry id to be mapped
*
* @param mmu_id MMU ID
* @param vaddr virtual address to be mapped
*
* @return
* MMU table entry id
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
(void)mmu_id;
return ((vaddr & MMU_VADDR_MASK) >> 16);
}
/**
* Format the paddr to be mappable
*
* @param mmu_id MMU ID
* @param paddr physical address to be mapped
*
* @return
* mmu_val - paddr in MMU table supported format
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
{
(void)mmu_id;
return paddr >> 16;
}
/**
* Write to the MMU table to map the virtual memory and the physical memory
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be set into an MMU entry, for physical address
* @param target MMU target physical memory.
*/
__attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
(void)mmu_id;
HAL_ASSERT(target == MMU_TARGET_FLASH0);
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include <stdbool.h>
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0);
cache_bus_mask_t mask = 0;
uint32_t vaddr_end = vaddr_start + len;
if (vaddr_start >= IRAM1_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS1;
} else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS0;
mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS0;
mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
} else if (vaddr_start >= DRAM1_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS1;
mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
} else if (vaddr_start >= DPORT_CACHE_ADDRESS_LOW) {
mask |= CACHE_BUS_DBUS2;
mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
} else if (vaddr_start >= DROM0_ADDRESS_LOW) {
mask |= CACHE_BUS_IBUS2;
mask |= (vaddr_end >= DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0;
mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
} else {
abort();
}
return mask;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be disabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0);
uint32_t ibus_mask = 0;
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
//On esp32s2, MMU Page size is always 64KB
(void)mmu_id;
return MMU_PAGE_64KB;
}
/**
* Set MMU page size
*
* @param size See `mmu_page_size_t`
*
* @note On esp32s2, only supports `MMU_PAGE_64KB`
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
{
HAL_ASSERT(size == MMU_PAGE_64KB);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
{
(void)mmu_id;
uint32_t vaddr_end = vaddr_start + len;
return (ADDRESS_IN_DROM0(vaddr_start) && ADDRESS_IN_DROM0(vaddr_end)) ||
(ADDRESS_IN_IRAM1(vaddr_start) && ADDRESS_IN_IRAM1(vaddr_end)) ||
(ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
(ADDRESS_IN_DPORT_CACHE(vaddr_start) && ADDRESS_IN_DPORT_CACHE(vaddr_end)) ||
(ADDRESS_IN_DRAM1(vaddr_start) && ADDRESS_IN_DRAM1(vaddr_end)) ||
(ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
}
/**
* To get the MMU table entry id to be mapped
*
* @param mmu_id MMU ID
* @param vaddr virtual address to be mapped
*
* @return
* MMU table entry id
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
(void)mmu_id;
uint32_t offset = 0;
if (ADDRESS_IN_DROM0(vaddr)) {
offset = PRO_CACHE_IBUS2_MMU_START / 4;
} else if (ADDRESS_IN_IRAM0_CACHE(vaddr)) {
offset = PRO_CACHE_IBUS0_MMU_START / 4;
} else if (ADDRESS_IN_IRAM1(vaddr)) {
offset = PRO_CACHE_IBUS1_MMU_START / 4;
} else if (ADDRESS_IN_DPORT_CACHE(vaddr)) {
offset = PRO_CACHE_DBUS2_MMU_START / 4;
} else if (ADDRESS_IN_DRAM1(vaddr)) {
offset = PRO_CACHE_DBUS1_MMU_START / 4;
} else if (ADDRESS_IN_DRAM0_CACHE(vaddr)) {
offset = PRO_CACHE_DBUS0_MMU_START / 4;
} else {
HAL_ASSERT(false);
}
return offset + ((vaddr & MMU_VADDR_MASK) >> 16);
}
/**
* Format the paddr to be mappable
*
* @param mmu_id MMU ID
* @param paddr physical address to be mapped
*
* @return
* mmu_val - paddr in MMU table supported format
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
{
(void)mmu_id;
return paddr >> 16;
}
/**
* Write to the MMU table to map the virtual memory and the physical memory
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be set into an MMU entry, for physical address
* @param target MMU target physical memory.
*/
__attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
(void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for Cache register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*
* External virtual address can only be accessed when the involved cache buses are enabled.
* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
*
* @param cache_id cache ID (when l1 cache is per core)
* @param vaddr_start virtual address start
* @param len vaddr length
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
cache_bus_mask_t mask = 0;
uint32_t vaddr_end = vaddr_start + len;
if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_IBUS0; //Both cores have their own IBUS0
} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
}
/**
* Enable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be enabled
*/
#if !BOOTLOADER_BUILD
__attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
if (cache_id == 0) {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
} else {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
}
REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
if (cache_id == 1) {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
} else {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
}
REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
}
/**
* Disable the Cache Buses
*
* @param cache_id cache ID (when l1 cache is per core)
* @param mask To know which buses should be disabled
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
if (cache_id == 0) {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
} else {
ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
}
REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
uint32_t dbus_mask = 0;
if (cache_id == 1) {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
} else {
dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
}
REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
}
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for MMU register operations
#pragma once
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Get MMU page size
*
* @param mmu_id MMU ID
*
* @return MMU page size code
*/
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
//On esp32s3, MMU Page size is always 64KB
(void)mmu_id;
return MMU_PAGE_64KB;
}
/**
* Set MMU page size
*
* @param size See `mmu_page_size_t`
*
* @note On esp32s3, only supports `MMU_PAGE_64KB`
*/
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, mmu_page_size_t size)
{
HAL_ASSERT(size == MMU_PAGE_64KB);
}
/**
* Check if the external memory vaddr region is valid
*
* @param mmu_id MMU ID
* @param vaddr_start start of the virtual address
* @param len length, in bytes
*
* @return
* True for valid
*/
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
{
(void)mmu_id;
uint32_t vaddr_end = vaddr_start + len;
return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
}
/**
* To get the MMU table entry id to be mapped
*
* @param mmu_id MMU ID
* @param vaddr virtual address to be mapped
*
* @return
* MMU table entry id
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
(void)mmu_id;
return ((vaddr & MMU_VADDR_MASK) >> 16);
}
/**
* Format the paddr to be mappable
*
* @param mmu_id MMU ID
* @param paddr physical address to be mapped
*
* @return
* mmu_val - paddr in MMU table supported format
*/
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
{
(void)mmu_id;
return paddr >> 16;
}
/**
* Write to the MMU table to map the virtual memory and the physical memory
*
* @param mmu_id MMU ID
* @param entry_id MMU entry ID
* @param mmu_val Value to be set into an MMU entry, for physical address
* @param target MMU target physical memory.
*/
__attribute__((always_inline))
static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
(void)mmu_id;
HAL_ASSERT(entry_id < MMU_MAX_ENTRY_NUM);
uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
}
#ifdef __cplusplus
}
#endif

41
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/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/cache_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Cache init and cache hal context init
*
*/
void cache_hal_init(void);
/**
* Disable the ICache or DCache or both, all the items in the corresponding Cache(s) will be invalideated.
* Next request to these items will trigger a transaction to the external memory (flash / psram)
*
* @note If the autoload feature is enabled, this API will return until the ICache autoload is disabled.
*
* @param type see `cache_type_t`
*/
void cache_hal_disable(cache_type_t type);
/**
* Enable the ICache or DCache or both.
*
* @param type see `cache_type_t`
*/
void cache_hal_enable(cache_type_t type);
#ifdef __cplusplus
}
#endif

39
components/hal/include/hal/cache_types.h Normal file
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@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
CACHE_TYPE_DATA,
CACHE_TYPE_INSTRUCTION,
CACHE_TYPE_ALL //This means both ICache and DCache will be used. On some chips, I/D are controlled by a shared Cache. Also use this enum under this condition. See `SOC_SHARED_IDCACHE_SUPPORTED`.
} cache_type_t;
/**
* @brief Ibuses and Dbuses.
*
* @note
* These enumurations are abstract concepts. Virtual address reside in one of these buses.
* Therefore, use `cache_ll_l1_get_bus(cache_id, vaddr_start, len)` to convert your vaddr into buses first
*/
typedef enum {
CACHE_BUS_IBUS0 = BIT(0),
CACHE_BUS_IBUS1 = BIT(1),
CACHE_BUS_IBUS2 = BIT(2),
CACHE_BUS_DBUS0 = BIT(3),
CACHE_BUS_DBUS1 = BIT(4),
CACHE_BUS_DBUS2 = BIT(5),
} cache_bus_mask_t;
#ifdef __cplusplus
}
#endif

64
components/hal/include/hal/mmu_hal.h Normal file
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@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/mmu_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Unmap all the MMU table. After this all external memory vaddr are not available
*/
void mmu_hal_init(void);
#if !CONFIG_IDF_TARGET_ESP32
/**
* Helper functions to convert the MMU page numbers into bytes. e.g.:
* - When MMU page size is 16KB, page_num = 2 will be converted into 32KB
* - When MMU page size is 32KB, page_num = 2 will be converted into 64KB
*
* @param mmu_id MMU ID
* @param page_num page numbers
*
* @return
* length in byte
*/
uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num);
/**
* Helper functions to convert bytes into MMU page numbers. e.g.:
* - When MMU page size is 16KB, bytes = 64KB will be converted into 4 pages
* - When MMU page size is 32KB, bytes = 64KB will be converted into 2 pages
*
* @param mmu_id MMU ID
* @param bytes length in byte
*
* @return
* length in MMU_PAGE_SIZE
*/
uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes);
/**
* To map a virtual address region to a physical memory region
*
* @param mmu_id MMU ID
* @param mem_type physical memory type, see `mmu_target_t`
* @param vaddr start virtual address to be mapped
* @param paddr start physical address to be mapped
* @param len length to be mapped, in bytes
* @param[out] out_len actual mapped length
*
* @note vaddr and paddr should be aligned with the MMU_PAGE_SIZE, see `mmu_ll.h`
*/
void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len);
#endif
#ifdef __cplusplus
}
#endif

33
components/hal/include/hal/mmu_types.h Normal file
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@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* MMU Page size
*/
typedef enum {
MMU_PAGE_16KB,
MMU_PAGE_32KB,
MMU_PAGE_64KB,
} mmu_page_size_t;
/**
* External physical memory
*/
typedef enum {
MMU_TARGET_FLASH0,
MMU_TARGET_PSRAM0,
} mmu_target_t;
#ifdef __cplusplus
}
#endif

3
components/hal/linker.lf
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@ -1,6 +1,9 @@
[mapping:hal]
archive: libhal.a
entries:
mmu_hal (noflash)
if IDF_TARGET_ESP32 = n:
cache_hal (noflash)
spi_hal_iram (noflash)
spi_slave_hal_iram (noflash)
if UART_ISR_IN_IRAM = y || ESP_PANIC_HANDLER_IRAM = y:

115
components/hal/mmu_hal.c Normal file
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@ -0,0 +1,115 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/param.h>
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_attr.h"
#include "hal/assert.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#include "soc/dport_reg.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#endif
void mmu_hal_init(void)
{
#if CONFIG_IDF_TARGET_ESP32
mmu_init(0);
#if !CONFIG_FREERTOS_UNICORE
/**
* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are necessary to work around a hardware bug.
* See ESP32 Errata 3.1
*/
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
mmu_init(1);
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
#endif
#else //!esp32
Cache_MMU_Init();
#endif
}
#if !CONFIG_IDF_TARGET_ESP32
//If decided, add a jira ticket for implementing these APIs on ESP32
uint32_t mmu_hal_pages_to_bytes(uint32_t mmu_id, uint32_t page_num)
{
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return page_num << shift_code;
}
uint32_t mmu_hal_bytes_to_pages(uint32_t mmu_id, uint32_t bytes)
{
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
switch (page_size) {
case MMU_PAGE_64KB:
shift_code = 16;
break;
case MMU_PAGE_32KB:
shift_code = 15;
break;
case MMU_PAGE_16KB:
shift_code = 14;
break;
default:
HAL_ASSERT(shift_code);
}
return bytes >> shift_code;
}
void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len)
{
uint32_t page_size_in_bytes = mmu_hal_pages_to_bytes(mmu_id, 1);
HAL_ASSERT(vaddr % page_size_in_bytes == 0);
HAL_ASSERT(paddr % page_size_in_bytes == 0);
HAL_ASSERT((paddr + len) <= mmu_hal_pages_to_bytes(mmu_id, MMU_MAX_ENTRY_NUM));
HAL_ASSERT(mmu_ll_check_valid_ext_vaddr_region(mmu_id, vaddr, len));
uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes;
uint32_t entry_id = 0;
uint32_t mmu_val; //This is the physical address in the format that MMU supported
*out_len = mmu_hal_pages_to_bytes(mmu_id, page_num);
entry_id = mmu_ll_get_entry_id(mmu_id, vaddr);
mmu_val = mmu_ll_format_paddr(mmu_id, paddr);
while (page_num) {
mmu_ll_write_entry(mmu_id, entry_id, mmu_val, mem_type);
entry_id++;
mmu_val++;
page_num--;
}
}
#endif //#if !CONFIG_IDF_TARGET_ESP32

2
components/mbedtls/port/sha/dma/sha.c
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@ -33,7 +33,7 @@
#include "esp_crypto_lock.h"
#include "esp_attr.h"
#include "soc/lldesc.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/periph_defs.h"
#include "freertos/FreeRTOS.h"

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@ -139,6 +139,10 @@ config SOC_ADC_MAX_BITWIDTH
int
default 12
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 2

45
components/soc/esp32/include/soc/ext_mem_defs.h Normal file
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@ -0,0 +1,45 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define IRAM0_CACHE_ADDRESS_LOW 0x400D0000
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
#define IRAM1_CACHE_ADDRESS_LOW 0x40400000
#define IRAM1_CACHE_ADDRESS_HIGH 0x40800000
#define IROM0_CACHE_ADDRESS_LOW 0x40800000
#define IROM0_CACHE_ADDRESS_HIGH 0x40C00000
#define DRAM1_CACHE_ADDRESS_LOW 0x3F800000
#define DRAM1_CACHE_ADDRESS_HIGH 0x3FC00000
#define DROM0_CACHE_ADDRESS_LOW 0x3F400000
#define DROM0_CACHE_ADDRESS_HIGH 0x3F800000
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
#define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
#define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
#ifdef __cplusplus
}
#endif
#endif /*_CACHE_MEMORY_H_ */

3
components/soc/esp32/include/soc/soc_caps.h
View File

@ -120,6 +120,9 @@
#define SOC_BROWNOUT_RESET_SUPPORTED 1
#endif
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2

8
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@ -63,10 +63,6 @@ config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default n
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
@ -143,6 +139,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 2

37
components/soc/esp32c2/include/soc/cache_memory.h → components/soc/esp32c2/include/soc/ext_mem_defs.h
View File

@ -6,16 +6,18 @@
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "esp32c2/rom/cache.h"
//TODO IDF-3821, for now it's always 64KB
#define MMU_PAGE_MODE 2
/*IRAM0 is connected with Cache IBUS0*/
#define MMU_PAGE_MODE MMU_Get_Page_Mode()
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
@ -51,6 +53,7 @@ extern "C" {
#define CACHE_DBUS_MMU_START 0
#define CACHE_DBUS_MMU_END 0x100
//TODO, remove these cache function dependencies
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
@ -68,6 +71,7 @@ extern "C" {
#define MMU_BUS_SIZE(i) 0x100
#define MMU_INVALID BIT(6)
#define MMU_VALID 0
#define MMU_TYPE 0
#define MMU_ACCESS_FLASH 0
@ -79,12 +83,29 @@ extern "C" {
#define MMU_TABLE_INVALID_VAL MMU_INVALID
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK (MMU_TABLE_INVALID_VAL - 1)
#define MMU_PAGE_SIZE (0x4000 << (MMU_PAGE_MODE))
#define INVALID_PHY_PAGE (MMU_PAGE_SIZE - 1)
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(6), so value bits are 0x3f
*/
#define MMU_VALID_VAL_MASK 0x3f
/**
* Helper macro to make a MMU entry invalid
* Check this! IDF-3821
*/
#define INVALID_PHY_PAGE 0x7f
/**
* Max MMU entry num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
* 64 * 64KB, means MMU can map 4MB at most
*/
#define MMU_MAX_ENTRY_NUM 64
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK ((0x100000 << (MMU_PAGE_MODE)) - 1)
#define BUS_ADDR_SIZE (0x100000 << (MMU_PAGE_MODE))
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_PMS_MASK 0xffffff
#define CACHE_ICACHE_LOW_SHIFT 0

4
components/soc/esp32c2/include/soc/mmu.h
View File

@ -6,7 +6,7 @@
#pragma once
#include <stdint.h>
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
@ -21,7 +21,7 @@ extern "C" {
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW

4
components/soc/esp32c2/include/soc/soc_caps.h
View File

@ -40,7 +40,6 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 0
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 0
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
/*-------------------------- AES CAPS -----------------------------------------*/
@ -78,6 +77,9 @@
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2

8
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -75,10 +75,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
@ -187,6 +183,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 8

28
components/soc/esp32c3/include/soc/cache_memory.h → components/soc/esp32c3/include/soc/ext_mem_defs.h
View File

@ -6,6 +6,8 @@
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -43,6 +45,7 @@ extern "C" {
#define CACHE_DBUS_MMU_START 0
#define CACHE_DBUS_MMU_END 0x200
//TODO, remove these cache function dependencies
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
@ -60,6 +63,7 @@ extern "C" {
#define MMU_BUS_SIZE(i) 0x200
#define MMU_INVALID BIT(8)
#define MMU_VALID 0
#define MMU_TYPE 0
#define MMU_ACCESS_FLASH 0
@ -71,12 +75,28 @@ extern "C" {
#define MMU_TABLE_INVALID_VAL 0x100
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0xff
#define MMU_PAGE_SIZE 0x10000
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(8), so value bits are 0xff
*/
#define MMU_VALID_VAL_MASK 0xff
/**
* Helper macro to make a MMU entry invalid
*/
#define INVALID_PHY_PAGE 0xffff
/**
* Max MMU entry num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
* 256 * 64KB, means MMU can map 16MB at most
*/
#define MMU_MAX_ENTRY_NUM 256
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK 0x7FFFFF
#define BUS_ADDR_SIZE 0x800000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2

22
components/soc/esp32c3/include/soc/mmu.h
View File

@ -1,20 +1,12 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
@ -29,7 +21,7 @@ extern "C" {
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW

4
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -43,7 +43,6 @@
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
@ -92,6 +91,9 @@
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8

8
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -55,10 +55,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
@ -167,6 +163,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 8

29
components/soc/esp32h2/include/soc/cache_memory.h → components/soc/esp32h2/include/soc/ext_mem_defs.h
View File

@ -6,6 +6,8 @@
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -35,6 +37,7 @@ extern "C" {
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
//TODO, remove these cache function dependencies
#define CACHE_IBUS 0
#define CACHE_IBUS_MMU_START 0
#define CACHE_IBUS_MMU_END 0x200
@ -60,6 +63,7 @@ extern "C" {
#define MMU_BUS_SIZE(i) 0x200
#define MMU_INVALID BIT(8)
#define MMU_VALID 0
#define MMU_TYPE 0
#define MMU_ACCESS_FLASH 0
@ -71,12 +75,27 @@ extern "C" {
#define MMU_TABLE_INVALID_VAL 0x100
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0xff
#define MMU_PAGE_SIZE 0x10000
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(8), so value bits are 0xff
*/
#define MMU_VALID_VAL_MASK 0xff
/**
* Helper macro to make a MMU entry invalid
*/
#define INVALID_PHY_PAGE 0xffff
#define BUS_ADDR_SIZE 0x800000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
/**
* Max MMU entry num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
* 256 * 64KB, means MMU can map 16MB at most
*/
#define MMU_MAX_ENTRY_NUM 256
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK 0x7fffff
#define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2

22
components/soc/esp32h2/include/soc/mmu.h
View File

@ -1,20 +1,12 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
@ -29,7 +21,7 @@ extern "C" {
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW

4
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -46,7 +46,6 @@
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
@ -95,6 +94,9 @@
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CACHE CAPS --------------------------------------*/
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -79,10 +79,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_TEMP_SENSOR_SUPPORTED
bool
default y

25
components/soc/esp32s2/include/soc/cache_memory.h → components/soc/esp32s2/include/soc/ext_mem_defs.h
View File

@ -6,6 +6,8 @@
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -93,6 +95,7 @@ extern "C" {
#define MMU_BUS_SIZE 0x100
#define MMU_INVALID BIT(14)
#define MMU_VALID 0
#define MMU_ACCESS_FLASH BIT(15)
#define MMU_ACCESS_SPIRAM BIT(16)
@ -101,11 +104,23 @@ extern "C" {
#define MMU_TABLE_INVALID_VAL 0x4000
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(14), so value bits are 0x3fff
*/
#define MMU_VALID_VAL_MASK 0x3fff
/**
* Max MMU entry num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
* 16384 * 64KB, means MMU can map 1GB at most
*/
#define MMU_MAX_ENTRY_NUM 16384
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK 0x3FFFFF
#define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BANK_SIZE 8192

22
components/soc/esp32s2/include/soc/mmu.h
View File

@ -1,20 +1,12 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
@ -29,7 +21,7 @@ extern "C" {
#define SOC_MMU_DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW

1
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -58,7 +58,6 @@
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1

29
components/soc/esp32s3/include/soc/cache_memory.h → components/soc/esp32s3/include/soc/ext_mem_defs.h
View File

@ -5,6 +5,8 @@
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -42,6 +44,7 @@ extern "C" {
#define CACHE_DBUS_MMU_START 0
#define CACHE_DBUS_MMU_END 0x800
//TODO, remove these cache function dependencies
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
@ -59,6 +62,7 @@ extern "C" {
#define MMU_BUS_SIZE(i) 0x800
#define MMU_INVALID BIT(14)
#define MMU_VALID 0
#define MMU_TYPE BIT(15)
#define MMU_ACCESS_FLASH 0
#define MMU_ACCESS_SPIRAM BIT(15)
@ -71,12 +75,27 @@ extern "C" {
#define MMU_TABLE_INVALID_VAL 0x4000
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(14), so value bits are 0x3fff
*/
#define MMU_VALID_VAL_MASK 0x3fff
/**
* Helper macro to make a MMU entry invalid
*/
#define INVALID_PHY_PAGE 0xffff
#define BUS_ADDR_SIZE 0x2000000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
/**
* Max MMU entry num.
* `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
* 16384 * 64KB, means MMU can map 1GB at most
*/
#define MMU_MAX_ENTRY_NUM 16384
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK 0x1FFFFFF
#define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2

22
components/soc/esp32s3/include/soc/mmu.h
View File

@ -1,20 +1,12 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
@ -29,7 +21,7 @@ extern "C" {
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW

10
components/spi_flash/cache_utils.c
View File

@ -18,23 +18,23 @@
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#endif
#include "esp_rom_spiflash.h"
#include <soc/soc.h>

10
components/spi_flash/flash_mmap.c
View File

@ -34,25 +34,25 @@
#include "esp32s2/rom/cache.h"
#include "esp_private/mmu_psram.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#include "esp32s3/spiram.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#include "soc/cache_memory.h"
#include "soc/ext_mem_defs.h"
#include "soc/mmu.h"
#endif

2
tools/ci/build_template_app.sh
View File

@ -31,6 +31,8 @@ gen_configs() {
# CONFIG_COMPILER_OPTIMIZATION_DEFAULT with flag -Og
echo "CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y" > esp-idf-template/sdkconfig.ci2.Og
echo "CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG=y" >> esp-idf-template/sdkconfig.ci2.Og
# -Og makes the bootloader too large to fit in the default space, otherwise(!)
echo "CONFIG_PARTITION_TABLE_OFFSET=0x10000" >> esp-idf-template/sdkconfig.ci2.Og
# Needs to be built with specific extra flags
# Same as O2, but also disable assertions.

5
tools/ci/check_copyright_ignore.txt
View File

@ -885,7 +885,6 @@ components/hal/esp32h2/include/hal/gpspi_flash_ll.h
components/hal/esp32h2/include/hal/hmac_hal.h
components/hal/esp32h2/include/hal/hmac_ll.h
components/hal/esp32h2/include/hal/interrupt_controller_ll.h
components/hal/esp32h2/include/hal/memprot_ll.h
components/hal/esp32h2/include/hal/mpu_ll.h
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
components/hal/esp32h2/include/hal/sha_ll.h
@ -1392,7 +1391,6 @@ components/soc/esp32c3/include/soc/i2c_struct.h
components/soc/esp32c3/include/soc/interrupt_core0_reg.h
components/soc/esp32c3/include/soc/interrupt_reg.h
components/soc/esp32c3/include/soc/ledc_reg.h
components/soc/esp32c3/include/soc/mmu.h
components/soc/esp32c3/include/soc/nrx_reg.h
components/soc/esp32c3/include/soc/reset_reasons.h
components/soc/esp32c3/include/soc/rmt_reg.h
@ -1451,7 +1449,6 @@ components/soc/esp32h2/include/soc/gpio_sd_struct.h
components/soc/esp32h2/include/soc/hwcrypto_reg.h
components/soc/esp32h2/include/soc/interrupt_reg.h
components/soc/esp32h2/include/soc/ledc_reg.h
components/soc/esp32h2/include/soc/mmu.h
components/soc/esp32h2/include/soc/nrx_reg.h
components/soc/esp32h2/include/soc/rtc_caps.h
components/soc/esp32h2/include/soc/rtc_i2c_reg.h
@ -1512,7 +1509,6 @@ components/soc/esp32s2/include/soc/interrupt_reg.h
components/soc/esp32s2/include/soc/ledc_reg.h
components/soc/esp32s2/include/soc/ledc_struct.h
components/soc/esp32s2/include/soc/memprot_defs.h
components/soc/esp32s2/include/soc/mmu.h
components/soc/esp32s2/include/soc/nrx_reg.h
components/soc/esp32s2/include/soc/reset_reasons.h
components/soc/esp32s2/include/soc/rtc_cntl_reg.h
@ -1601,7 +1597,6 @@ components/soc/esp32s3/include/soc/interrupt_reg.h
components/soc/esp32s3/include/soc/interrupt_struct.h
components/soc/esp32s3/include/soc/ledc_reg.h
components/soc/esp32s3/include/soc/ledc_struct.h
components/soc/esp32s3/include/soc/mmu.h
components/soc/esp32s3/include/soc/mpu_caps.h
components/soc/esp32s3/include/soc/nrx_reg.h
components/soc/esp32s3/include/soc/peri_backup_reg.h