mirror of
https://github.com/espressif/esp-idf.git
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ESP8684: Clean up ESP8684 code, remove useless code, update headers
This commit is contained in:
Cao Sen Miao
parent
6380585649
commit
463cf2cf1c
@ -1,40 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "regi2c_ctrl.h"
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/* Analog function control register */
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#define ANA_CONFIG_REG 0x6000E044
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#define ANA_CONFIG_S (8)
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#define ANA_CONFIG_M (0x3FF)
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/* Clear to enable APLL */
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#define I2C_APLL_M (BIT(14))
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/* Clear to enable BBPLL */
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#define I2C_BBPLL_M (BIT(17))
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/* ROM functions which read/write internal control bus */
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uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
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void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
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/* Convenience macros for the above functions, these use register definitions
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* from i2c_apll.h/i2c_bbpll.h header files.
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*/
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#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
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rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
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#define I2C_READREG_MASK_RTC(block, reg_add) \
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rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
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#define I2C_WRITEREG_RTC(block, reg_add, indata) \
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rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
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#define I2C_READREG_RTC(block, reg_add) \
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rom_i2c_readReg(block, block##_HOSTID, reg_add)
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@ -1,40 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "regi2c_ctrl.h"
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/* Analog function control register */
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#define ANA_CONFIG_REG 0x6000E044
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#define ANA_CONFIG_S (8)
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#define ANA_CONFIG_M (0x3FF)
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/* Clear to enable APLL */
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#define I2C_APLL_M (BIT(14))
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/* Clear to enable BBPLL */
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#define I2C_BBPLL_M (BIT(17))
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/* ROM functions which read/write internal control bus */
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uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
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void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
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/* Convenience macros for the above functions, these use register definitions
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* from i2c_apll.h/i2c_bbpll.h header files.
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*/
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#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
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rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
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#define I2C_READREG_MASK_RTC(block, reg_add) \
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rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
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#define I2C_WRITEREG_RTC(block, reg_add, indata) \
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rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
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#define I2C_READREG_RTC(block, reg_add) \
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rom_i2c_readReg(block, block##_HOSTID, reg_add)
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@ -1,40 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "regi2c_ctrl.h"
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/* Analog function control register */
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#define ANA_CONFIG_REG 0x6000E044
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#define ANA_CONFIG_S (8)
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#define ANA_CONFIG_M (0x3FF)
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/* Clear to enable APLL */
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#define I2C_APLL_M (BIT(14))
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/* Clear to enable BBPLL */
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#define I2C_BBPLL_M (BIT(17))
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/* ROM functions which read/write internal control bus */
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uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
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uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
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void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
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void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
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/* Convenience macros for the above functions, these use register definitions
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* from i2c_apll.h/i2c_bbpll.h header files.
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*/
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#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
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rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
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#define I2C_READREG_MASK_RTC(block, reg_add) \
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rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
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#define I2C_WRITEREG_RTC(block, reg_add, indata) \
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rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
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#define I2C_READREG_RTC(block, reg_add) \
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rom_i2c_readReg(block, block##_HOSTID, reg_add)
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@ -14,7 +14,6 @@
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#include "soc/efuse_periph.h"
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#include "soc/apb_ctrl_reg.h"
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#include "hal/cpu_hal.h"
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#include "regi2c_ctrl.h"
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#include "soc_log.h"
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@ -8,7 +8,6 @@
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#include <assert.h>
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/apb_ctrl_reg.h"
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typedef enum {
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PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */
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@ -9,7 +9,7 @@
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "soc/syscon_reg.h"
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#include "soc/rtc.h"
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#include "soc/bb_reg.h"
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#include "soc/nrx_reg.h"
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@ -29,9 +29,9 @@
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void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
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@ -40,14 +40,14 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
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if (cfg.sram_fpu) {
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REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, APB_CTRL_SRAM_POWER_UP);
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
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} else {
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REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_SRAM_POWER_UP, 0);
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
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}
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if (cfg.rom_ram_fpu) {
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REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, APB_CTRL_ROM_POWER_UP);
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
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} else {
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REG_SET_FIELD(APB_CTRL_MEM_POWER_UP_REG, APB_CTRL_ROM_POWER_UP, 0);
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
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}
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}
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@ -101,13 +101,11 @@ typedef enum {
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MAC_TRIG = BIT5,
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UART0_TRIG = BIT6,
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UART1_TRIG = BIT7,
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TOUCH_TRIG = BIT8,
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SAR_TRIG = BIT9,
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BT_TRIG = BIT10,
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RISCV_TRIG = BIT11,
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XTAL_DEAD_TRIG = BIT12,
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RISCV_TRAP_TRIG = BIT13,
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USB_TRIG = BIT14
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RISCV_TRAP_TRIG = BIT13
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} WAKEUP_REASON;
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typedef enum {
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@ -120,13 +118,11 @@ typedef enum {
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MAC_TRIG_EN = MAC_TRIG,
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UART0_TRIG_EN = UART0_TRIG,
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UART1_TRIG_EN = UART1_TRIG,
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TOUCH_TRIG_EN = TOUCH_TRIG,
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SAR_TRIG_EN = SAR_TRIG,
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BT_TRIG_EN = BT_TRIG,
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RISCV_TRIG_EN = RISCV_TRIG,
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XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
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RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
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USB_TRIG_EN = USB_TRIG
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RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG
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} WAKEUP_ENABLE;
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/**
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@ -9,7 +9,7 @@
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "soc/syscon_reg.h"
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#ifdef __cplusplus
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extern "C" {
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@ -42,7 +42,7 @@ static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
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static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr)
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{
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/* write memory address to register */
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REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_LINK_ADDR, (uint32_t)addr);
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REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr);
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/* Enable clock */
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
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/* Enable retention when cpu sleep enable */
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@ -1,16 +1,8 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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@ -20,8 +12,6 @@
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#include "esp_bit_defs.h"
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#endif
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#include "sdkconfig.h"
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#define PRO_CPU_NUM (0)
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#define DR_REG_SYSTEM_BASE 0x600c0000
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@ -12,8 +12,6 @@
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#include "esp_bit_defs.h"
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#endif
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#include "sdkconfig.h"
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#define PRO_CPU_NUM (0)
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#define DR_REG_SYSTEM_BASE 0x600c0000
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@ -235,46 +235,6 @@ config SOC_MPU_REGION_WO_SUPPORTED
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bool
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default n
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config SOC_RMT_GROUPS
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int
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default 1
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config SOC_RMT_TX_CANDIDATES_PER_GROUP
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int
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default 2
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config SOC_RMT_RX_CANDIDATES_PER_GROUP
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int
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default 2
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config SOC_RMT_CHANNELS_PER_GROUP
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int
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default 4
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config SOC_RMT_MEM_WORDS_PER_CHANNEL
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int
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default 48
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config SOC_RMT_SUPPORT_RX_PINGPONG
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bool
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default y
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config SOC_RMT_SUPPORT_RX_DEMODULATION
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bool
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default y
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config SOC_RMT_SUPPORT_TX_LOOP_COUNT
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bool
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default y
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config SOC_RMT_SUPPORT_TX_SYNCHRO
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bool
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default y
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config SOC_RMT_SUPPORT_XTAL
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bool
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default y
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config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
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int
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default 128
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@ -1,584 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_APB_CTRL_REG_H_
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#define _SOC_APB_CTRL_REG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
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/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: reg_rst_tick_cnt.*/
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#define APB_CTRL_RST_TICK_CNT (BIT(12))
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#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
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#define APB_CTRL_RST_TICK_CNT_V 0x1
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#define APB_CTRL_RST_TICK_CNT_S 12
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/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
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/*description: reg_clk_en.*/
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#define APB_CTRL_CLK_EN (BIT(11))
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#define APB_CTRL_CLK_EN_M (BIT(11))
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#define APB_CTRL_CLK_EN_V 0x1
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#define APB_CTRL_CLK_EN_S 11
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/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
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/*description: reg_clk_320m_en.*/
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#define APB_CTRL_CLK_320M_EN (BIT(10))
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#define APB_CTRL_CLK_320M_EN_M (BIT(10))
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#define APB_CTRL_CLK_320M_EN_V 0x1
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#define APB_CTRL_CLK_320M_EN_S 10
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/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
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/*description: reg_pre_div_cnt.*/
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#define APB_CTRL_PRE_DIV_CNT 0x000003FF
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#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
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#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
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#define APB_CTRL_PRE_DIV_CNT_S 0
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#define APB_CTRL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
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/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
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/*description: reg_tick_enable.*/
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#define APB_CTRL_TICK_ENABLE (BIT(16))
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#define APB_CTRL_TICK_ENABLE_M (BIT(16))
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#define APB_CTRL_TICK_ENABLE_V 0x1
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#define APB_CTRL_TICK_ENABLE_S 16
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/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
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/*description: reg_ck8m_tick_num.*/
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#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
|
||||
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
|
||||
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
|
||||
#define APB_CTRL_CK8M_TICK_NUM_S 8
|
||||
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
|
||||
/*description: reg_xtal_tick_num.*/
|
||||
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
|
||||
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
|
||||
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
|
||||
#define APB_CTRL_XTAL_TICK_NUM_S 0
|
||||
|
||||
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8)
|
||||
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: reg_clk_xtal_oen.*/
|
||||
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
|
||||
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
|
||||
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_XTAL_OEN_S 10
|
||||
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: reg_clk40x_bb_oen.*/
|
||||
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
|
||||
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
|
||||
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
|
||||
#define APB_CTRL_CLK40X_BB_OEN_S 9
|
||||
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
|
||||
/*description: reg_clk_dac_cpu_oen.*/
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
|
||||
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: reg_clk_adc_inf_oen.*/
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
|
||||
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: reg_clk_320m_oen.*/
|
||||
#define APB_CTRL_CLK_320M_OEN (BIT(6))
|
||||
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
|
||||
#define APB_CTRL_CLK_320M_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_320M_OEN_S 6
|
||||
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: reg_clk160_oen.*/
|
||||
#define APB_CTRL_CLK160_OEN (BIT(5))
|
||||
#define APB_CTRL_CLK160_OEN_M (BIT(5))
|
||||
#define APB_CTRL_CLK160_OEN_V 0x1
|
||||
#define APB_CTRL_CLK160_OEN_S 5
|
||||
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: reg_clk80_oen.*/
|
||||
#define APB_CTRL_CLK80_OEN (BIT(4))
|
||||
#define APB_CTRL_CLK80_OEN_M (BIT(4))
|
||||
#define APB_CTRL_CLK80_OEN_V 0x1
|
||||
#define APB_CTRL_CLK80_OEN_S 4
|
||||
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: reg_clk_bb_oen.*/
|
||||
#define APB_CTRL_CLK_BB_OEN (BIT(3))
|
||||
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
|
||||
#define APB_CTRL_CLK_BB_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_BB_OEN_S 3
|
||||
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: reg_clk44_oen.*/
|
||||
#define APB_CTRL_CLK44_OEN (BIT(2))
|
||||
#define APB_CTRL_CLK44_OEN_M (BIT(2))
|
||||
#define APB_CTRL_CLK44_OEN_V 0x1
|
||||
#define APB_CTRL_CLK44_OEN_S 2
|
||||
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: reg_clk22_oen.*/
|
||||
#define APB_CTRL_CLK22_OEN (BIT(1))
|
||||
#define APB_CTRL_CLK22_OEN_M (BIT(1))
|
||||
#define APB_CTRL_CLK22_OEN_V 0x1
|
||||
#define APB_CTRL_CLK22_OEN_S 1
|
||||
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: reg_clk20_oen.*/
|
||||
#define APB_CTRL_CLK20_OEN (BIT(0))
|
||||
#define APB_CTRL_CLK20_OEN_M (BIT(0))
|
||||
#define APB_CTRL_CLK20_OEN_V 0x1
|
||||
#define APB_CTRL_CLK20_OEN_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
|
||||
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: reg_wifi_bb_cfg.*/
|
||||
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
|
||||
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
|
||||
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: reg_wifi_bb_cfg_2.*/
|
||||
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14)
|
||||
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: reg_wifi_clk_en.*/
|
||||
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
|
||||
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_CLK_EN_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
|
||||
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: reg_wifi_rst.*/
|
||||
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
|
||||
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_RST_S 0
|
||||
|
||||
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
|
||||
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: reg_peri_io_swap.*/
|
||||
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
|
||||
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
|
||||
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
|
||||
#define APB_CTRL_PERI_IO_SWAP_S 0
|
||||
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
|
||||
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: reg_ext_mem_pms_lock.*/
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
|
||||
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: reg_flash_ace0_attr.*/
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C)
|
||||
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: reg_flash_ace1_attr.*/
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
|
||||
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: reg_flash_ace2_attr.*/
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
|
||||
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: reg_flash_ace3_attr.*/
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
|
||||
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: reg_flash_ace0_addr_s.*/
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C)
|
||||
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
|
||||
/*description: reg_flash_ace1_addr_s.*/
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
|
||||
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
|
||||
/*description: reg_flash_ace2_addr_s.*/
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
|
||||
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
|
||||
/*description: reg_flash_ace3_addr_s.*/
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
|
||||
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: reg_flash_ace0_size.*/
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C)
|
||||
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: reg_flash_ace1_size.*/
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
|
||||
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: reg_flash_ace2_size.*/
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
|
||||
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: reg_flash_ace3_size.*/
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
|
||||
/*description: reg_spi_mem_reject_cde.*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: reg_spi_mem_reject_clr.*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
|
||||
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: reg_spi_mem_reject_int.*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: reg_spi_mem_reject_addr.*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
|
||||
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: reg_sdio_win_access_en.*/
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
|
||||
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: reg_redcy_andor.*/
|
||||
#define APB_CTRL_REDCY_ANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_ANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: reg_redcy_sig0.*/
|
||||
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
|
||||
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
|
||||
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: reg_redcy_nandor.*/
|
||||
#define APB_CTRL_REDCY_NANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_NANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: reg_redcy_sig1.*/
|
||||
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
|
||||
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_S 0
|
||||
|
||||
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
|
||||
/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: reg_freq_mem_force_pd.*/
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7
|
||||
/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: reg_freq_mem_force_pu.*/
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6
|
||||
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: reg_dc_mem_force_pd.*/
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
|
||||
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: reg_dc_mem_force_pu.*/
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: reg_pbus_mem_force_pd.*/
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: reg_pbus_mem_force_pu.*/
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: reg_agc_mem_force_pd.*/
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: reg_agc_mem_force_pu.*/
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0)
|
||||
/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: reg_nobypass_cpu_iso_rst.*/
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
|
||||
/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: reg_retention_link_addr.*/
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA4)
|
||||
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
|
||||
/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
|
||||
hen only when have access the sram have clock.*/
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3
|
||||
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
|
||||
en only when have access the rom have clock.*/
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xA8)
|
||||
/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
|
||||
/*description: Set 1 to let sram power down.*/
|
||||
#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_V 0xF
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_S 3
|
||||
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set 1 to let rom power down.*/
|
||||
#define APB_CTRL_ROM_POWER_DOWN 0x00000007
|
||||
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
|
||||
#define APB_CTRL_ROM_POWER_DOWN_V 0x7
|
||||
#define APB_CTRL_ROM_POWER_DOWN_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xAC)
|
||||
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
|
||||
/*description: Set 1 to let sram power up.*/
|
||||
#define APB_CTRL_SRAM_POWER_UP 0x0000000F
|
||||
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
|
||||
#define APB_CTRL_SRAM_POWER_UP_V 0xF
|
||||
#define APB_CTRL_SRAM_POWER_UP_S 3
|
||||
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set 1 to let rom power up.*/
|
||||
#define APB_CTRL_ROM_POWER_UP 0x00000007
|
||||
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
|
||||
#define APB_CTRL_ROM_POWER_UP_V 0x7
|
||||
#define APB_CTRL_ROM_POWER_UP_S 0
|
||||
|
||||
#define APB_CTRL_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xB0)
|
||||
/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: reg_rnd_data.*/
|
||||
#define APB_CTRL_RND_DATA 0xFFFFFFFF
|
||||
#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
|
||||
#define APB_CTRL_RND_DATA_V 0xFFFFFFFF
|
||||
#define APB_CTRL_RND_DATA_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xB4)
|
||||
/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: reg_peri_backup_ena.*/
|
||||
#define APB_CTRL_PERI_BACKUP_ENA (BIT(31))
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31))
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_S 31
|
||||
/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: reg_peri_backup_to_mem.*/
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30))
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30))
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30
|
||||
/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: reg_peri_backup_start.*/
|
||||
#define APB_CTRL_PERI_BACKUP_START (BIT(29))
|
||||
#define APB_CTRL_PERI_BACKUP_START_M (BIT(29))
|
||||
#define APB_CTRL_PERI_BACKUP_START_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_START_S 29
|
||||
/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
|
||||
/*description: reg_peri_backup_size.*/
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_S 19
|
||||
/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
|
||||
/*description: reg_peri_backup_tout_thres.*/
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9
|
||||
/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
|
||||
/*description: reg_peri_backup_burst_limit.*/
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4
|
||||
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
|
||||
/*description: reg_peri_backup_flow_err.*/
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xB8)
|
||||
/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: reg_backup_apb_start_addr.*/
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xBC)
|
||||
/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: reg_backup_mem_start_addr.*/
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xC0)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_err_int_raw.*/
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_done_int_raw.*/
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xC4)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_err_int_st.*/
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_done_int_st.*/
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xC8)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_err_int_ena.*/
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_done_int_ena.*/
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xD0)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_err_int_clr.*/
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: reg_peri_backup_done_int_clr.*/
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0
|
||||
|
||||
#define APB_CTRL_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
|
||||
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
|
||||
/*description: reg_dateVersion control.*/
|
||||
#define APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
|
||||
#define APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_CTRL_REG_H_ */
|
||||
@ -1,481 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_APB_CTRL_STRUCT_H_
|
||||
#define _SOC_APB_CTRL_STRUCT_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
typedef volatile struct apb_ctrl_dev_s{
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div : 10; /*reg_pre_div_cnt*/
|
||||
uint32_t clk_320m_en : 1; /*reg_clk_320m_en*/
|
||||
uint32_t clk_en : 1; /*reg_clk_en*/
|
||||
uint32_t rst_tick : 1; /*reg_rst_tick_cnt*/
|
||||
uint32_t reserved13 : 19; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal_tick : 8; /*reg_xtal_tick_num*/
|
||||
uint32_t ck8m_tick : 8; /*reg_ck8m_tick_num*/
|
||||
uint32_t tick_enable : 1; /*reg_tick_enable*/
|
||||
uint32_t reserved17 : 15; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen : 1; /*reg_clk20_oen*/
|
||||
uint32_t clk22_oen : 1; /*reg_clk22_oen*/
|
||||
uint32_t clk44_oen : 1; /*reg_clk44_oen*/
|
||||
uint32_t clk_bb_oen : 1; /*reg_clk_bb_oen*/
|
||||
uint32_t clk80_oen : 1; /*reg_clk80_oen*/
|
||||
uint32_t clk160_oen : 1; /*reg_clk160_oen*/
|
||||
uint32_t clk_320m_oen : 1; /*reg_clk_320m_oen*/
|
||||
uint32_t clk_adc_inf_oen : 1; /*reg_clk_adc_inf_oen*/
|
||||
uint32_t clk_dac_cpu_oen : 1; /*reg_clk_dac_cpu_oen*/
|
||||
uint32_t clk40x_bb_oen : 1; /*reg_clk40x_bb_oen*/
|
||||
uint32_t clk_xtal_oen : 1; /*reg_clk_xtal_oen*/
|
||||
uint32_t reserved11 : 21; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg;
|
||||
uint32_t wifi_bb_cfg_2;
|
||||
uint32_t wifi_clk_en;
|
||||
uint32_t wifi_rst_en;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap : 8; /*reg_peri_io_swap*/
|
||||
uint32_t reserved8 : 24; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock : 1; /*reg_ext_mem_pms_lock*/
|
||||
uint32_t reserved1 : 31; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
uint32_t reserved_24;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr : 2; /*reg_flash_ace0_attr*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr : 2; /*reg_flash_ace1_attr*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr : 2; /*reg_flash_ace2_attr*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr : 2; /*reg_flash_ace3_attr*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr;
|
||||
uint32_t flash_ace1_addr;
|
||||
uint32_t flash_ace2_addr;
|
||||
uint32_t flash_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size : 13; /*reg_flash_ace0_size*/
|
||||
uint32_t reserved13 : 19; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size : 13; /*reg_flash_ace1_size*/
|
||||
uint32_t reserved13 : 19; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size : 13; /*reg_flash_ace2_size*/
|
||||
uint32_t reserved13 : 19; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size : 13; /*reg_flash_ace3_size*/
|
||||
uint32_t reserved13 : 19; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int : 1; /*reg_spi_mem_reject_int*/
|
||||
uint32_t spi_mem_reject_clr : 1; /*reg_spi_mem_reject_clr*/
|
||||
uint32_t spi_mem_reject_cde : 5; /*reg_spi_mem_reject_cde*/
|
||||
uint32_t reserved7 : 25; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en : 1; /*reg_sdio_win_access_en*/
|
||||
uint32_t reserved1 : 31; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0 : 31; /*reg_redcy_sig0*/
|
||||
uint32_t redcy_andor : 1; /*reg_redcy_andor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1 : 31; /*reg_redcy_sig1*/
|
||||
uint32_t redcy_nandor : 1; /*reg_redcy_nandor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu : 1; /*reg_agc_mem_force_pu*/
|
||||
uint32_t agc_mem_force_pd : 1; /*reg_agc_mem_force_pd*/
|
||||
uint32_t pbus_mem_force_pu : 1; /*reg_pbus_mem_force_pu*/
|
||||
uint32_t pbus_mem_force_pd : 1; /*reg_pbus_mem_force_pd*/
|
||||
uint32_t dc_mem_force_pu : 1; /*reg_dc_mem_force_pu*/
|
||||
uint32_t dc_mem_force_pd : 1; /*reg_dc_mem_force_pd*/
|
||||
uint32_t freq_mem_force_pu : 1; /*reg_freq_mem_force_pu*/
|
||||
uint32_t freq_mem_force_pd : 1; /*reg_freq_mem_force_pd*/
|
||||
uint32_t reserved8 : 24; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_link_addr : 27; /*reg_retention_link_addr*/
|
||||
uint32_t nobypass_cpu_iso_rst : 1; /*reg_nobypass_cpu_iso_rst*/
|
||||
uint32_t reserved28 : 4; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on : 3; /*Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock*/
|
||||
uint32_t sram_clkgate_force_on : 4; /*Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock*/
|
||||
uint32_t reserved7 : 25; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down : 3; /*Set 1 to let rom power down*/
|
||||
uint32_t sram_power_down : 4; /*Set 1 to let sram power down*/
|
||||
uint32_t reserved7 : 25; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up : 3; /*Set 1 to let rom power up*/
|
||||
uint32_t sram_power_up : 4; /*Set 1 to let sram power up*/
|
||||
uint32_t reserved7 : 25; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
uint32_t rnd_data;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 1; /*Reserved.*/
|
||||
uint32_t peri_backup_flow_err : 2; /*reg_peri_backup_flow_err*/
|
||||
uint32_t reserved3 : 1; /*Reserved.*/
|
||||
uint32_t peri_backup_burst_limit : 5; /*reg_peri_backup_burst_limit*/
|
||||
uint32_t peri_backup_tout_thres : 10; /*reg_peri_backup_tout_thres*/
|
||||
uint32_t peri_backup_size : 10; /*reg_peri_backup_size*/
|
||||
uint32_t peri_backup_start : 1; /*reg_peri_backup_start*/
|
||||
uint32_t peri_backup_to_mem : 1; /*reg_peri_backup_to_mem*/
|
||||
uint32_t peri_backup_ena : 1; /*reg_peri_backup_ena*/
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_config;
|
||||
uint32_t peri_backup_addr;
|
||||
uint32_t peri_backup_mem_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_raw*/
|
||||
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_raw*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_st*/
|
||||
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_st*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_ena*/
|
||||
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_ena*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_ena;
|
||||
uint32_t reserved_cc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_clr*/
|
||||
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_clr*/
|
||||
uint32_t reserved2 : 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_clr;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date;
|
||||
} apb_ctrl_dev_t;
|
||||
extern apb_ctrl_dev_t APB_CTRL;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_CTRL_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -14,26 +14,20 @@ typedef enum {
|
||||
PERIPH_LEDC_MODULE = 0,
|
||||
PERIPH_UART0_MODULE,
|
||||
PERIPH_UART1_MODULE,
|
||||
PERIPH_USB_DEVICE_MODULE,
|
||||
PERIPH_I2C0_MODULE,
|
||||
PERIPH_TIMG0_MODULE,
|
||||
PERIPH_TIMG1_MODULE, //No timg1 on esp8684, please remove TODO: IDF-3825
|
||||
PERIPH_UHCI0_MODULE,
|
||||
PERIPH_RMT_MODULE,
|
||||
PERIPH_SPI_MODULE, //SPI1
|
||||
PERIPH_SPI2_MODULE, //SPI2
|
||||
PERIPH_TWAI_MODULE,
|
||||
PERIPH_RNG_MODULE,
|
||||
PERIPH_WIFI_MODULE,
|
||||
PERIPH_BT_MODULE,
|
||||
PERIPH_WIFI_BT_COMMON_MODULE,
|
||||
PERIPH_BT_BASEBAND_MODULE,
|
||||
PERIPH_BT_LC_MODULE,
|
||||
PERIPH_RSA_MODULE,
|
||||
PERIPH_AES_MODULE,
|
||||
PERIPH_SHA_MODULE,
|
||||
PERIPH_HMAC_MODULE,
|
||||
PERIPH_DS_MODULE,
|
||||
PERIPH_GDMA_MODULE,
|
||||
PERIPH_SYSTIMER_MODULE,
|
||||
PERIPH_SARADC_MODULE,
|
||||
|
||||
@ -588,7 +588,6 @@ typedef struct {
|
||||
uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep
|
||||
uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep
|
||||
uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep
|
||||
uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep
|
||||
uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
|
||||
@ -603,7 +602,6 @@ typedef struct {
|
||||
.dig_fpu = (val), \
|
||||
.rtc_fpu = (val), \
|
||||
.cpu_fpu = (val), \
|
||||
.i2s_fpu = (val), \
|
||||
.bb_fpu = (val), \
|
||||
.nrx_fpu = (val), \
|
||||
.fe_fpu = (val), \
|
||||
|
||||
@ -1,676 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_RTC_I2C_REG_H_
|
||||
#define _SOC_RTC_I2C_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
|
||||
/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
|
||||
/*description: time period that scl = 0*/
|
||||
#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
|
||||
/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: rtc i2c reg clk gating*/
|
||||
#define RTC_I2C_CLK_EN (BIT(31))
|
||||
#define RTC_I2C_CLK_EN_M (BIT(31))
|
||||
#define RTC_I2C_CLK_EN_V 0x1
|
||||
#define RTC_I2C_CLK_EN_S 31
|
||||
/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: rtc i2c sw reset*/
|
||||
#define RTC_I2C_RESET (BIT(30))
|
||||
#define RTC_I2C_RESET_M (BIT(30))
|
||||
#define RTC_I2C_RESET_V 0x1
|
||||
#define RTC_I2C_RESET_S 30
|
||||
/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29))
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29))
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_S 29
|
||||
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: receive lsb first*/
|
||||
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_M (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_V 0x1
|
||||
#define RTC_I2C_RX_LSB_FIRST_S 5
|
||||
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: transit lsb first*/
|
||||
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_M (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_V 0x1
|
||||
#define RTC_I2C_TX_LSB_FIRST_S 4
|
||||
/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: force start*/
|
||||
#define RTC_I2C_TRANS_START (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_V 0x1
|
||||
#define RTC_I2C_TRANS_START_S 3
|
||||
/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: 1=master 0=slave*/
|
||||
#define RTC_I2C_MS_MODE (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_M (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_V 0x1
|
||||
#define RTC_I2C_MS_MODE_S 2
|
||||
/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: 1=push pull 0=open drain*/
|
||||
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_V 0x1
|
||||
#define RTC_I2C_SCL_FORCE_OUT_S 1
|
||||
/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1=push pull 0=open drain*/
|
||||
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_V 0x1
|
||||
#define RTC_I2C_SDA_FORCE_OUT_S 0
|
||||
|
||||
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
|
||||
/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
|
||||
/*description: scl last status*/
|
||||
#define RTC_I2C_SCL_STATE_LAST 0x00000007
|
||||
#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
|
||||
#define RTC_I2C_SCL_STATE_LAST_V 0x7
|
||||
#define RTC_I2C_SCL_STATE_LAST_S 28
|
||||
/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
|
||||
/*description: i2c last main status*/
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
|
||||
/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
|
||||
/*description: shifter content*/
|
||||
#define RTC_I2C_SHIFT 0x000000FF
|
||||
#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
|
||||
#define RTC_I2C_SHIFT_V 0xFF
|
||||
#define RTC_I2C_SHIFT_S 16
|
||||
/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
|
||||
/*description: which operation is working*/
|
||||
#define RTC_I2C_OP_CNT 0x00000003
|
||||
#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
|
||||
#define RTC_I2C_OP_CNT_V 0x3
|
||||
#define RTC_I2C_OP_CNT_S 6
|
||||
/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: One byte transit done*/
|
||||
#define RTC_I2C_BYTE_TRANS (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_M (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_V 0x1
|
||||
#define RTC_I2C_BYTE_TRANS_S 5
|
||||
/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: slave reg sub address*/
|
||||
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_V 0x1
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_S 4
|
||||
/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: bus is busy*/
|
||||
#define RTC_I2C_BUS_BUSY (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_M (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_V 0x1
|
||||
#define RTC_I2C_BUS_BUSY_S 3
|
||||
/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: arbitration is lost*/
|
||||
#define RTC_I2C_ARB_LOST (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_M (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_V 0x1
|
||||
#define RTC_I2C_ARB_LOST_S 2
|
||||
/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: slave read or write*/
|
||||
#define RTC_I2C_SLAVE_RW (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_M (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_V 0x1
|
||||
#define RTC_I2C_SLAVE_RW_S 1
|
||||
/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: ack response*/
|
||||
#define RTC_I2C_ACK_REC (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_M (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_V 0x1
|
||||
#define RTC_I2C_ACK_REC_S 0
|
||||
|
||||
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
|
||||
/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
|
||||
/*description: time out threshold*/
|
||||
#define RTC_I2C_TIMEOUT 0x000FFFFF
|
||||
#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
|
||||
#define RTC_I2C_TIMEOUT_V 0xFFFFF
|
||||
#define RTC_I2C_TIMEOUT_S 0
|
||||
|
||||
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
|
||||
/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: i2c 10bit mode enable*/
|
||||
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_V 0x1
|
||||
#define RTC_I2C_ADDR_10BIT_EN_S 31
|
||||
/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
|
||||
/*description: slave address*/
|
||||
#define RTC_I2C_SLAVE_ADDR 0x00007FFF
|
||||
#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
|
||||
#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
|
||||
#define RTC_I2C_SLAVE_ADDR_S 0
|
||||
|
||||
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
|
||||
/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
|
||||
/*description: time period that scl = 1*/
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
|
||||
/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
|
||||
/*description: time period for SDA to toggle after SCL goes low*/
|
||||
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF
|
||||
#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
|
||||
#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF
|
||||
#define RTC_I2C_SDA_DUTY_NUM_S 0
|
||||
|
||||
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
|
||||
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
|
||||
/*description: time period for SCL to toggle after I2C start is triggered*/
|
||||
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
|
||||
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_START_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
|
||||
/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
|
||||
/*description: time period for SCL to stop after I2C end is triggered*/
|
||||
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
|
||||
/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: clear detect start interrupt*/
|
||||
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: clear transit load data complete interrupt*/
|
||||
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: clear receive data interrupt*/
|
||||
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: clear ack error interrupt*/
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: clear time out interrupt*/
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: clear transit complete interrupt*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: clear master transit complete interrupt*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: clear arbitration lost interrupt*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: clear slave transit complete interrupt*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
|
||||
|
||||
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028)
|
||||
/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: detect start interrupt raw*/
|
||||
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: transit data interrupt raw*/
|
||||
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: receive data interrupt raw*/
|
||||
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: ack error interrupt raw*/
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: time out interrupt raw*/
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: transit complete interrupt raw*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: master transit complete interrupt raw*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: arbitration lost interrupt raw*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: slave transit complete interrupt raw*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
|
||||
|
||||
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c)
|
||||
/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: detect start interrupt state*/
|
||||
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_ST_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: transit data interrupt state*/
|
||||
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_ST_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: receive data interrupt state*/
|
||||
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_ST_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: ack error interrupt state*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: time out interrupt state*/
|
||||
#define RTC_I2C_TIMEOUT_INT_ST (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: transit complete interrupt state*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: master transit complete interrupt state*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: arbitration lost interrupt state*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: slave transit complete interrupt state*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
|
||||
|
||||
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030)
|
||||
/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: enable detect start interrupt*/
|
||||
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: enable transit data interrupt*/
|
||||
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: enable receive data interrupt*/
|
||||
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: enable eack error interrupt*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: enable time out interrupt*/
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: enable transit complete interrupt*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: enable master transit complete interrupt*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable arbitration lost interrupt*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable slave transit complete interrupt*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
|
||||
|
||||
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034)
|
||||
/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: i2c done*/
|
||||
#define RTC_I2C_DONE (BIT(31))
|
||||
#define RTC_I2C_DONE_M (BIT(31))
|
||||
#define RTC_I2C_DONE_V 0x1
|
||||
#define RTC_I2C_DONE_S 31
|
||||
/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
|
||||
/*description: data sent by slave*/
|
||||
#define RTC_I2C_SLAVE_TX_DATA 0x000000FF
|
||||
#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
|
||||
#define RTC_I2C_SLAVE_TX_DATA_V 0xFF
|
||||
#define RTC_I2C_SLAVE_TX_DATA_S 8
|
||||
/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: data received*/
|
||||
#define RTC_I2C_RDATA 0x000000FF
|
||||
#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
|
||||
#define RTC_I2C_RDATA_V 0xFF
|
||||
#define RTC_I2C_RDATA_S 0
|
||||
|
||||
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038)
|
||||
/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command0_done*/
|
||||
#define RTC_I2C_COMMAND0_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND0_DONE_S 31
|
||||
/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
|
||||
/*description: command0*/
|
||||
#define RTC_I2C_COMMAND0 0x00003FFF
|
||||
#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
|
||||
#define RTC_I2C_COMMAND0_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND0_S 0
|
||||
|
||||
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c)
|
||||
/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command1_done*/
|
||||
#define RTC_I2C_COMMAND1_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND1_DONE_S 31
|
||||
/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command1*/
|
||||
#define RTC_I2C_COMMAND1 0x00003FFF
|
||||
#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
|
||||
#define RTC_I2C_COMMAND1_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND1_S 0
|
||||
|
||||
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040)
|
||||
/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command2_done*/
|
||||
#define RTC_I2C_COMMAND2_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND2_DONE_S 31
|
||||
/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
|
||||
/*description: command2*/
|
||||
#define RTC_I2C_COMMAND2 0x00003FFF
|
||||
#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
|
||||
#define RTC_I2C_COMMAND2_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND2_S 0
|
||||
|
||||
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044)
|
||||
/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command3_done*/
|
||||
#define RTC_I2C_COMMAND3_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND3_DONE_S 31
|
||||
/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
|
||||
/*description: command3*/
|
||||
#define RTC_I2C_COMMAND3 0x00003FFF
|
||||
#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
|
||||
#define RTC_I2C_COMMAND3_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND3_S 0
|
||||
|
||||
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048)
|
||||
/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command4_done*/
|
||||
#define RTC_I2C_COMMAND4_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND4_DONE_S 31
|
||||
/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
|
||||
/*description: command4*/
|
||||
#define RTC_I2C_COMMAND4 0x00003FFF
|
||||
#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
|
||||
#define RTC_I2C_COMMAND4_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND4_S 0
|
||||
|
||||
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c)
|
||||
/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command5_done*/
|
||||
#define RTC_I2C_COMMAND5_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND5_DONE_S 31
|
||||
/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
|
||||
/*description: command5*/
|
||||
#define RTC_I2C_COMMAND5 0x00003FFF
|
||||
#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
|
||||
#define RTC_I2C_COMMAND5_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND5_S 0
|
||||
|
||||
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050)
|
||||
/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command6_done*/
|
||||
#define RTC_I2C_COMMAND6_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND6_DONE_S 31
|
||||
/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command6*/
|
||||
#define RTC_I2C_COMMAND6 0x00003FFF
|
||||
#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
|
||||
#define RTC_I2C_COMMAND6_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND6_S 0
|
||||
|
||||
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054)
|
||||
/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command7_done*/
|
||||
#define RTC_I2C_COMMAND7_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND7_DONE_S 31
|
||||
/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
|
||||
/*description: command7*/
|
||||
#define RTC_I2C_COMMAND7 0x00003FFF
|
||||
#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
|
||||
#define RTC_I2C_COMMAND7_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND7_S 0
|
||||
|
||||
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058)
|
||||
/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command8_done*/
|
||||
#define RTC_I2C_COMMAND8_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND8_DONE_S 31
|
||||
/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command8*/
|
||||
#define RTC_I2C_COMMAND8 0x00003FFF
|
||||
#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
|
||||
#define RTC_I2C_COMMAND8_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND8_S 0
|
||||
|
||||
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c)
|
||||
/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command9_done*/
|
||||
#define RTC_I2C_COMMAND9_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND9_DONE_S 31
|
||||
/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
|
||||
/*description: command9*/
|
||||
#define RTC_I2C_COMMAND9 0x00003FFF
|
||||
#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
|
||||
#define RTC_I2C_COMMAND9_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND9_S 0
|
||||
|
||||
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060)
|
||||
/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command10_done*/
|
||||
#define RTC_I2C_COMMAND10_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND10_DONE_S 31
|
||||
/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
|
||||
/*description: command10*/
|
||||
#define RTC_I2C_COMMAND10 0x00003FFF
|
||||
#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
|
||||
#define RTC_I2C_COMMAND10_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND10_S 0
|
||||
|
||||
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064)
|
||||
/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command11_done*/
|
||||
#define RTC_I2C_COMMAND11_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND11_DONE_S 31
|
||||
/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
|
||||
/*description: command11*/
|
||||
#define RTC_I2C_COMMAND11 0x00003FFF
|
||||
#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
|
||||
#define RTC_I2C_COMMAND11_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND11_S 0
|
||||
|
||||
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068)
|
||||
/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command12_done*/
|
||||
#define RTC_I2C_COMMAND12_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND12_DONE_S 31
|
||||
/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
|
||||
/*description: command12*/
|
||||
#define RTC_I2C_COMMAND12 0x00003FFF
|
||||
#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
|
||||
#define RTC_I2C_COMMAND12_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND12_S 0
|
||||
|
||||
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c)
|
||||
/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command13_done*/
|
||||
#define RTC_I2C_COMMAND13_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND13_DONE_S 31
|
||||
/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command13*/
|
||||
#define RTC_I2C_COMMAND13 0x00003FFF
|
||||
#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
|
||||
#define RTC_I2C_COMMAND13_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND13_S 0
|
||||
|
||||
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070)
|
||||
/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command14_done*/
|
||||
#define RTC_I2C_COMMAND14_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND14_DONE_S 31
|
||||
/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: command14*/
|
||||
#define RTC_I2C_COMMAND14 0x00003FFF
|
||||
#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
|
||||
#define RTC_I2C_COMMAND14_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND14_S 0
|
||||
|
||||
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074)
|
||||
/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command15_done*/
|
||||
#define RTC_I2C_COMMAND15_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND15_DONE_S 31
|
||||
/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: command15*/
|
||||
#define RTC_I2C_COMMAND15 0x00003FFF
|
||||
#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
|
||||
#define RTC_I2C_COMMAND15_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND15_S 0
|
||||
|
||||
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
|
||||
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
|
||||
/*description: */
|
||||
#define RTC_I2C_DATE 0x0FFFFFFF
|
||||
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
|
||||
#define RTC_I2C_DATE_V 0xFFFFFFF
|
||||
#define RTC_I2C_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_RTC_I2C_REG_H_ */
|
||||
@ -1,219 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_RTC_I2C_STRUCT_H_
|
||||
#define _SOC_RTC_I2C_STRUCT_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct rtc_i2c_dev_s{
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 20; /*time period that scl = 0*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_low;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
|
||||
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
|
||||
uint32_t ms_mode: 1; /*1=master 0=slave*/
|
||||
uint32_t trans_start: 1; /*force start*/
|
||||
uint32_t tx_lsb_first: 1; /*transit lsb first*/
|
||||
uint32_t rx_lsb_first: 1; /*receive lsb first*/
|
||||
uint32_t reserved6: 23;
|
||||
uint32_t i2c_ctrl_clk_gate_en: 1;
|
||||
uint32_t i2c_reset: 1; /*rtc i2c sw reset*/
|
||||
uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ack_rec: 1; /*ack response*/
|
||||
uint32_t slave_rw: 1; /*slave read or write*/
|
||||
uint32_t arb_lost: 1; /*arbitration is lost*/
|
||||
uint32_t bus_busy: 1; /*bus is busy*/
|
||||
uint32_t slave_addressed: 1; /*slave reg sub address*/
|
||||
uint32_t byte_trans: 1; /*One byte transit done*/
|
||||
uint32_t op_cnt: 2; /*which operation is working*/
|
||||
uint32_t reserved8: 8;
|
||||
uint32_t shift: 8; /*shifter content*/
|
||||
uint32_t scl_main_state_last: 3; /*i2c last main status*/
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t scl_state_last: 3; /*scl last status*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time_out: 20; /*time out threshold*/
|
||||
uint32_t reserved20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} timeout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 15; /*slave address*/
|
||||
uint32_t reserved15: 16;
|
||||
uint32_t en_10bit: 1; /*i2c 10bit mode enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 20; /*time period that scl = 1*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_high;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_duty;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_start_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/
|
||||
uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/
|
||||
uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/
|
||||
uint32_t trans_complete: 1; /*clear transit complete interrupt*/
|
||||
uint32_t time_out: 1; /*clear time out interrupt*/
|
||||
uint32_t ack_err: 1; /*clear ack error interrupt*/
|
||||
uint32_t rx_data: 1; /*clear receive data interrupt*/
|
||||
uint32_t tx_data: 1; /*clear transit load data complete interrupt*/
|
||||
uint32_t detect_start: 1; /*clear detect start interrupt*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/
|
||||
uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/
|
||||
uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/
|
||||
uint32_t trans_complete: 1; /*transit complete interrupt raw*/
|
||||
uint32_t time_out: 1; /*time out interrupt raw*/
|
||||
uint32_t ack_err: 1; /*ack error interrupt raw*/
|
||||
uint32_t rx_data: 1; /*receive data interrupt raw*/
|
||||
uint32_t tx_data: 1; /*transit data interrupt raw*/
|
||||
uint32_t detect_start: 1; /*detect start interrupt raw*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/
|
||||
uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/
|
||||
uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/
|
||||
uint32_t trans_complete: 1; /*transit complete interrupt state*/
|
||||
uint32_t time_out: 1; /*time out interrupt state*/
|
||||
uint32_t ack_err: 1; /*ack error interrupt state*/
|
||||
uint32_t rx_data: 1; /*receive data interrupt state*/
|
||||
uint32_t tx_data: 1; /*transit data interrupt state*/
|
||||
uint32_t detect_start: 1; /*detect start interrupt state*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/
|
||||
uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/
|
||||
uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/
|
||||
uint32_t trans_complete: 1; /*enable transit complete interrupt*/
|
||||
uint32_t time_out: 1; /*enable time out interrupt*/
|
||||
uint32_t ack_err: 1; /*enable eack error interrupt*/
|
||||
uint32_t rx_data: 1; /*enable receive data interrupt*/
|
||||
uint32_t tx_data: 1; /*enable transit data interrupt*/
|
||||
uint32_t detect_start: 1; /*enable detect start interrupt*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_rdata: 8; /*data received*/
|
||||
uint32_t slave_tx_data: 8; /*data sent by slave*/
|
||||
uint32_t reserved16: 15;
|
||||
uint32_t i2c_done: 1; /*i2c done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_data;
|
||||
union {
|
||||
struct {
|
||||
uint32_t command0: 14; /*command0*/
|
||||
uint32_t reserved14: 17;
|
||||
uint32_t done: 1; /*command0_done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} command[16];
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_i2c_dev_t;
|
||||
extern rtc_i2c_dev_t RTC_I2C;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_RTC_I2C_STRUCT_H_ */
|
||||
@ -1,214 +1,290 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_SENSITIVE_REG_H_
|
||||
#define _SOC_SENSITIVE_REG_H_
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0)
|
||||
/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_ROM_TABLE_LOCK_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0)
|
||||
/** SENSITIVE_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_ROM_TABLE_LOCK (BIT(0))
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_M (BIT(0))
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_V 0x1
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_M (SENSITIVE_ROM_TABLE_LOCK_V << SENSITIVE_ROM_TABLE_LOCK_S)
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_V 0x00000001U
|
||||
#define SENSITIVE_ROM_TABLE_LOCK_S 0
|
||||
|
||||
#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4)
|
||||
/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_ROM_TABLE 0xFFFFFFFF
|
||||
#define SENSITIVE_ROM_TABLE_M ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
|
||||
#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFF
|
||||
/** SENSITIVE_ROM_TABLE_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4)
|
||||
/** SENSITIVE_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_ROM_TABLE 0xFFFFFFFFU
|
||||
#define SENSITIVE_ROM_TABLE_M (SENSITIVE_ROM_TABLE_V << SENSITIVE_ROM_TABLE_S)
|
||||
#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFFU
|
||||
#define SENSITIVE_ROM_TABLE_S 0
|
||||
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8)
|
||||
/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8)
|
||||
/** SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0))
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0))
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V << SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S)
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x00000001U
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0
|
||||
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xC)
|
||||
/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xc)
|
||||
/** SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0))
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0))
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V << SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S)
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x00000001U
|
||||
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0
|
||||
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10)
|
||||
/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_0_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10)
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0))
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0))
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S)
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x00000001U
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0
|
||||
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14)
|
||||
/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: 3'b111 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x7
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1
|
||||
/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_1_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14)
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0))
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (BIT(0))
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x1
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S)
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x00000001U
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W; bitpos: [3:1]; default: 7;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007U
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S)
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x00000007U
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1
|
||||
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x18)
|
||||
/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3))
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (BIT(3))
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x1
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3
|
||||
/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x7
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_3_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x18)
|
||||
/** SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W; bitpos: [2:0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007U
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M (SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S)
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x00000007U
|
||||
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0
|
||||
/** SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W; bitpos: [3]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3))
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V << SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S)
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x00000001U
|
||||
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3
|
||||
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x1C)
|
||||
/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_CACHE_TAG_ACCESS_0_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x1c)
|
||||
/** SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0))
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0))
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (SENSITIVE_CACHE_TAG_ACCESS_LOCK_V << SENSITIVE_CACHE_TAG_ACCESS_LOCK_S)
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x00000001U
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0
|
||||
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x20)
|
||||
/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3))
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3))
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3
|
||||
/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2))
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2))
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2
|
||||
/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1))
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1))
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1
|
||||
/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_CACHE_TAG_ACCESS_1_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x20)
|
||||
/** SENSITIVE_PRO_I_TAG_RD_ACS : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0))
|
||||
#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0))
|
||||
#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1
|
||||
#define SENSITIVE_PRO_I_TAG_RD_ACS_M (SENSITIVE_PRO_I_TAG_RD_ACS_V << SENSITIVE_PRO_I_TAG_RD_ACS_S)
|
||||
#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x00000001U
|
||||
#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0
|
||||
/** SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1))
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS_M (SENSITIVE_PRO_I_TAG_WR_ACS_V << SENSITIVE_PRO_I_TAG_WR_ACS_S)
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x00000001U
|
||||
#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1
|
||||
/** SENSITIVE_PRO_D_TAG_RD_ACS : R/W; bitpos: [2]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2))
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS_M (SENSITIVE_PRO_D_TAG_RD_ACS_V << SENSITIVE_PRO_D_TAG_RD_ACS_S)
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x00000001U
|
||||
#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2
|
||||
/** SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3))
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS_M (SENSITIVE_PRO_D_TAG_WR_ACS_V << SENSITIVE_PRO_D_TAG_WR_ACS_S)
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x00000001U
|
||||
#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3
|
||||
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x24)
|
||||
/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_CACHE_MMU_ACCESS_0_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x24)
|
||||
/** SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0))
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0))
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (SENSITIVE_CACHE_MMU_ACCESS_LOCK_V << SENSITIVE_CACHE_MMU_ACCESS_LOCK_S)
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x00000001U
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0
|
||||
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x28)
|
||||
/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1))
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1))
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS_S 1
|
||||
/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_CACHE_MMU_ACCESS_1_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x28)
|
||||
/** SENSITIVE_PRO_MMU_RD_ACS : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0))
|
||||
#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0))
|
||||
#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1
|
||||
#define SENSITIVE_PRO_MMU_RD_ACS_M (SENSITIVE_PRO_MMU_RD_ACS_V << SENSITIVE_PRO_MMU_RD_ACS_S)
|
||||
#define SENSITIVE_PRO_MMU_RD_ACS_V 0x00000001U
|
||||
#define SENSITIVE_PRO_MMU_RD_ACS_S 0
|
||||
/** SENSITIVE_PRO_MMU_WR_ACS : R/W; bitpos: [1]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1))
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS_M (SENSITIVE_PRO_MMU_WR_ACS_V << SENSITIVE_PRO_MMU_WR_ACS_S)
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS_V 0x00000001U
|
||||
#define SENSITIVE_PRO_MMU_WR_ACS_S 1
|
||||
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x2C)
|
||||
/* SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_0_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x2c)
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK (BIT(0))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M (BIT(0))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V 0x1
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M (SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V << SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S)
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V 0x00000001U
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S 0
|
||||
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x30)
|
||||
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN (BIT(1))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V 0x1
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S 1
|
||||
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_1_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x30)
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S)
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V 0x00000001U
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S 0
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN (BIT(1))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S)
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V 0x00000001U
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S 1
|
||||
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x34)
|
||||
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1
|
||||
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_2_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x34)
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S)
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V 0x00000001U
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S 0
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; bitpos: [2:1];
|
||||
* default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003U
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x00000003U
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1
|
||||
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x38)
|
||||
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_3_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x38)
|
||||
/** SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0];
|
||||
* default: 0;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFFU
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M (SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFFU
|
||||
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0
|
||||
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_REG (DR_REG_SENSITIVE_BASE + 0x3C)
|
||||
/* SENSITIVE_XTS_AES_KEY_UPDATE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to update xts_aes key.*/
|
||||
/** SENSITIVE_XTS_AES_KEY_UPDATE_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_REG (DR_REG_SENSITIVE_BASE + 0x3c)
|
||||
/** SENSITIVE_XTS_AES_KEY_UPDATE : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to update xts_aes key
|
||||
*/
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE (BIT(0))
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_M (BIT(0))
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_V 0x1
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_M (SENSITIVE_XTS_AES_KEY_UPDATE_V << SENSITIVE_XTS_AES_KEY_UPDATE_S)
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_V 0x00000001U
|
||||
#define SENSITIVE_XTS_AES_KEY_UPDATE_S 0
|
||||
|
||||
#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x40)
|
||||
/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Need add description.*/
|
||||
/** SENSITIVE_CLOCK_GATE_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x40)
|
||||
/** SENSITIVE_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_CLK_EN (BIT(0))
|
||||
#define SENSITIVE_CLK_EN_M (BIT(0))
|
||||
#define SENSITIVE_CLK_EN_V 0x1
|
||||
#define SENSITIVE_CLK_EN_M (SENSITIVE_CLK_EN_V << SENSITIVE_CLK_EN_S)
|
||||
#define SENSITIVE_CLK_EN_V 0x00000001U
|
||||
#define SENSITIVE_CLK_EN_S 0
|
||||
|
||||
#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC)
|
||||
/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106301 ; */
|
||||
/*description: Need add description.*/
|
||||
#define SENSITIVE_DATE 0x0FFFFFFF
|
||||
#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
|
||||
#define SENSITIVE_DATE_V 0xFFFFFFF
|
||||
#define SENSITIVE_DATE_S 0
|
||||
|
||||
/** SENSITIVE_SENSITIVE_REG_DATE_REG register
|
||||
* register description
|
||||
*/
|
||||
#define SENSITIVE_SENSITIVE_REG_DATE_REG (DR_REG_SENSITIVE_BASE + 0xffc)
|
||||
/** SENSITIVE_SENSITIVE_REG_DATE : R/W; bitpos: [27:0]; default: 34628353;
|
||||
* Need add description
|
||||
*/
|
||||
#define SENSITIVE_SENSITIVE_REG_DATE 0x0FFFFFFFU
|
||||
#define SENSITIVE_SENSITIVE_REG_DATE_M (SENSITIVE_SENSITIVE_REG_DATE_V << SENSITIVE_SENSITIVE_REG_DATE_S)
|
||||
#define SENSITIVE_SENSITIVE_REG_DATE_V 0x0FFFFFFFU
|
||||
#define SENSITIVE_SENSITIVE_REG_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SENSITIVE_REG_H_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -12,8 +12,6 @@
|
||||
#include "esp_bit_defs.h"
|
||||
#endif
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
#define DR_REG_SYSTEM_BASE 0x600c0000
|
||||
#define DR_REG_SENSITIVE_BASE 0x600c1000
|
||||
|
||||
@ -110,9 +110,6 @@
|
||||
#define SOC_I2C_SUPPORT_XTAL (1)
|
||||
#define SOC_I2C_SUPPORT_RTC (1)
|
||||
|
||||
/*-------------------------- I2S CAPS ----------------------------------------*/
|
||||
// TODO IDF-3896
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
#define SOC_LEDC_CHANNEL_NUM (6)
|
||||
@ -125,18 +122,6 @@
|
||||
#define SOC_MPU_REGION_RO_SUPPORTED 0
|
||||
#define SOC_MPU_REGION_WO_SUPPORTED 0
|
||||
|
||||
/*--------------------------- RMT CAPS ---------------------------------------*/
|
||||
#define SOC_RMT_GROUPS (1U) /*!< One RMT group */
|
||||
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
|
||||
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
|
||||
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
|
||||
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
|
||||
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
|
||||
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
|
||||
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
|
||||
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
|
||||
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
|
||||
|
||||
/*-------------------------- RTC CAPS --------------------------------------*/
|
||||
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
|
||||
#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
|
||||
@ -222,9 +207,6 @@
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_NUM (0U) /*! No touch sensors on ESP8684 */
|
||||
|
||||
/*-------------------------- TWAI CAPS ---------------------------------------*/
|
||||
// TODO IDF-3897
|
||||
|
||||
/*-------------------------- Flash Encryption CAPS----------------------------*/
|
||||
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
|
||||
|
||||
|
||||
@ -7,10 +7,10 @@
|
||||
#define _SOC_SPI_MEM_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
|
||||
/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,10 +1,8 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_SYSTIMER_REG_H_
|
||||
#define _SOC_SYSTIMER_REG_H_
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
@ -13,403 +11,548 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
|
||||
/* SYSTIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: register file clk gating.*/
|
||||
#define SYSTIMER_CLK_EN (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_M (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_V 0x1
|
||||
#define SYSTIMER_CLK_EN_S 31
|
||||
/* SYSTIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
|
||||
/*description: timer unit0 work enable.*/
|
||||
#define SYSTIMER_UNIT0_WORK_EN (BIT(30))
|
||||
#define SYSTIMER_UNIT0_WORK_EN_M (BIT(30))
|
||||
#define SYSTIMER_UNIT0_WORK_EN_V 0x1
|
||||
#define SYSTIMER_UNIT0_WORK_EN_S 30
|
||||
/* SYSTIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: timer unit1 work enable.*/
|
||||
#define SYSTIMER_UNIT1_WORK_EN (BIT(29))
|
||||
#define SYSTIMER_UNIT1_WORK_EN_M (BIT(29))
|
||||
#define SYSTIMER_UNIT1_WORK_EN_V 0x1
|
||||
#define SYSTIMER_UNIT1_WORK_EN_S 29
|
||||
/* SYSTIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: If timer unit0 is stalled when core0 stalled.*/
|
||||
#define SYSTIMER_UNIT0_CORE0_STALL_EN (BIT(28))
|
||||
#define SYSTIMER_UNIT0_CORE0_STALL_EN_M (BIT(28))
|
||||
#define SYSTIMER_UNIT0_CORE0_STALL_EN_V 0x1
|
||||
#define SYSTIMER_UNIT0_CORE0_STALL_EN_S 28
|
||||
/* SYSTIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: If timer unit0 is stalled when core1 stalled.*/
|
||||
#define SYSTIMER_UNIT0_CORE1_STALL_EN (BIT(27))
|
||||
#define SYSTIMER_UNIT0_CORE1_STALL_EN_M (BIT(27))
|
||||
#define SYSTIMER_UNIT0_CORE1_STALL_EN_V 0x1
|
||||
#define SYSTIMER_UNIT0_CORE1_STALL_EN_S 27
|
||||
/* SYSTIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
|
||||
/*description: If timer unit1 is stalled when core0 stalled.*/
|
||||
#define SYSTIMER_UNIT1_CORE0_STALL_EN (BIT(26))
|
||||
#define SYSTIMER_UNIT1_CORE0_STALL_EN_M (BIT(26))
|
||||
#define SYSTIMER_UNIT1_CORE0_STALL_EN_V 0x1
|
||||
#define SYSTIMER_UNIT1_CORE0_STALL_EN_S 26
|
||||
/* SYSTIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
|
||||
/*description: If timer unit1 is stalled when core1 stalled.*/
|
||||
#define SYSTIMER_UNIT1_CORE1_STALL_EN (BIT(25))
|
||||
#define SYSTIMER_UNIT1_CORE1_STALL_EN_M (BIT(25))
|
||||
#define SYSTIMER_UNIT1_CORE1_STALL_EN_V 0x1
|
||||
#define SYSTIMER_UNIT1_CORE1_STALL_EN_S 25
|
||||
/* SYSTIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
|
||||
/*description: target0 work enable.*/
|
||||
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_M (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_V 0x1
|
||||
#define SYSTIMER_TARGET0_WORK_EN_S 24
|
||||
/* SYSTIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
|
||||
/*description: target1 work enable.*/
|
||||
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_M (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_V 0x1
|
||||
#define SYSTIMER_TARGET1_WORK_EN_S 23
|
||||
/* SYSTIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
|
||||
/*description: target2 work enable.*/
|
||||
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_M (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_V 0x1
|
||||
#define SYSTIMER_TARGET2_WORK_EN_S 22
|
||||
/* SYSTIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: systimer clock force on.*/
|
||||
/** SYSTIMER_CONF_REG register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
|
||||
/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_M (BIT(0))
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x1
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
|
||||
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_WORK_EN_S 22
|
||||
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_WORK_EN_S 23
|
||||
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_WORK_EN_S 24
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
|
||||
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
|
||||
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
#define SYSTIMER_CLK_EN (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
|
||||
#define SYSTIMER_CLK_EN_V 0x00000001U
|
||||
#define SYSTIMER_CLK_EN_S 31
|
||||
|
||||
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
|
||||
/* SYSTIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: update timer_unit0.*/
|
||||
#define SYSTIMER_UNIT0_UPDATE (BIT(30))
|
||||
#define SYSTIMER_UNIT0_UPDATE_M (BIT(30))
|
||||
#define SYSTIMER_UNIT0_UPDATE_V 0x1
|
||||
#define SYSTIMER_UNIT0_UPDATE_S 30
|
||||
/* SYSTIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: timer value is sync and valid.*/
|
||||
#define SYSTIMER_UNIT0_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_UNIT0_VALUE_VALID_M (BIT(29))
|
||||
#define SYSTIMER_UNIT0_VALUE_VALID_V 0x1
|
||||
#define SYSTIMER_UNIT0_VALUE_VALID_S 29
|
||||
/** SYSTIMER_UNIT0_OP_REG register
|
||||
* system timer unit0 value update register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
|
||||
|
||||
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
|
||||
/* SYSTIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: update timer unit1.*/
|
||||
#define SYSTIMER_UNIT1_UPDATE (BIT(30))
|
||||
#define SYSTIMER_UNIT1_UPDATE_M (BIT(30))
|
||||
#define SYSTIMER_UNIT1_UPDATE_V 0x1
|
||||
#define SYSTIMER_UNIT1_UPDATE_S 30
|
||||
/* SYSTIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: timer value is sync and valid.*/
|
||||
#define SYSTIMER_UNIT1_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_UNIT1_VALUE_VALID_M (BIT(29))
|
||||
#define SYSTIMER_UNIT1_VALUE_VALID_V 0x1
|
||||
#define SYSTIMER_UNIT1_VALUE_VALID_S 29
|
||||
/** SYSTIMER_UNIT1_OP_REG register
|
||||
* system timer unit1 value update register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer unit1
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
|
||||
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xC)
|
||||
/* SYSTIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer unit0 load high 20 bits.*/
|
||||
#define SYSTIMER_UNIT0_LOAD_HI 0x000FFFFF
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_M ((SYSTIMER_UNIT0_LOAD_HI_V)<<(SYSTIMER_UNIT0_LOAD_HI_S))
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_V 0xFFFFF
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_S 0
|
||||
/** SYSTIMER_UNIT0_LOAD_HI_REG register
|
||||
* system timer unit0 value high load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit0 load high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
|
||||
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
|
||||
/* SYSTIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer unit0 load low 32 bits.*/
|
||||
#define SYSTIMER_UNIT0_LOAD_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_M ((SYSTIMER_UNIT0_LOAD_LO_V)<<(SYSTIMER_UNIT0_LOAD_LO_S))
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_S 0
|
||||
/** SYSTIMER_UNIT0_LOAD_LO_REG register
|
||||
* system timer unit0 value low load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit0 load low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
|
||||
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
|
||||
/* SYSTIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer unit1 load high 20 bits.*/
|
||||
#define SYSTIMER_UNIT1_LOAD_HI 0x000FFFFF
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_M ((SYSTIMER_UNIT1_LOAD_HI_V)<<(SYSTIMER_UNIT1_LOAD_HI_S))
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_V 0xFFFFF
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_S 0
|
||||
/** SYSTIMER_UNIT1_LOAD_HI_REG register
|
||||
* system timer unit1 value high load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit1 load high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
|
||||
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
|
||||
/* SYSTIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer unit1 load low 32 bits.*/
|
||||
#define SYSTIMER_UNIT1_LOAD_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_M ((SYSTIMER_UNIT1_LOAD_LO_V)<<(SYSTIMER_UNIT1_LOAD_LO_S))
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_S 0
|
||||
/** SYSTIMER_UNIT1_LOAD_LO_REG register
|
||||
* system timer unit1 value low load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit1 load low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
|
||||
|
||||
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1C)
|
||||
/* SYSTIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer taget0 high 20 bits.*/
|
||||
#define SYSTIMER_TARGET0_HI 0x000FFFFF
|
||||
#define SYSTIMER_TARGET0_HI_M ((SYSTIMER_TARGET0_HI_V)<<(SYSTIMER_TARGET0_HI_S))
|
||||
#define SYSTIMER_TARGET0_HI_V 0xFFFFF
|
||||
#define SYSTIMER_TARGET0_HI_S 0
|
||||
/** SYSTIMER_TARGET0_HI_REG register
|
||||
* system timer comp0 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
|
||||
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget0 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_S 0
|
||||
|
||||
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
|
||||
/* SYSTIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer taget0 low 32 bits.*/
|
||||
#define SYSTIMER_TARGET0_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET0_LO_M ((SYSTIMER_TARGET0_LO_V)<<(SYSTIMER_TARGET0_LO_S))
|
||||
#define SYSTIMER_TARGET0_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET0_LO_S 0
|
||||
/** SYSTIMER_TARGET0_LO_REG register
|
||||
* system timer comp0 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
|
||||
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget0 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_S 0
|
||||
|
||||
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
|
||||
/* SYSTIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer taget1 high 20 bits.*/
|
||||
#define SYSTIMER_TARGET1_HI 0x000FFFFF
|
||||
#define SYSTIMER_TARGET1_HI_M ((SYSTIMER_TARGET1_HI_V)<<(SYSTIMER_TARGET1_HI_S))
|
||||
#define SYSTIMER_TARGET1_HI_V 0xFFFFF
|
||||
#define SYSTIMER_TARGET1_HI_S 0
|
||||
/** SYSTIMER_TARGET1_HI_REG register
|
||||
* system timer comp1 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
|
||||
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget1 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_S 0
|
||||
|
||||
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
|
||||
/* SYSTIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer taget1 low 32 bits.*/
|
||||
#define SYSTIMER_TARGET1_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET1_LO_M ((SYSTIMER_TARGET1_LO_V)<<(SYSTIMER_TARGET1_LO_S))
|
||||
#define SYSTIMER_TARGET1_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET1_LO_S 0
|
||||
/** SYSTIMER_TARGET1_LO_REG register
|
||||
* system timer comp1 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
|
||||
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget1 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_S 0
|
||||
|
||||
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2C)
|
||||
/* SYSTIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer taget2 high 20 bits.*/
|
||||
#define SYSTIMER_TARGET2_HI 0x000FFFFF
|
||||
#define SYSTIMER_TARGET2_HI_M ((SYSTIMER_TARGET2_HI_V)<<(SYSTIMER_TARGET2_HI_S))
|
||||
#define SYSTIMER_TARGET2_HI_V 0xFFFFF
|
||||
#define SYSTIMER_TARGET2_HI_S 0
|
||||
/** SYSTIMER_TARGET2_HI_REG register
|
||||
* system timer comp2 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
|
||||
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget2 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_S 0
|
||||
|
||||
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
|
||||
/* SYSTIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer taget2 low 32 bits.*/
|
||||
#define SYSTIMER_TARGET2_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET2_LO_M ((SYSTIMER_TARGET2_LO_V)<<(SYSTIMER_TARGET2_LO_S))
|
||||
#define SYSTIMER_TARGET2_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET2_LO_S 0
|
||||
/** SYSTIMER_TARGET2_LO_REG register
|
||||
* system timer comp2 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
|
||||
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget2 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_S 0
|
||||
|
||||
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
|
||||
/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: select which unit to compare.*/
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x1
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
|
||||
/* SYSTIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: Set target0 to period mode.*/
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_M (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x1
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
|
||||
/* SYSTIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: target0 period.*/
|
||||
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET0_PERIOD_M ((SYSTIMER_TARGET0_PERIOD_V)<<(SYSTIMER_TARGET0_PERIOD_S))
|
||||
#define SYSTIMER_TARGET0_PERIOD_V 0x3FFFFFF
|
||||
/** SYSTIMER_TARGET0_CONF_REG register
|
||||
* system timer comp0 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
|
||||
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target0 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET0_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target0 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
|
||||
|
||||
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
|
||||
/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: select which unit to compare.*/
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x1
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
|
||||
/* SYSTIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: Set target1 to period mode.*/
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_M (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x1
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
|
||||
/* SYSTIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: target1 period.*/
|
||||
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET1_PERIOD_M ((SYSTIMER_TARGET1_PERIOD_V)<<(SYSTIMER_TARGET1_PERIOD_S))
|
||||
#define SYSTIMER_TARGET1_PERIOD_V 0x3FFFFFF
|
||||
/** SYSTIMER_TARGET1_CONF_REG register
|
||||
* system timer comp1 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
|
||||
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target1 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET1_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target1 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
|
||||
|
||||
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3C)
|
||||
/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: select which unit to compare.*/
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x1
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
|
||||
/* SYSTIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: Set target2 to period mode.*/
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_M (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x1
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
|
||||
/* SYSTIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: target2 period.*/
|
||||
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET2_PERIOD_M ((SYSTIMER_TARGET2_PERIOD_V)<<(SYSTIMER_TARGET2_PERIOD_S))
|
||||
#define SYSTIMER_TARGET2_PERIOD_V 0x3FFFFFF
|
||||
/** SYSTIMER_TARGET2_CONF_REG register
|
||||
* system timer comp2 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
|
||||
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target2 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET2_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target2 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
|
||||
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
|
||||
/* SYSTIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer read value high 20bits.*/
|
||||
#define SYSTIMER_UNIT0_VALUE_HI 0x000FFFFF
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_M ((SYSTIMER_UNIT0_VALUE_HI_V)<<(SYSTIMER_UNIT0_VALUE_HI_S))
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_V 0xFFFFF
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_S 0
|
||||
/** SYSTIMER_UNIT0_VALUE_HI_REG register
|
||||
* system timer unit0 value high register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
|
||||
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
|
||||
/* SYSTIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer read value low 32bits.*/
|
||||
#define SYSTIMER_UNIT0_VALUE_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_M ((SYSTIMER_UNIT0_VALUE_LO_V)<<(SYSTIMER_UNIT0_VALUE_LO_S))
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_S 0
|
||||
/** SYSTIMER_UNIT0_VALUE_LO_REG register
|
||||
* system timer unit0 value low register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
|
||||
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
||||
/* SYSTIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
|
||||
/*description: timer read value high 20bits.*/
|
||||
#define SYSTIMER_UNIT1_VALUE_HI 0x000FFFFF
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_M ((SYSTIMER_UNIT1_VALUE_HI_V)<<(SYSTIMER_UNIT1_VALUE_HI_S))
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_V 0xFFFFF
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_S 0
|
||||
/** SYSTIMER_UNIT1_VALUE_HI_REG register
|
||||
* system timer unit1 value high register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
|
||||
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4C)
|
||||
/* SYSTIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: timer read value low 32bits.*/
|
||||
#define SYSTIMER_UNIT1_VALUE_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_M ((SYSTIMER_UNIT1_VALUE_LO_V)<<(SYSTIMER_UNIT1_VALUE_LO_S))
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_S 0
|
||||
/** SYSTIMER_UNIT1_VALUE_LO_REG register
|
||||
* system timer unit1 value low register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
|
||||
|
||||
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
|
||||
/* SYSTIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: timer comp0 sync enable signal.*/
|
||||
#define SYSTIMER_COMP0_LOAD (BIT(0))
|
||||
#define SYSTIMER_COMP0_LOAD_M (BIT(0))
|
||||
#define SYSTIMER_COMP0_LOAD_V 0x1
|
||||
#define SYSTIMER_COMP0_LOAD_S 0
|
||||
/** SYSTIMER_COMP0_LOAD_REG register
|
||||
* system timer comp0 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
|
||||
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp0 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
|
||||
|
||||
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
|
||||
/* SYSTIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: timer comp1 sync enable signal.*/
|
||||
#define SYSTIMER_COMP1_LOAD (BIT(0))
|
||||
#define SYSTIMER_COMP1_LOAD_M (BIT(0))
|
||||
#define SYSTIMER_COMP1_LOAD_V 0x1
|
||||
#define SYSTIMER_COMP1_LOAD_S 0
|
||||
/** SYSTIMER_COMP1_LOAD_REG register
|
||||
* system timer comp1 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
|
||||
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp1 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
|
||||
|
||||
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
|
||||
/* SYSTIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: timer comp2 sync enable signal.*/
|
||||
#define SYSTIMER_COMP2_LOAD (BIT(0))
|
||||
#define SYSTIMER_COMP2_LOAD_M (BIT(0))
|
||||
#define SYSTIMER_COMP2_LOAD_V 0x1
|
||||
#define SYSTIMER_COMP2_LOAD_S 0
|
||||
/** SYSTIMER_COMP2_LOAD_REG register
|
||||
* system timer comp2 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
|
||||
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp2 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
|
||||
|
||||
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5C)
|
||||
/* SYSTIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: timer unit0 sync enable signal.*/
|
||||
#define SYSTIMER_UNIT0_LOAD (BIT(0))
|
||||
#define SYSTIMER_UNIT0_LOAD_M (BIT(0))
|
||||
#define SYSTIMER_UNIT0_LOAD_V 0x1
|
||||
#define SYSTIMER_UNIT0_LOAD_S 0
|
||||
/** SYSTIMER_UNIT0_LOAD_REG register
|
||||
* system timer unit0 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit0 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
|
||||
|
||||
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
|
||||
/* SYSTIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: timer unit1 sync enable signal.*/
|
||||
#define SYSTIMER_UNIT1_LOAD (BIT(0))
|
||||
#define SYSTIMER_UNIT1_LOAD_M (BIT(0))
|
||||
#define SYSTIMER_UNIT1_LOAD_V 0x1
|
||||
#define SYSTIMER_UNIT1_LOAD_S 0
|
||||
/** SYSTIMER_UNIT1_LOAD_REG register
|
||||
* system timer unit1 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit1 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
|
||||
|
||||
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
|
||||
/* SYSTIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: interupt2 enable.*/
|
||||
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_M (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_V 0x1
|
||||
#define SYSTIMER_TARGET2_INT_ENA_S 2
|
||||
/* SYSTIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: interupt1 enable.*/
|
||||
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_M (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_V 0x1
|
||||
#define SYSTIMER_TARGET1_INT_ENA_S 1
|
||||
/* SYSTIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: interupt0 enable.*/
|
||||
/** SYSTIMER_INT_ENA_REG register
|
||||
* systimer interrupt enable register
|
||||
*/
|
||||
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
|
||||
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ENA_M (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ENA_V 0x1
|
||||
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_ENA_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_ENA_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_ENA_S 2
|
||||
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
|
||||
/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: interupt2 raw.*/
|
||||
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_M (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_V 0x1
|
||||
#define SYSTIMER_TARGET2_INT_RAW_S 2
|
||||
/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: interupt1 raw.*/
|
||||
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_M (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_V 0x1
|
||||
#define SYSTIMER_TARGET1_INT_RAW_S 1
|
||||
/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: interupt0 raw.*/
|
||||
/** SYSTIMER_INT_RAW_REG register
|
||||
* systimer interrupt raw register
|
||||
*/
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
|
||||
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_RAW_M (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_RAW_V 0x1
|
||||
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_RAW_S 0
|
||||
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_RAW_S 1
|
||||
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_RAW_S 2
|
||||
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6C)
|
||||
/* SYSTIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: interupt2 clear.*/
|
||||
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_M (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_V 0x1
|
||||
#define SYSTIMER_TARGET2_INT_CLR_S 2
|
||||
/* SYSTIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: interupt1 clear.*/
|
||||
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_M (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_V 0x1
|
||||
#define SYSTIMER_TARGET1_INT_CLR_S 1
|
||||
/* SYSTIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: interupt0 clear.*/
|
||||
/** SYSTIMER_INT_CLR_REG register
|
||||
* systimer interrupt clear register
|
||||
*/
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
|
||||
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_CLR_M (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_CLR_V 0x1
|
||||
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_CLR_S 0
|
||||
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_CLR_S 1
|
||||
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_CLR_S 2
|
||||
|
||||
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
|
||||
/* SYSTIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: interupt2 status.*/
|
||||
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_M (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_V 0x1
|
||||
#define SYSTIMER_TARGET2_INT_ST_S 2
|
||||
/* SYSTIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: interupt1 status.*/
|
||||
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_M (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_V 0x1
|
||||
#define SYSTIMER_TARGET1_INT_ST_S 1
|
||||
/* SYSTIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: interupt0 status.*/
|
||||
/** SYSTIMER_INT_ST_REG register
|
||||
* systimer interrupt status register
|
||||
*/
|
||||
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
|
||||
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* interupt0 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ST_M (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ST_V 0x1
|
||||
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
|
||||
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_ST_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* interupt1 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
|
||||
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_ST_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* interupt2 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
|
||||
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_ST_S 2
|
||||
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xFC)
|
||||
/* SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */
|
||||
/*description: systimer register version.*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFF
|
||||
#define SYSTIMER_DATE_M ((SYSTIMER_DATE_V)<<(SYSTIMER_DATE_S))
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFF
|
||||
/** SYSTIMER_DATE_REG register
|
||||
* system timer version control register
|
||||
*/
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753;
|
||||
* systimer register version
|
||||
*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFFU
|
||||
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -14,8 +14,6 @@ PROVIDE ( RTCIO = 0x60008400 );
|
||||
PROVIDE ( HINF = 0x6000B000 );
|
||||
PROVIDE ( I2C0 = 0x60013000 );
|
||||
PROVIDE ( HOST = 0x60015000 );
|
||||
PROVIDE ( RMT = 0x60016000 );
|
||||
PROVIDE ( RMTMEM = 0x60016400 );
|
||||
PROVIDE ( PCNT = 0x60017000 );
|
||||
PROVIDE ( SLC = 0x60018000 );
|
||||
PROVIDE ( LEDC = 0x60019000 );
|
||||
|
||||
@ -1,35 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/rmt_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
const rmt_signal_conn_t rmt_periph_signals = {
|
||||
.groups = {
|
||||
[0] = {
|
||||
.module = PERIPH_RMT_MODULE,
|
||||
.irq = ETS_RMT_INTR_SOURCE,
|
||||
.channels = {
|
||||
[0] = {
|
||||
.tx_sig = RMT_SIG_OUT0_IDX,
|
||||
.rx_sig = -1
|
||||
},
|
||||
[1] = {
|
||||
.tx_sig = RMT_SIG_OUT1_IDX,
|
||||
.rx_sig = -1
|
||||
},
|
||||
[2] = {
|
||||
.tx_sig = -1,
|
||||
.rx_sig = RMT_SIG_IN0_IDX
|
||||
},
|
||||
[3] = {
|
||||
.tx_sig = -1,
|
||||
.rx_sig = RMT_SIG_IN1_IDX
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
@ -123,22 +123,29 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
|
||||
return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
|
||||
}
|
||||
|
||||
#if SOC_RTC_FAST_MEM_SUPPORTED
|
||||
inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) {
|
||||
#if SOC_RTC_FAST_MEM_SUPPORTED
|
||||
return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH);
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
inline static bool IRAM_ATTR esp_ptr_in_rtc_dram_fast(const void *p) {
|
||||
#if SOC_RTC_FAST_MEM_SUPPORTED
|
||||
return ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
|
||||
}
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP8684
|
||||
// IDF-3901
|
||||
inline static bool IRAM_ATTR esp_ptr_in_rtc_slow(const void *p) {
|
||||
#if SOC_RTC_SLOW_MEM_SUPPORTED
|
||||
return ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
|
||||
}
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* Convert a D/IRAM DRAM pointer to equivalent word address in IRAM
|
||||
|
||||
|
||||
@ -1754,7 +1754,6 @@ components/soc/esp32c3/include/soc/rtc_i2c_reg.h
|
||||
components/soc/esp32c3/include/soc/rtc_i2c_struct.h
|
||||
components/soc/esp32c3/include/soc/sensitive_reg.h
|
||||
components/soc/esp32c3/include/soc/sensitive_struct.h
|
||||
components/soc/esp32c3/include/soc/soc.h
|
||||
components/soc/esp32c3/include/soc/soc_caps.h
|
||||
components/soc/esp32c3/include/soc/soc_pins.h
|
||||
components/soc/esp32c3/include/soc/spi_mem_reg.h
|
||||
|
||||
Loading…
Reference in New Issue
Block a user