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esp32h2: code clean up

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This commit is contained in:
Shu Chen 2021-06-11 16:30:22 +08:00
parent e9a51e410a
commit ee23a489b9
26 changed files with 34 additions and 248 deletions
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5
components/bootloader_support/component.mk
View File

@ -31,12 +31,15 @@ endif
COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \
src/bootloader_flash_config_esp32s3.o \
src/bootloader_flash_config_esp32c3.o \
src/bootloader_flash_config_esp32h2.o \
src/bootloader_efuse_esp32s2.o \
src/bootloader_efuse_esp32s3.o \
src/bootloader_efuse_esp32c3.o \
src/bootloader_efuse_esp32h2.o \
src/bootloader_random_esp32s2.o \
src/bootloader_random_esp32s3.o \
src/bootloader_random_esp32c3.o
src/bootloader_random_esp32c3.o \
src/bootloader_random_esp32h2.o
ifdef IS_BOOTLOADER_BUILD
ifndef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME

4
components/driver/periph_ctrl.c
View File

@ -42,7 +42,7 @@ void periph_module_reset(periph_module_t periph)
portEXIT_CRITICAL_SAFE(&periph_spinlock);
}
#if CONFIG_WIFI_ENABLED
#if CONFIG_ESP32_WIFI_ENABLED
IRAM_ATTR void wifi_bt_common_module_enable(void)
{
portENTER_CRITICAL_SAFE(&periph_spinlock);
@ -72,4 +72,4 @@ void wifi_module_disable(void)
{
periph_ll_wifi_module_disable_clk_set_rst();
}
#endif // CONFIG_WIFI_ENABLED
#endif // CONFIG_ESP32_WIFI_ENABLED

2
components/efuse/include/esp_efuse.h
View File

@ -25,6 +25,8 @@ extern "C" {
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/secure_boot.h"
#endif
#define ESP_ERR_EFUSE 0x1600 /*!< Base error code for efuse api. */

2
components/esp_adc_cal/component.mk
View File

@ -3,4 +3,4 @@
#
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_OBJEXCLUDE += esp_adc_cal_esp32s2.o esp_adc_cal_esp32c3.o
COMPONENT_OBJEXCLUDE += esp_adc_cal_esp32s2.o esp_adc_cal_esp32c3.o esp_adc_cal_esp32h2.o

4
components/esp_hw_support/port/esp32h2/rtc_clk.c
View File

@ -282,11 +282,11 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
*/
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{
int per_conf = DPORT_CPUPERIOD_SEL_80;
// int per_conf = DPORT_CPUPERIOD_SEL_80;
if (cpu_freq_mhz == 80) {
/* nothing to do */
} else if (cpu_freq_mhz == 160) {
per_conf = DPORT_CPUPERIOD_SEL_160;
// per_conf = DPORT_CPUPERIOD_SEL_160;
} else {
SOC_LOGE(TAG, "invalid frequency");
abort();

68
components/esp_hw_support/port/esp32h2/rtc_init.c
View File

@ -27,10 +27,7 @@
#include "esp_efuse.h"
#include "esp_efuse_table.h"
static const char *TAG = "rtc_init";
static void set_ocode_by_efuse(int calib_version);
static void calibrate_ocode(void);
// ESP32H2-TODO: IDF-3396
void rtc_init(rtc_config_t cfg)
{
@ -177,66 +174,3 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
val |= RTC_CNTL_SDIO_PD_EN;
REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
}
static void set_ocode_by_efuse(int calib_version)
{
assert(calib_version == 1);
// use efuse ocode.
uint32_t ocode;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8);
assert(err == ESP_OK);
(void) err;
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
}
static void calibrate_ocode(void)
{
/*
Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
Method:
1. read current cpu config, save in old_config;
2. switch cpu to xtal because PLL will be closed when o-code calibration;
3. begin o-code calibration;
4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
5. set cpu to old-config.
*/
rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
if (slow_clk_freq == (rtc_slow_freq_x32k)) {
cal_clk = RTC_CAL_32K_XTAL;
} else if (slow_clk_freq == rtc_slow_freq_8MD256) {
cal_clk = RTC_CAL_8MD256;
}
uint64_t max_delay_time_us = 10000;
uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
uint64_t cycle0 = rtc_time_get();
uint64_t timeout_cycle = cycle0 + max_delay_cycle;
uint64_t cycle1 = 0;
rtc_cpu_freq_config_t old_config;
rtc_clk_cpu_freq_get_config(&old_config);
rtc_clk_cpu_freq_set_xtal();
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
bool odone_flag = 0;
bool bg_odone_flag = 0;
while (1) {
odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
cycle1 = rtc_time_get();
if (odone_flag && bg_odone_flag) {
break;
}
if (cycle1 >= timeout_cycle) {
SOC_LOGW(TAG, "o_code calibration fail\n");
break;
}
}
rtc_clk_cpu_freq_set_config(&old_config);
}

2
components/esp_phy/lib

@ -1 +1 @@
Subproject commit 5fd56f1692128209056fea699f9d118e88e176f6
Subproject commit 0deb3621c216cc198aecd642d1b7c4b99afe322c

1
components/esp_rom/esp32h2/ld/esp32h2.rom.ld
View File

@ -714,4 +714,3 @@ rom_phy_dig_reg_backup = 0x40000b9c;
chip726_phyrom_version_num = 0x40000ba0;
/* Data (.data, .bss, .rodata) */
phy_param_rom = 0x3fcdffc8;

1
components/esp_rom/esp32h2/ld/esp32h2.rom.libgcc.ld
View File

@ -103,4 +103,3 @@ __umoddi3 = 0x400008c8;
__umodsi3 = 0x400008cc;
__unorddf2 = 0x400008d0;
__unordsf2 = 0x400008d4;

1
components/esp_rom/esp32h2/ld/esp32h2.rom.newlib-nano.ld
View File

@ -25,4 +25,3 @@ fprintf = 0x400004a8;
printf = 0x400004ac;
vfiprintf = 0x400004b0;
vfprintf = 0x400004b4;

1
components/esp_rom/esp32h2/ld/esp32h2.rom.newlib.ld
View File

@ -92,4 +92,3 @@ PROVIDE( __swsetup_r = 0x40000484 );
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffdc;
_global_impure_ptr = 0x3fcdffd8;

2
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -208,7 +208,7 @@ void rtc_clk_select_rtc_slow_clk(void)
*/
__attribute__((weak)) void esp_perip_clk_init(void)
{
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk, hwcrypto_perip_clk = 0;
uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE

4
components/esp_wifi/CMakeLists.txt
View File

@ -1,4 +1,4 @@
if(CONFIG_WIFI_ENABLED)
if(CONFIG_ESP32_WIFI_ENABLED)
idf_build_get_property(idf_target IDF_TARGET)
if(CONFIG_ESP32_NO_BLOBS OR CONFIG_ESP32S2_NO_BLOBS)
@ -35,7 +35,7 @@ idf_component_register(SRCS "${srcs}"
wpa_supplicant hal ${extra_priv_requires}
LDFRAGMENTS "${ldfragments}")
if(CONFIG_WIFI_ENABLED)
if(CONFIG_ESP32_WIFI_ENABLED)
idf_build_get_property(build_dir BUILD_DIR)
set(target_name "${idf_target}")

31
components/esp_wifi/Kconfig
View File

@ -2,15 +2,13 @@
menu "Wi-Fi"
visible if !IDF_TARGET_ESP32H2
config WIFI_ENABLED
bool "Wi-Fi"
default "y" if !IDF_TARGET_ESP32H2
help
Select this option to enable Wi-Fi and show the submenu with Wi-Fi configuration choices.
config ESP32_WIFI_ENABLED
bool
default "y" if !IDF_TARGET_ESP32H2 # TODO: replace with SOC_CAPS_SUPPORT_WIFI after IDF-2223 is done
config ESP32_WIFI_SW_COEXIST_ENABLE
bool "Software controls WiFi/Bluetooth coexistence"
depends on WIFI_ENABLED && BT_ENABLED
depends on BT_ENABLED
default y
help
If enabled, WiFi & Bluetooth coexistence is controlled by software rather than hardware.
@ -21,7 +19,6 @@ menu "Wi-Fi"
config ESP32_WIFI_STATIC_RX_BUFFER_NUM
int "Max number of WiFi static RX buffers"
depends on WIFI_ENABLED
range 2 25
default 10 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
@ -37,7 +34,6 @@ menu "Wi-Fi"
config ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM
int "Max number of WiFi dynamic RX buffers"
depends on WIFI_ENABLED
range 0 128 if !LWIP_WND_SCALE
range 0 1024 if LWIP_WND_SCALE
default 32
@ -57,7 +53,6 @@ menu "Wi-Fi"
choice ESP32_WIFI_TX_BUFFER
prompt "Type of WiFi TX buffers"
depends on WIFI_ENABLED
default ESP32_WIFI_DYNAMIC_TX_BUFFER
help
Select type of WiFi TX buffers:
@ -82,13 +77,11 @@ menu "Wi-Fi"
config ESP32_WIFI_TX_BUFFER_TYPE
int
depends on WIFI_ENABLED
default 0 if ESP32_WIFI_STATIC_TX_BUFFER
default 1 if ESP32_WIFI_DYNAMIC_TX_BUFFER
config ESP32_WIFI_STATIC_TX_BUFFER_NUM
int "Max number of WiFi static TX buffers"
depends on WIFI_ENABLED
depends on ESP32_WIFI_STATIC_TX_BUFFER
range 1 64
default 16
@ -104,7 +97,6 @@ menu "Wi-Fi"
config ESP32_WIFI_CACHE_TX_BUFFER_NUM
int "Max number of WiFi cache TX buffers"
depends on WIFI_ENABLED
depends on (ESP32_SPIRAM_SUPPORT || ESP32S2_SPIRAM_SUPPORT || ESP32S3_SPIRAM_SUPPORT)
range 16 128
default 32
@ -118,7 +110,6 @@ menu "Wi-Fi"
config ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM
int "Max number of WiFi dynamic TX buffers"
depends on WIFI_ENABLED
depends on ESP32_WIFI_DYNAMIC_TX_BUFFER
range 1 128
default 32
@ -133,7 +124,6 @@ menu "Wi-Fi"
config ESP32_WIFI_CSI_ENABLED
bool "WiFi CSI(Channel State Information)"
depends on WIFI_ENABLED
default n
help
Select this option to enable CSI(Channel State Information) feature. CSI takes about
@ -142,7 +132,6 @@ menu "Wi-Fi"
config ESP32_WIFI_AMPDU_TX_ENABLED
bool "WiFi AMPDU TX"
depends on WIFI_ENABLED
default y
help
Select this option to enable AMPDU TX feature
@ -161,7 +150,6 @@ menu "Wi-Fi"
config ESP32_WIFI_AMPDU_RX_ENABLED
bool "WiFi AMPDU RX"
depends on WIFI_ENABLED
default y
help
Select this option to enable AMPDU RX feature
@ -182,7 +170,6 @@ menu "Wi-Fi"
config ESP32_WIFI_AMSDU_TX_ENABLED
bool "WiFi AMSDU TX"
depends on WIFI_ENABLED
depends on (ESP32_SPIRAM_SUPPORT || ESP32S2_SPIRAM_SUPPORT || ESP32S3_SPIRAM_SUPPORT)
default n
help
@ -190,13 +177,11 @@ menu "Wi-Fi"
config ESP32_WIFI_NVS_ENABLED
bool "WiFi NVS flash"
depends on WIFI_ENABLED
default y
help
Select this option to enable WiFi NVS flash
choice ESP32_WIFI_TASK_CORE_ID
depends on WIFI_ENABLED
depends on !FREERTOS_UNICORE
prompt "WiFi Task Core ID"
default ESP32_WIFI_TASK_PINNED_TO_CORE_0
@ -211,7 +196,6 @@ menu "Wi-Fi"
config ESP32_WIFI_SOFTAP_BEACON_MAX_LEN
int "Max length of WiFi SoftAP Beacon"
depends on WIFI_ENABLED
range 752 1256
default 752
help
@ -234,7 +218,6 @@ menu "Wi-Fi"
config ESP32_WIFI_MGMT_SBUF_NUM
int "WiFi mgmt short buffer number"
depends on WIFI_ENABLED
range 6 32
default 32
help
@ -242,7 +225,6 @@ menu "Wi-Fi"
config ESP32_WIFI_IRAM_OPT
bool "WiFi IRAM speed optimization"
depends on WIFI_ENABLED
default n if (BT_ENABLED && ESP32_SPIRAM_SUPPORT)
default y
help
@ -252,7 +234,6 @@ menu "Wi-Fi"
config ESP32_WIFI_RX_IRAM_OPT
bool "WiFi RX IRAM speed optimization"
depends on WIFI_ENABLED
default n if (BT_ENABLED && ESP32_SPIRAM_SUPPORT)
default y
help
@ -262,7 +243,6 @@ menu "Wi-Fi"
config ESP32_WIFI_ENABLE_WPA3_SAE
bool "Enable WPA3-Personal"
depends on WIFI_ENABLED
default y
depends on WPA_MBEDTLS_CRYPTO
help
@ -272,7 +252,6 @@ menu "Wi-Fi"
config ESP_WIFI_SLP_IRAM_OPT
bool "WiFi SLP IRAM speed optimization"
depends on WIFI_ENABLED
select PM_SLP_DEFAULT_PARAMS_OPT
help
Select this option to place called Wi-Fi library TBTT process and receive beacon functions in IRAM.
@ -300,7 +279,6 @@ menu "Wi-Fi"
config ESP_WIFI_FTM_ENABLE
bool "WiFi FTM"
depends on WIFI_ENABLED
default n
depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3)
help
@ -318,7 +296,6 @@ menu "Wi-Fi"
config ESP_WIFI_STA_DISCONNECTED_PM_ENABLE
bool "Power Management for station at disconnected"
depends on WIFI_ENABLED
help
Select this option to enable power_management for station when disconnected.
Chip will do modem-sleep when rf module is not in use any more.

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit 46ead46242c57a0b0b137976dc55550225faefec
Subproject commit 3f6ff86ba5711b8eb4283d326f52d420959d530e

3
components/freertos/CMakeLists.txt
View File

@ -6,7 +6,8 @@ endif()
idf_build_get_property(target IDF_TARGET)
if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2") # should test arch here not target, TODO ESP32-C3 IDF-1754
# should test arch here not target, TODO ESP32-C3 IDF-1754
if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2")
set(srcs
"port/xtensa/port.c"
"port/xtensa/portasm.S"

6
components/hal/esp32h2/include/hal/adc_ll.h
View File

@ -444,7 +444,7 @@ static inline void adc_ll_digi_reset(void)
static inline void adc_ll_pwdet_set_cct(uint32_t cct)
{
/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
// RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; // ESP32H2-TODO
// RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; // ESP32H2-TODO: IDF-3389
}
/**
@ -457,7 +457,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
{
/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
// return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
return 0; // ESP32H2-TODO
return 0; // ESP32H2-TODO: IDF-3389
}
/**
@ -685,7 +685,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
*/
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
{
// ESP32H2-TODO
// ESP32H2-TODO: IDF-3389
}
/*---------------------------------------------------------------

2
components/riscv/CMakeLists.txt
View File

@ -1,6 +1,6 @@
idf_build_get_property(target IDF_TARGET)
if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2" )
if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2")
return()
endif()

20
components/soc/esp32h2/gpio_periph.c
View File

@ -14,6 +14,7 @@
#include "soc/gpio_periph.h"
// ESP32H2-TODO: IDF-3439
const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
@ -37,25 +38,6 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
IO_MUX_GPIO24_REG,
IO_MUX_GPIO25_REG,
IO_MUX_GPIO26_REG,
IO_MUX_GPIO27_REG,
IO_MUX_GPIO28_REG,
IO_MUX_GPIO29_REG,
IO_MUX_GPIO30_REG,
IO_MUX_GPIO31_REG,
IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG,
IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG,
IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG,
IO_MUX_GPIO38_REG,
IO_MUX_GPIO39_REG,
IO_MUX_GPIO40_REG,
};
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {

7
components/soc/esp32h2/include/soc/clkrst_reg.h
View File

@ -63,7 +63,7 @@ extern "C" {
#define SYSTEM_PRE_DIV_CNT_M SYSTEM_CPU_DIV_NUM_M
#define SYSTEM_PRE_DIV_CNT_V SYSTEM_CPU_DIV_NUM_V
#define SYSTEM_PRE_DIV_CNT_S SYSTEM_CPU_DIV_NUM_S
#define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0008)
/* SYSTEM_AHB_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: */
@ -1048,9 +1048,4 @@ extern "C" {
}
#endif
#endif /*_SOC_CLKRST_REG_H_ */

102
components/soc/esp32h2/include/soc/io_mux_reg.h
View File

@ -116,30 +116,6 @@
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_GPIO28_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_GPIO30_U
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_GPIO31_U
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_GPIO40_U
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_GPIO41_U
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_GPIO42_U
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_GPIO43_U
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_GPIO44_U
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
/* Value to set in IO Mux to use a pin as GPIO. */
#define PIN_FUNC_GPIO 1
@ -290,85 +266,9 @@
#define FUNC_U0TXD_GPIO21 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE +0x5c)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE +0x60)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE +0x64)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE +0x68)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE +0x6c)
#define FUNC_GPIO26_GPIO26 1
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE +0x70)
#define FUNC_GPIO27_GPIO27 1
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_GPIO28_U (REG_IO_MUX_BASE +0x74)
#define FUNC_GPIO28_GPIO28 1
#define FUNC_GPIO28_GPIO28_0 0
#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE +0x78)
#define FUNC_GPIO29_GPIO29 1
#define FUNC_GPIO29_GPIO29_0 0
#define PERIPHS_IO_MUX_GPIO30_U (REG_IO_MUX_BASE +0x7c)
#define FUNC_GPIO30_GPIO30 1
#define FUNC_GPIO30_GPIO30_0 0
#define PERIPHS_IO_MUX_GPIO31_U (REG_IO_MUX_BASE +0x80)
#define FUNC_GPIO31_GPIO31 1
#define FUNC_GPIO31_GPIO31_0 0
#define PERIPHS_IO_MUX_GPIO32_U (REG_IO_MUX_BASE +0x84)
#define FUNC_GPIO32_GPIO32 1
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_GPIO39_U (REG_IO_MUX_BASE +0xa0)
#define FUNC_GPIO39_GPIO39 1
#define FUNC_GPIO39_GPIO39_0 0
#define PERIPHS_IO_MUX_GPIO40_U (REG_IO_MUX_BASE +0xa4)
#define FUNC_GPIO40_GPIO40 1
#define FUNC_GPIO40_GPIO40_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x2012310
#define IO_MUX_DATE_VERSION 0x2006050
#endif

2
components/soc/esp32h2/include/soc/rtc.h
View File

@ -73,7 +73,7 @@ extern "C" {
#define RTC_CNTL_DBIAS_1V05 4
#define RTC_CNTL_DBIAS_1V10 5
#define RTC_CNTL_DBIAS_1V15 6
#define RTC_CNTL_DBIAS_1V20 7
#define RTC_CNTL_DBIAS_1V20 7
/* The value of 1V00 can be adjusted between 0~3*/
#define RTC_CNTL_DIG_DBIAS_0V85 0

4
components/soc/esp32h2/include/soc/rtc_cntl_reg.h
View File

@ -3180,8 +3180,4 @@ extern "C" {
}
#endif
#endif /*_SOC_RTC_CNTL_REG_H_ */

2
components/soc/esp32h2/include/soc/spi_reg.h
View File

@ -1450,7 +1450,7 @@ the receive data. 0: Others. .*/
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x0E0)
/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of current seg-trans operation
/*description: 1: Enable the DMA CONF phase of current seg-trans operation
which means seg-trans will start. 0: This is not seg-trans mode.*/
#define SPI_USR_CONF (BIT(28))
#define SPI_USR_CONF_M (BIT(28))

2
components/xtensa/CMakeLists.txt
View File

@ -14,4 +14,4 @@ idf_component_register(SRCS ${srcs}
INCLUDE_DIRS include ${target}/include
LDFRAGMENTS linker.lf)
target_link_libraries(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/${target}/libxt_hal.a")
target_link_libraries(${COMPONENT_LIB} PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}/${target}/libxt_hal.a")

2
tools/idf_size.py
View File

@ -439,7 +439,7 @@ def main():
class StructureForSummary(object):
(dram_data_names, dram_bss_names, dram_other_names,
diram_data_names, diram_bss_names) = (frozenset(), ) * 5
diram_data_names, diram_bss_names) = (frozenset(), ) * 5 # type: ignore
(total_iram, total_dram, total_dram, total_diram,
used_dram_data, used_dram_bss, used_dram_other,