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soc: add reset reasons in soc component

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This commit is contained in:
morris 2021-07-13 10:45:06 +08:00
parent a68fd59b02
commit 1560d6f1ba
47 changed files with 624 additions and 314 deletions
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2
components/app_update/test/test_switch_ota.c
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@ -14,10 +14,8 @@
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#endif
#include "freertos/FreeRTOS.h"

3
components/bootloader_support/include/bootloader_common.h
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@ -8,7 +8,8 @@
#include "esp_flash_partitions.h"
#include "esp_image_format.h"
#include "esp_app_format.h"
// RESET_REASON is declared in rom/rtc.h
// [refactor-todo]: we shouldn't expose ROM header files in a public API header, remove them in v5.0
// Tracked in IDF-1968
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2

19
components/bootloader_support/src/bootloader_clock_init.c
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@ -8,23 +8,10 @@
#include "soc/rtc.h"
#include "soc/efuse_periph.h"
#include "soc/rtc_cntl_reg.h"
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#ifdef CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include "esp32/rom/rtc.h"
#undef CPU_RESET_REASON
#define CPU_RESET_REASON SW_CPU_RESET
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rtc.h"
#endif
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
__attribute__((weak)) void bootloader_clock_configure(void)
@ -52,7 +39,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
}
#endif
if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW) {
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
#if CONFIG_IDF_TARGET_ESP32
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;

2
components/bootloader_support/src/bootloader_common.c
View File

@ -189,5 +189,5 @@ void bootloader_common_vddsdio_configure(void)
RESET_REASON bootloader_common_get_reset_reason(int cpu_no)
{
return rtc_get_reset_reason(cpu_no);
return (RESET_REASON)esp_rom_get_reset_reason(cpu_no);
}

9
components/bootloader_support/src/bootloader_utility.c
View File

@ -13,23 +13,21 @@
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/rtc.h"
#include "esp32s3/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
@ -39,7 +37,6 @@
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/crc.h"
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h"
#include "esp32c3/rom/secure_boot.h"
@ -51,7 +48,6 @@
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/crc.h"
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
#include "esp32h2/rom/secure_boot.h"
@ -69,7 +65,6 @@
#include "soc/rtc_periph.h"
#include "soc/timer_periph.h"
#include "sdkconfig.h"
#include "esp_image_format.h"
#include "esp_secure_boot.h"
#include "esp_flash_encrypt.h"
@ -456,7 +451,7 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index)
#ifdef CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP
void bootloader_utility_load_boot_image_from_deep_sleep(void)
{
if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) {
if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) {
esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition();
if (partition != NULL) {
esp_image_metadata_t image_data;

15
components/bootloader_support/src/esp32/bootloader_esp32.c
View File

@ -33,7 +33,6 @@
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp_efuse.h"
static const char *TAG = "boot.esp32";
@ -323,17 +322,17 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
RESET_REASON rst_reas[2];
soc_reset_reason_t rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0);
rst_reas[1] = rtc_get_reset_reason(1);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
rst_reas[0] = esp_rom_get_reset_reason(0);
rst_reas[1] = esp_rom_get_reset_reason(1);
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
}
if (rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == TG1WDT_SYS_RESET ||
rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) {
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
wdt_rst = 1;
}

9
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@ -28,7 +28,6 @@
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/rtc.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "bootloader_clock.h"
@ -234,11 +233,9 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
RESET_REASON rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
}

9
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
View File

@ -28,7 +28,6 @@
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/rtc.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "bootloader_clock.h"
@ -233,11 +232,9 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
RESET_REASON rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
}

11
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
View File

@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <string.h>
#include "sdkconfig.h"
#include "bootloader_common.h"
#include "soc/efuse_reg.h"
@ -23,7 +24,6 @@
#include "esp_rom_sys.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp_attr.h"
#include "esp_log.h"
@ -35,7 +35,6 @@
#include "soc/extmem_reg.h"
#include "soc/rtc.h"
#include "soc/spi_periph.h"
#include <string.h>
#include "esp_efuse.h"
static const char *TAG = "boot.esp32s2";
@ -256,11 +255,9 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
RESET_REASON rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
}

14
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
View File

@ -265,14 +265,20 @@ static void wdt_reset_info_dump(int cpu)
static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
RESET_REASON rst_reas[2];
soc_reset_reason_t rst_reas[2];
rst_reas[0] = rtc_get_reset_reason(0);
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
rst_reas[0] = esp_rom_get_reset_reason(0);
rst_reas[1] = esp_rom_get_reset_reason(1);
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
}
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
wdt_rst = 1;
}
if (wdt_rst) {
// if reset by WDT dump info from trace port
wdt_reset_info_dump(0);

10
components/bootloader_support/src/esp_image_format.c
View File

@ -17,21 +17,17 @@
#include <bootloader_sha.h>
#include "bootloader_util.h"
#include "bootloader_common.h"
#include "esp_rom_sys.h"
#include "soc/soc_memory_layout.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "esp32s3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/secure_boot.h"
#endif
@ -254,7 +250,7 @@ esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metad
#if CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS
mode = ESP_IMAGE_LOAD_NO_VALIDATE;
#elif CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON
if (rtc_get_reset_reason(0) == POWERON_RESET) {
if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) {
mode = ESP_IMAGE_LOAD_NO_VALIDATE;
}
#endif // CONFIG_BOOTLOADER_SKIP_...
@ -685,7 +681,7 @@ static bool should_load(uint32_t load_addr)
{
/* Reload the RTC memory segments whenever a non-deepsleep reset
is occurring */
bool load_rtc_memory = rtc_get_reset_reason(0) != DEEPSLEEP_RESET;
bool load_rtc_memory = esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP;
if (should_map(load_addr)) {
return false;

5
components/esp_hw_support/sleep_modes.c
View File

@ -48,12 +48,13 @@
#include "sdkconfig.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "brownout.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#include "esp32/clk.h"
#include "esp32/rom/rtc.h"
#include "esp32/clk.h"
#include "esp_private/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/clk.h"
@ -1199,7 +1200,7 @@ esp_err_t esp_sleep_disable_wifi_wakeup(void)
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
{
if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) {
if (esp_rom_get_reset_reason(0) != RESET_REASON_CORE_DEEP_SLEEP && !s_light_sleep_wakeup) {
return ESP_SLEEP_WAKEUP_UNDEFINED;
}

8
components/esp_hw_support/test/test_rtc_clk.c
View File

@ -365,8 +365,8 @@ static void trigger_deepsleep(void)
static void check_time_deepsleep_1(void)
{
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
int64_t end = esp_rtc_get_time_us();
TEST_ASSERT_GREATER_THAN(start, end);
@ -385,8 +385,8 @@ static void check_time_deepsleep_1(void)
static void check_time_deepsleep_2(void)
{
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
int64_t end = esp_rtc_get_time_us();
TEST_ASSERT_GREATER_THAN(start, end);
}

14
components/esp_phy/src/phy_init.c
View File

@ -34,17 +34,12 @@
#include "driver/periph_ctrl.h"
#include "esp_private/wifi.h"
#include "esp_rom_crc.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#if CONFIG_IDF_TARGET_ESP32C3
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#endif
@ -605,12 +600,9 @@ void esp_phy_load_cal_and_init(void)
}
memcpy(init_data, phy_init_data, sizeof(esp_phy_init_data_t));
#if CONFIG_IDF_TARGET_ESP32
// ToDo: remove once esp_reset_reason is supported on esp32s2
if (esp_reset_reason() == ESP_RST_BROWNOUT) {
esp_phy_reduce_tx_power(init_data);
}
#endif
#else
const esp_phy_init_data_t* init_data = esp_phy_get_init_data();
if (init_data == NULL) {
@ -622,7 +614,7 @@ void esp_phy_load_cal_and_init(void)
#ifdef CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL;
uint8_t sta_mac[6];
if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) {
if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) {
calibration_mode = PHY_RF_CAL_NONE;
}
esp_err_t err = esp_phy_load_cal_data_from_nvs(cal_data);

1
components/esp_rom/esp32/ld/esp32.rom.api.ld
View File

@ -37,3 +37,4 @@ PROVIDE ( esp_rom_md5_final = 0x4005db1c );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
View File

@ -33,3 +33,4 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
View File

@ -33,3 +33,4 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
View File

@ -36,3 +36,4 @@ PROVIDE ( esp_rom_md5_final = 0x4000530c );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );

1
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
View File

@ -37,5 +37,6 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );

14
components/esp_rom/include/esp32/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
@ -98,6 +99,19 @@ typedef enum {
RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)SW_RESET == RESET_REASON_CORE_SW, "SW_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TGWDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TGWDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,

15
components/esp_rom/include/esp32c3/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
@ -99,6 +100,20 @@ typedef enum {
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,

15
components/esp_rom/include/esp32h2/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
@ -99,6 +100,20 @@ typedef enum {
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,

16
components/esp_rom/include/esp32s2/rom/rtc.h
View File

@ -22,6 +22,7 @@
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
@ -98,6 +99,21 @@ typedef enum {
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,

17
components/esp_rom/include/esp32s3/rom/rtc.h
View File

@ -17,6 +17,7 @@
#include <stdbool.h>
#include <stdint.h>
#include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
@ -93,6 +94,22 @@ typedef enum {
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
typedef enum {
NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0,

13
components/esp_rom/include/esp_rom_sys.h
View File

@ -14,12 +14,13 @@
#pragma once
#include <stdint.h>
#include "soc/reset_reasons.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief Print formated string to console device
* @note float and long long data are not supported!
@ -51,6 +52,14 @@ void esp_rom_install_channel_putc(int channel, void (*putc)(char c));
*/
void esp_rom_install_uart_printf(void);
/**
* @brief Get reset reason of CPU
*
* @param cpu_no CPU number
* @return Reset reason code (see in soc/reset_reasons.h)
*/
soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no);
#ifdef __cplusplus
}
#endif

19
components/esp_system/port/cpu_start.c
View File

@ -35,19 +35,16 @@
#include "soc/dport_reg.h"
#include "esp32/rtc.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp32/spiram.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rtc.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/spiram.h"
#include "esp32s2/dport_access.h"
#include "esp32s2/memprot.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rtc.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/rtc.h"
#include "esp32s3/spiram.h"
#include "esp32s3/dport_access.h"
#include "esp32s3/memprot.h"
@ -58,13 +55,11 @@
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h"
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/rtc.h"
#include "soc/cache_memory.h"
#include "esp32c3/memprot.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rtc.h"
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/rtc.h"
#include "soc/cache_memory.h"
#include "esp32h2/memprot.h"
#endif
@ -274,9 +269,9 @@ static void intr_matrix_clear(void)
void IRAM_ATTR call_start_cpu0(void)
{
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
RESET_REASON rst_reas[SOC_CPU_CORES_NUM];
soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
#else
RESET_REASON rst_reas[1];
soc_reset_reason_t rst_reas[1];
#endif
#ifdef __riscv
@ -301,16 +296,16 @@ void IRAM_ATTR call_start_cpu0(void)
// Move exception vectors to IRAM
cpu_hal_set_vecbase(&_vector_table);
rst_reas[0] = rtc_get_reset_reason(0);
rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
rst_reas[1] = rtc_get_reset_reason(1);
rst_reas[1] = esp_rom_get_reset_reason(1);
#endif
#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
// from panic handler we can be reset by RWDT or TG0WDT
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
|| rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0
#endif
) {
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
@ -329,7 +324,7 @@ void IRAM_ATTR call_start_cpu0(void)
#endif
/* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
if (rst_reas[0] != DEEPSLEEP_RESET) {
if (rst_reas[0] != RESET_REASON_CORE_DEEP_SLEEP) {
memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
}

15
components/esp_system/port/soc/esp32/clk.c
View File

@ -27,8 +27,8 @@
#include "esp_log.h"
#include "esp32/clk.h"
#include "esp32/rom/rtc.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "sdkconfig.h"
@ -213,23 +213,22 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t wifi_bt_sdio_clk;
#if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1];
soc_reset_reason_t rst_reas[1];
#else
RESET_REASON rst_reas[2];
soc_reset_reason_t rst_reas[2];
#endif
rst_reas[0] = rtc_get_reset_reason(0);
rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1);
rst_reas[1] = esp_rom_get_reset_reason(1);
#endif
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET)
if ((rst_reas[0] >= RESET_REASON_CPU0_MWDT0 && rst_reas[0] <= RESET_REASON_CPU0_RTC_WDT)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
|| (rst_reas[1] >= RESET_REASON_CPU1_MWDT1 && rst_reas[1] <= RESET_REASON_CPU1_RTC_WDT)
#endif
) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);

66
components/esp_system/port/soc/esp32/reset_reason.c
View File

@ -13,67 +13,61 @@
// limitations under the License.
#include "esp_system.h"
#include "esp32/rom/rtc.h"
#include "esp_rom_sys.h"
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
#include "esp32/rom/rtc.h"
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
static esp_reset_reason_t get_reset_reason(uint32_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
case POWERON_RESET:
return ESP_RST_POWERON;
case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON;
/* For ESP32, ESP_RST_EXT is never returned */
case SW_CPU_RESET:
case SW_RESET:
case EXT_CPU_RESET: /* unused */
if (reset_reason_hint == ESP_RST_PANIC ||
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
return reset_reason_hint;
}
return ESP_RST_SW;
case DEEPSLEEP_RESET:
return ESP_RST_DEEPSLEEP;
case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET:
return ESP_RST_TASK_WDT;
case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET:
return ESP_RST_INT_WDT;
case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT;
case OWDT_RESET:
case RTCWDT_SYS_RESET:
case RTCWDT_RTC_RESET:
case RTCWDT_CPU_RESET: /* unused */
case TGWDT_CPU_RESET: /* unused */
return ESP_RST_WDT;
case RESET_REASON_CORE_RTC_WDT:
case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_CPU0_RTC_WDT:
case RESET_REASON_CPU0_MWDT0:
return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: /* unused */
return ESP_RST_BROWNOUT;
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
case SDIO_RESET:
return ESP_RST_SDIO;
case RESET_REASON_CORE_SDIO:
return ESP_RST_SDIO;
case INTRUSION_RESET: /* unused */
default:
return ESP_RST_UNKNOWN;
default:
return ESP_RST_UNKNOWN;
}
}
static void __attribute__((constructor)) esp_reset_reason_init(void)
{
esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
hint);
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint();
}
@ -88,7 +82,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous.
* esp_rom_get_reset_reason is unambiguous.
*
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that,

25
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -23,7 +23,6 @@
#include "esp_clk_internal.h"
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/rtc.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "soc/soc.h"
@ -36,6 +35,7 @@
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive
@ -75,9 +75,9 @@ static const char *TAG = "clk";
{
#if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas;
rst_reas = rtc_get_reset_reason(0);
if (rst_reas == POWERON_RESET) {
soc_reset_reason_t rst_reas;
rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1;
}
rtc_init(cfg);
@ -211,16 +211,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1];
#else
RESET_REASON rst_reas[2];
#endif
rst_reas[0] = rtc_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1);
#endif
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
@ -228,11 +219,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
#endif
) {
if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);

43
components/esp_system/port/soc/esp32c3/reset_reason.c
View File

@ -13,51 +13,51 @@
// limitations under the License.
#include "esp_system.h"
#include "esp32c3/rom/rtc.h"
#include "esp_rom_sys.h"
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
#include "esp32c3/rom/rtc.h"
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
case POWERON_RESET:
case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON;
case RTC_SW_CPU_RESET:
case RTC_SW_SYS_RESET:
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
case DEEPSLEEP_RESET:
case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET:
case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET:
case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET:
case RTCWDT_RTC_RESET:
case SUPER_WDT_RESET:
case RTCWDT_CPU_RESET: /* unused */
case TG0WDT_CPU_RESET: /* unused */
case TG1WDT_CPU_RESET: /* unused */
case RESET_REASON_CORE_RTC_WDT:
case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_SYS_SUPER_WDT:
case RESET_REASON_CPU0_RTC_WDT:
case RESET_REASON_CPU0_MWDT0:
case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET:
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default:
return ESP_RST_UNKNOWN;
}
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void)
{
esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
hint);
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint();
}
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous.
* esp_rom_get_reset_reason is unambiguous.
*
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that,

25
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -23,7 +23,6 @@
#include "esp_clk_internal.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/rtc.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "soc/soc.h"
@ -36,6 +35,7 @@
#include "bootloader_clock.h"
#include "soc/syscon_reg.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive
@ -75,9 +75,9 @@ static const char *TAG = "clk";
{
#if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas;
rst_reas = rtc_get_reset_reason(0);
if (rst_reas == POWERON_RESET) {
soc_reset_reason_t rst_reas;
rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1;
}
rtc_init(cfg);
@ -211,16 +211,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk = 0;
uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1];
#else
RESET_REASON rst_reas[2];
#endif
rst_reas[0] = rtc_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1);
#endif
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
@ -228,11 +219,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
#endif
) {
if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
} else {

37
components/esp_system/port/soc/esp32h2/reset_reason.c
View File

@ -13,22 +13,23 @@
// limitations under the License.
#include "esp_system.h"
#include "esp32h2/rom/rtc.h"
#include "esp_rom_sys.h"
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
#include "esp32h2/rom/rtc.h"
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
case POWERON_RESET:
case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON;
case RTC_SW_CPU_RESET:
case RTC_SW_SYS_RESET:
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
@ -37,27 +38,26 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
}
return ESP_RST_SW;
case DEEPSLEEP_RESET:
case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET:
case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET:
case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET:
case RTCWDT_RTC_RESET:
case SUPER_WDT_RESET:
case RTCWDT_CPU_RESET: /* unused */
case TG0WDT_CPU_RESET: /* unused */
case TG1WDT_CPU_RESET: /* unused */
case RESET_REASON_CORE_RTC_WDT:
case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_SYS_SUPER_WDT:
case RESET_REASON_CPU0_RTC_WDT:
case RESET_REASON_CPU0_MWDT0:
case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET:
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default:
return ESP_RST_UNKNOWN;
}
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void)
{
esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
hint);
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint();
}
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous.
* esp_rom_get_reset_reason is unambiguous.
*
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that,

15
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -22,8 +22,8 @@
#include "esp_log.h"
#include "esp32s2/clk.h"
#include "esp_clk_internal.h"
#include "esp32s2/rom/rtc.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "soc/soc.h"
@ -77,9 +77,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
__attribute__((weak)) void esp_clk_init(void)
{
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
RESET_REASON rst_reas;
rst_reas = rtc_get_reset_reason(0);
if (rst_reas == POWERON_RESET) {
soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
cfg.cali_ocode = 1;
}
rtc_init(cfg);
@ -214,16 +213,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0;
RESET_REASON rst_reas[1];
rst_reas[0] = rtc_get_reset_reason(0);
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reas[0] >= TG0WDT_CPU_RESET &&
rst_reas[0] <= TG0WDT_CPU_RESET &&
rst_reas[0] != RTCWDT_BROWN_OUT_RESET) {
if (rst_reason >= RESET_REASON_CPU0_MWDT0 && rst_reason <= RESET_REASON_CPU0_RTC_WDT && rst_reason != RESET_REASON_SYS_BROWN_OUT) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);

67
components/esp_system/port/soc/esp32s2/reset_reason.c
View File

@ -13,61 +13,60 @@
// limitations under the License.
#include "esp_system.h"
#include "esp32s2/rom/rtc.h"
#include "esp_rom_sys.h"
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
#include "esp32s2/rom/rtc.h"
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
case POWERON_RESET:
return ESP_RST_POWERON;
case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON;
case RTC_SW_CPU_RESET:
case RTC_SW_SYS_RESET:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
case DEEPSLEEP_RESET:
return ESP_RST_DEEPSLEEP;
case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET:
return ESP_RST_TASK_WDT;
case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET:
return ESP_RST_INT_WDT;
case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET:
case RTCWDT_RTC_RESET:
case SUPER_WDT_RESET:
case RTCWDT_CPU_RESET: /* unused */
case TG0WDT_CPU_RESET: /* unused */
case TG1WDT_CPU_RESET: /* unused */
return ESP_RST_WDT;
case RESET_REASON_CORE_RTC_WDT:
case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_SYS_SUPER_WDT:
case RESET_REASON_CPU0_RTC_WDT:
case RESET_REASON_CPU0_MWDT0:
case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET:
return ESP_RST_BROWNOUT;
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default:
return ESP_RST_UNKNOWN;
default:
return ESP_RST_UNKNOWN;
}
}
static void __attribute__((constructor)) esp_reset_reason_init(void)
{
esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
hint);
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint();
}
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous.
* esp_rom_get_reset_reason is unambiguous.
*
* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
* the value is replicated in low and high half-words. In addition to that,

15
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -22,9 +22,8 @@
#include "esp_log.h"
#include "esp32s3/clk.h"
#include "esp_clk_internal.h"
#include "esp32s3/rom/ets_sys.h"
#include "esp32s3/rom/rtc.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "soc/soc.h"
@ -210,22 +209,22 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1];
soc_reset_reason_t rst_reas[1];
#else
RESET_REASON rst_reas[2];
soc_reset_reason_t rst_reas[2];
#endif
rst_reas[0] = rtc_get_reset_reason(0);
rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = rtc_get_reset_reason(1);
rst_reas[1] = esp_rom_get_reset_reason(1);
#endif
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
if ((rst_reas[0] >= RESET_REASON_CPU0_MWDT0 && rst_reas[0] <= RESET_REASON_CPU0_RTC_WDT && rst_reas[0] != RESET_REASON_SYS_BROWN_OUT)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TG0WDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
|| (rst_reas[1] >= RESET_REASON_CPU1_MWDT1 && rst_reas[1] <= RESET_REASON_CPU1_RTC_WDT && rst_reas[1] != RESET_REASON_SYS_BROWN_OUT)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);

43
components/esp_system/port/soc/esp32s3/reset_reason.c
View File

@ -13,51 +13,51 @@
// limitations under the License.
#include "esp_system.h"
#include "esp32s3/rom/rtc.h"
#include "esp_rom_sys.h"
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
#include "esp32s3/rom/rtc.h"
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
case POWERON_RESET:
case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON;
case RTC_SW_CPU_RESET:
case RTC_SW_SYS_RESET:
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
case DEEPSLEEP_RESET:
case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET:
case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET:
case RESET_REASON_CORE_MWDT1:
return ESP_RST_INT_WDT;
case RTCWDT_SYS_RESET:
case RTCWDT_RTC_RESET:
case SUPER_WDT_RESET:
case RTCWDT_CPU_RESET: /* unused */
case TG0WDT_CPU_RESET: /* unused */
case TG1WDT_CPU_RESET: /* unused */
case RESET_REASON_CORE_RTC_WDT:
case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_SYS_SUPER_WDT:
case RESET_REASON_CPU0_RTC_WDT:
case RESET_REASON_CPU0_MWDT0:
case RESET_REASON_CPU0_MWDT1:
return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET:
case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default:
return ESP_RST_UNKNOWN;
}
@ -66,8 +66,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void)
{
esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
hint);
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint();
}
@ -82,7 +81,7 @@ esp_reset_reason_t esp_reset_reason(void)
* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
* deep sleep wake stub entry address and for reset reason hint, since wake stub
* is only used for deep sleep reset, and in this case the reason provided by
* rtc_get_reset_reason is unambiguous.
* esp_rom_get_reset_reason is unambiguous.
*
* In addition to that, MSB is set to 1, which doesn't happen when
* RTC_CNTL_STORE6_REG contains deep sleep wake stub address.

11
components/esp_system/test/test_sleep.c
View File

@ -3,7 +3,6 @@
#include <sys/param.h>
#include "esp_sleep.h"
#include "driver/rtc_io.h"
#include "esp_rom_uart.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -17,6 +16,7 @@
#include "esp_newlib.h"
#include "test_utils.h"
#include "sdkconfig.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_timer.h"
@ -24,19 +24,14 @@
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/clk.h"
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/clk.h"
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/clk.h"
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/clk.h"
#include "esp32h2/rom/rtc.h"
#endif
#define ESP_EXT0_WAKEUP_LEVEL_LOW 0
@ -531,8 +526,8 @@ static void trigger_deepsleep(void)
static void check_time_deepsleep(void)
{
struct timeval stop;
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
gettimeofday(&stop, NULL);
// Time dt_ms must in any case be positive.
int dt_ms = (stop.tv_sec - start.tv_sec) * 1000 + (stop.tv_usec - start.tv_usec) / 1000;

58
components/soc/esp32/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,58 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU1_MWDT1 = 0x0B, // Main watch dog 1 resets CPU 1
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0
RESET_REASON_CPU1_SW = 0x0C, // Software resets CPU 1
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_CPU1_RTC_WDT = 0x0D, // RTC watch dog resets CPU 1
RESET_REASON_CPU1_CPU0 = 0x0E, // CPU0 resets CPU1 by DPORT_APPCPU_RESETTING
RESET_REASON_SYS_BROWN_OUT = 0x0F, // Reset when the VDD voltage is not stable
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

61
components/soc/esp32c3/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,61 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

61
components/soc/esp32h2/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,61 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

58
components/soc/esp32s2/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,58 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

64
components/soc/esp32s3/include/soc/reset_reasons.h Normal file
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@ -0,0 +1,64 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU1_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 1
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU1_SW = 0x0C, // Software resets CPU 1 by RTC_CNTL_SW_APPCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_CPU1_RTC_WDT = 0x0D, // RTC watch dog resets CPU 1
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_CPU1_MWDT1 = 0x11, // Main watch dog 1 resets CPU 1
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

4
docs/en/api-guides/unit-tests-legacy.rst
View File

@ -120,8 +120,8 @@ To support this, we can define multi-stage test cases, to group a set of test fu
void check_deepsleep_reset_reason()
{
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
}
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[esp32]", trigger_deepsleep, check_deepsleep_reset_reason);

8
docs/en/api-guides/unit-tests.rst
View File

@ -108,8 +108,8 @@ The normal test cases are expected to finish without reset (or only need to chec
void check_deepsleep_reset_reason()
{
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
}
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[{IDF_TARGET_PATH_NAME}]", trigger_deepsleep, check_deepsleep_reset_reason);
@ -173,7 +173,7 @@ Change into ``tools/unit-test-app`` directory to configure and build it:
.. note::
Due to inherent limitations of Windows command prompt, following syntax has to be used in order to build unit-test-app with multiple components: ``idf.py -T xxx -T yyy build`` or with escaped quoates: ``idf.py -T \`"xxx yyy\`" build`` in PowerShell or ``idf.py -T \^"ssd1306 hts221\^" build`` in Windows command prompt.
When the build finishes, it will print instructions for flashing the chip. You can simply run ``idf.py flash`` to flash all build output.
You can also run ``idf.py -T all flash`` or ``idf.py -T xxx flash`` to build and flash. Everything needed will be rebuilt automatically before flashing.
@ -285,7 +285,7 @@ Besides the usual IDF requirements, ``ruby`` is necessary to generate the mocks.
In IDF, adjustments are necessary inside the component(s) that should be mocked as well as inside the unit test, compared to writing normal components or unit tests without mocking.
Adjustments in Mock Component
Adjustments in Mock Component
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The component that should be mocked requires a separate ``mock`` directory containing all additional files needed specifically for the mocking. Most importantly, it contains ``mock_config.yaml`` which configures CMock. For more details on what the options inside that configuration file mean and how to write your own, please take a look at the :component_file:`CMock documentation <cmock/CMock/docs/CMock_Summary.md>`. It may be necessary to have some more files related to mocking which should also be placed inside the `mock` directory.

4
docs/zh_CN/api-guides/unit-tests-legacy.rst
View File

@ -137,8 +137,8 @@ DUT2 终端::
void check_deepsleep_reset_reason()
{
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
}
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[esp32]", trigger_deepsleep, check_deepsleep_reset_reason);

10
docs/zh_CN/api-guides/unit-tests.rst
View File

@ -105,8 +105,8 @@ DUT2（slave）终端::
void check_deepsleep_reset_reason()
{
RESET_REASON reason = rtc_get_reset_reason(0);
TEST_ASSERT(reason == DEEPSLEEP_RESET);
soc_reset_reason_t reason = esp_rom_get_reset_reason(0);
TEST_ASSERT(reason == RESET_REASON_CORE_DEEP_SLEEP);
}
TEST_CASE_MULTIPLE_STAGES("reset reason check for deepsleep", "[{IDF_TARGET_PATH_NAME}]", trigger_deepsleep, check_deepsleep_reset_reason);
@ -120,7 +120,7 @@ DUT2（slave）终端::
1. 使用宏 ``!(TEMPORARY_)DISABLED_FOR_TARGETS()`` 包装你的测试代码，并将其放于原始的测试文件中，或将代码分成按功能分组的文件。但请确保所有这些文件都会由编译器处理。例::
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP8266)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP8266)
TEST_CASE("a test that is not ready for esp32 and esp8266 yet", "[]")
{
}
@ -170,7 +170,7 @@ DUT2（slave）终端::
.. note::
由于 Windows 命令提示符固有限制，需使用以下语法来编译多个组件的单元测试程序：``idf.py -T xxx -T yyy build`` 或者在 PowerShell 中使用 ``idf.py -T \`"xxx yyy\`" build``，在 Windows 命令提示符中使用 ``idf.py -T \^"ssd1306 hts221\^" build``。
当编译完成时，它会打印出烧写芯片的指令。您只需要运行 ``idf.py flash`` 即可烧写所有编译输出的文件。
您还可以运行 ``idf.py -T all flash`` 或者 ``idf.py -T xxx flash`` 来编译并烧写，所有需要的文件都会在烧写之前自动重新编译。
@ -279,7 +279,7 @@ ESP-IDF 有一个集成 CMock mocking 框架的组件。CMock 通常使用 Unity
要使用 IDF 提供的 Unity 组件（不是子模块)，构建系统需要传递一个环境变量 ``UNITY_IDR`` 给 CMock。该变量仅包含 IDF 中 Unity 目录的路径，如 ``export "UNITY_DIR=${IDF_PATH}/components/unity/unity"``。
关于 CMock 中 Unity 目录是如何确定的，请参考 :component_file:`cmock/CMock/lib/cmock_generator.rb`。
在组件的 CMakeLists.txt 中创建组件的 mock 的 cmake 编译命令可能如下所示：
.. code-block:: cmake

4
tools/ci/check_public_headers_exceptions.txt
View File

@ -111,11 +111,15 @@ components/esp_hw_support/port/esp32/regi2c_ctrl.h
components/esp_rom/include/esp32/rom/sha.h
components/esp_rom/include/esp32/rom/secure_boot.h
components/esp_rom/include/esp32c3/rom/spi_flash.h
components/esp_rom/include/esp32c3/rom/rtc.h
components/esp_rom/include/esp32s2/rom/spi_flash.h
components/esp_rom/include/esp32s2/rom/cache.h
components/esp_rom/include/esp32s2/rom/secure_boot.h
components/esp_rom/include/esp32s2/rom/opi_flash.h
components/esp_rom/include/esp32s2/rom/rtc.h
components/esp_rom/include/esp32s2/rom/efuse.h
components/esp_rom/include/esp32s3/rom/rtc.h
components/esp_rom/include/esp32h2/rom/rtc.h
components/esp32/include/esp32/dport_access.h
components/esp32/include/rom/sha.h
components/esp32/include/rom/secure_boot.h