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update esp32h2beta2 chip_id to 14

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This commit is contained in:
wuzhenghui 2021-10-18 17:02:19 +08:00 committed by laokaiyao
parent 968c42d88c
commit 388615add0
44 changed files with 7536 additions and 906 deletions
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4
Kconfig
View File

@ -72,6 +72,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_TARGET_ESP32H2_BETA_VERSION_2
bool
prompt "ESP32-H2 beta2"
select ESPTOOLPY_NO_STUB # TODO: IDF-4288
endchoice
config IDF_TARGET_ESP8684
@ -92,8 +93,9 @@ mainmenu "Espressif IoT Development Framework Configuration"
default 0x0002 if IDF_TARGET_ESP32S2
default 0x0005 if IDF_TARGET_ESP32C3
default 0x0009 if IDF_TARGET_ESP32S3
default 0x000A if IDF_TARGET_ESP32H2 # ESP32H2-TODO: IDF-3475
default 0x000C if IDF_TARGET_ESP8684
default 0x000A if IDF_TARGET_ESP32H2_BETA_VERSION_1
default 0x000E if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3475
default 0xFFFF
menu "SDK tool configuration"

6
components/bootloader_support/include/esp_app_format.h
View File

@ -16,8 +16,12 @@ typedef enum {
ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */
ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 */ // ESP32H2-TODO: IDF-3475
ESP_CHIP_ID_ESP8684 = 0x000C, /*!< chip ID: ESP32-8684 */
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
ESP_CHIP_ID_ESP32H2 = 0x000E, /*!< chip ID: ESP32-H2 Beta2*/ // ESP32H2-TODO: IDF-3475
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */
#endif
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;

119
components/esp_hw_support/port/esp32h2/rtc_sleep.c
View File

@ -24,6 +24,18 @@
#include "soc_log.h"
#include "esp_rom_uart.h"
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG
#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG
#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG
#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG RTC_CNTL_DIGULATOR0_DBIAS_REG
#define RTC_CNTL_REGULATOR1_DBIAS_REG RTC_CNTL_RTCULATOR1_DBIAS_REG
#define RTC_CNTL_REGULATOR0_DBIAS_REG RTC_CNTL_RTCULATOR0_DBIAS_REG
#endif
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
@ -75,62 +87,34 @@ void dcdc_ctl(uint32_t mode)
void regulator_set(regulator_cfg_t cfg)
{
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
// DIG REGULATOR0
if (cfg.dig_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
}
// DIG REGULATOR1
if (cfg.dig_regul1_en) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
}
// RTC REGULATOR0
if (cfg.rtc_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 1);
}
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
// DIG REGULATOR0
if (cfg.dig_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
}
// DIG REGULATOR1
if (cfg.dig_regul1_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
}
// RTC REGULATOR0
if (cfg.rtc_regul0_en) {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1);
}
#endif
}
void regulator_slt(regulator_config_t regula_cfg)
{
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
// dig regulator
if (regula_cfg.dig_source == 1) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
@ -147,37 +131,13 @@ void regulator_slt(regulator_config_t regula_cfg)
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
}
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
// dig regulator
if (regula_cfg.dig_source == 1) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
}
// rtc regulator
if (regula_cfg.rtc_source == 1) {
REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
}
#endif
}
void dbias_switch_set(dbias_swt_cfg_t cfg)
{
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
#endif
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
}
void left_up_trx_fpu(bool fpu)
@ -240,37 +200,20 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
// ESP32-H2 TO-DO: IDF-3693
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
if (cfg.deep_slp) {
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
if (cfg.deep_slp) {
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
#endif
/* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);

BIN
components/esp_rom/eagle.pro.rom.out
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Binary file not shown.

6
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
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@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 );

6
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.libgcc.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib-nano.ld
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@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.newlib.ld
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@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z
*
*

6
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.version.ld
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@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32b1z
*
* These addresses should be compatible with any ROM version for this chip.

6
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
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@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** ROM APIs
*/
PROVIDE ( esp_rom_tjpgd_decomp = 0x40000104 );

2360
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld
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File diff suppressed because it is too large Load Diff

190
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld
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@ -1,7 +1,13 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h2.rom.libgcc.ld for esp32h2
*
*
* Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,93 +19,95 @@
***************************************/
/* Functions */
__absvdi2 = 0x40000738;
__absvsi2 = 0x4000073c;
__adddf3 = 0x40000740;
__addsf3 = 0x40000744;
__addvdi3 = 0x40000748;
__addvsi3 = 0x4000074c;
__ashldi3 = 0x40000750;
__ashrdi3 = 0x40000754;
__bswapdi2 = 0x40000758;
__bswapsi2 = 0x4000075c;
__clear_cache = 0x40000760;
__clrsbdi2 = 0x40000764;
__clrsbsi2 = 0x40000768;
__clzdi2 = 0x4000076c;
__clzsi2 = 0x40000770;
__cmpdi2 = 0x40000774;
__ctzdi2 = 0x40000778;
__ctzsi2 = 0x4000077c;
__divdc3 = 0x40000780;
__divdf3 = 0x40000784;
__divdi3 = 0x40000788;
__divsc3 = 0x4000078c;
__divsf3 = 0x40000790;
__divsi3 = 0x40000794;
__eqdf2 = 0x40000798;
__eqsf2 = 0x4000079c;
__extendsfdf2 = 0x400007a0;
__ffsdi2 = 0x400007a4;
__ffssi2 = 0x400007a8;
__fixdfdi = 0x400007ac;
__fixdfsi = 0x400007b0;
__fixsfdi = 0x400007b4;
__fixsfsi = 0x400007b8;
__fixunsdfsi = 0x400007bc;
__fixunssfdi = 0x400007c0;
__fixunssfsi = 0x400007c4;
__floatdidf = 0x400007c8;
__floatdisf = 0x400007cc;
__floatsidf = 0x400007d0;
__floatsisf = 0x400007d4;
__floatundidf = 0x400007d8;
__floatundisf = 0x400007dc;
__floatunsidf = 0x400007e0;
__floatunsisf = 0x400007e4;
__gcc_bcmp = 0x400007e8;
__gedf2 = 0x400007ec;
__gesf2 = 0x400007f0;
__gtdf2 = 0x400007f4;
__gtsf2 = 0x400007f8;
__ledf2 = 0x400007fc;
__lesf2 = 0x40000800;
__lshrdi3 = 0x40000804;
__ltdf2 = 0x40000808;
__ltsf2 = 0x4000080c;
__moddi3 = 0x40000810;
__modsi3 = 0x40000814;
__muldc3 = 0x40000818;
__muldf3 = 0x4000081c;
__muldi3 = 0x40000820;
__mulsc3 = 0x40000824;
__mulsf3 = 0x40000828;
__mulsi3 = 0x4000082c;
__mulvdi3 = 0x40000830;
__mulvsi3 = 0x40000834;
__nedf2 = 0x40000838;
__negdf2 = 0x4000083c;
__negdi2 = 0x40000840;
__negsf2 = 0x40000844;
__negvdi2 = 0x40000848;
__negvsi2 = 0x4000084c;
__nesf2 = 0x40000850;
__paritysi2 = 0x40000854;
__popcountdi2 = 0x40000858;
__popcountsi2 = 0x4000085c;
__powidf2 = 0x40000860;
__powisf2 = 0x40000864;
__subdf3 = 0x40000868;
__subsf3 = 0x4000086c;
__subvdi3 = 0x40000870;
__subvsi3 = 0x40000874;
__truncdfsf2 = 0x40000878;
__ucmpdi2 = 0x4000087c;
__udivdi3 = 0x40000880;
__udivmoddi4 = 0x40000884;
__udivsi3 = 0x40000888;
__udiv_w_sdiv = 0x4000088c;
__umoddi3 = 0x40000890;
__umodsi3 = 0x40000894;
__unorddf2 = 0x40000898;
__unordsf2 = 0x4000089c;
__absvdi2 = 0x4000098c;
__absvsi2 = 0x40000990;
__adddf3 = 0x40000994;
__addsf3 = 0x40000998;
__addvdi3 = 0x4000099c;
__addvsi3 = 0x400009a0;
__ashldi3 = 0x400009a4;
__ashrdi3 = 0x400009a8;
__bswapdi2 = 0x400009ac;
__bswapsi2 = 0x400009b0;
__clear_cache = 0x400009b4;
__clrsbdi2 = 0x400009b8;
__clrsbsi2 = 0x400009bc;
__clzdi2 = 0x400009c0;
__clzsi2 = 0x400009c4;
__cmpdi2 = 0x400009c8;
__ctzdi2 = 0x400009cc;
__ctzsi2 = 0x400009d0;
__divdc3 = 0x400009d4;
__divdf3 = 0x400009d8;
__divdi3 = 0x400009dc;
__divsc3 = 0x400009e0;
__divsf3 = 0x400009e4;
__divsi3 = 0x400009e8;
__eqdf2 = 0x400009ec;
__eqsf2 = 0x400009f0;
__extendsfdf2 = 0x400009f4;
__ffsdi2 = 0x400009f8;
__ffssi2 = 0x400009fc;
__fixdfdi = 0x40000a00;
__fixdfsi = 0x40000a04;
__fixsfdi = 0x40000a08;
__fixsfsi = 0x40000a0c;
__fixunsdfsi = 0x40000a10;
__fixunssfdi = 0x40000a14;
__fixunssfsi = 0x40000a18;
__floatdidf = 0x40000a1c;
__floatdisf = 0x40000a20;
__floatsidf = 0x40000a24;
__floatsisf = 0x40000a28;
__floatundidf = 0x40000a2c;
__floatundisf = 0x40000a30;
__floatunsidf = 0x40000a34;
__floatunsisf = 0x40000a38;
__gcc_bcmp = 0x40000a3c;
__gedf2 = 0x40000a40;
__gesf2 = 0x40000a44;
__gtdf2 = 0x40000a48;
__gtsf2 = 0x40000a4c;
__ledf2 = 0x40000a50;
__lesf2 = 0x40000a54;
__lshrdi3 = 0x40000a58;
__ltdf2 = 0x40000a5c;
__ltsf2 = 0x40000a60;
__moddi3 = 0x40000a64;
__modsi3 = 0x40000a68;
__muldc3 = 0x40000a6c;
__muldf3 = 0x40000a70;
__muldi3 = 0x40000a74;
__mulsc3 = 0x40000a78;
__mulsf3 = 0x40000a7c;
__mulsi3 = 0x40000a80;
__mulvdi3 = 0x40000a84;
__mulvsi3 = 0x40000a88;
__nedf2 = 0x40000a8c;
__negdf2 = 0x40000a90;
__negdi2 = 0x40000a94;
__negsf2 = 0x40000a98;
__negvdi2 = 0x40000a9c;
__negvsi2 = 0x40000aa0;
__nesf2 = 0x40000aa4;
__paritysi2 = 0x40000aa8;
__popcountdi2 = 0x40000aac;
__popcountsi2 = 0x40000ab0;
__powidf2 = 0x40000ab4;
__powisf2 = 0x40000ab8;
__subdf3 = 0x40000abc;
__subsf3 = 0x40000ac0;
__subvdi3 = 0x40000ac4;
__subvsi3 = 0x40000ac8;
__truncdfsf2 = 0x40000acc;
__ucmpdi2 = 0x40000ad0;
__udivdi3 = 0x40000ad4;
__udivmoddi4 = 0x40000ad8;
__udivsi3 = 0x40000adc;
__udiv_w_sdiv = 0x40000ae0;
__umoddi3 = 0x40000ae4;
__umodsi3 = 0x40000ae8;
__unorddf2 = 0x40000aec;
__unordsf2 = 0x40000af0;
__extenddftf2 = 0x40000af4;
__trunctfdf2 = 0x40000af8;

47
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld
View File

@ -1,7 +1,13 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2
*
*
* Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,15 +19,30 @@
***************************************/
/* Functions */
__sprint_r = 0x4000044c;
_fiprintf_r = 0x40000450;
_fprintf_r = 0x40000454;
_printf_common = 0x40000458;
_printf_i = 0x4000045c;
_vfiprintf_r = 0x40000460;
_vfprintf_r = 0x40000464;
fiprintf = 0x40000468;
fprintf = 0x4000046c;
printf = 0x40000470;
vfiprintf = 0x40000474;
vfprintf = 0x40000478;
__sprint_r = 0x40000674;
_fiprintf_r = 0x40000678;
_fprintf_r = 0x4000067c;
_printf_common = 0x40000680;
_printf_i = 0x40000684;
_vfiprintf_r = 0x40000688;
_vfprintf_r = 0x4000068c;
fiprintf = 0x40000690;
fprintf = 0x40000694;
printf = 0x40000698;
vfiprintf = 0x4000069c;
vfprintf = 0x400006a0;
asprintf = 0x400006a4;
sprintf = 0x400006a8;
snprintf = 0x400006ac;
siprintf = 0x400006b0;
sniprintf = 0x400006b4;
vprintf = 0x400006b8;
viprintf = 0x400006bc;
vsnprintf = 0x400006c0;
vsniprintf = 0x400006c4;
__rom_printf_float = 0x400006c8;
__rom_scanf_float = 0x400006cc;
_scanf_i = 0x400006d0;
_scanf_chars = 0x400006d4;
sscanf = 0x400006d8;
siscanf = 0x400006dc;

212
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld
View File

@ -1,7 +1,13 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM function interface esp32h2.rom.newlib.ld for esp32h2
*
*
* Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3
* Generated from ./interface-esp32h2.yml md5sum a4343bd6a9a68319e4e3cc26aea38574
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,82 +19,130 @@
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x4000031c;
memset = 0x40000320;
memcpy = 0x40000324;
memmove = 0x40000328;
memcmp = 0x4000032c;
strcpy = 0x40000330;
strncpy = 0x40000334;
strcmp = 0x40000338;
strncmp = 0x4000033c;
strlen = 0x40000340;
strstr = 0x40000344;
bzero = 0x40000348;
_isatty_r = 0x4000034c;
sbrk = 0x40000350;
isalnum = 0x40000354;
isalpha = 0x40000358;
isascii = 0x4000035c;
isblank = 0x40000360;
iscntrl = 0x40000364;
isdigit = 0x40000368;
islower = 0x4000036c;
isgraph = 0x40000370;
isprint = 0x40000374;
ispunct = 0x40000378;
isspace = 0x4000037c;
isupper = 0x40000380;
toupper = 0x40000384;
tolower = 0x40000388;
toascii = 0x4000038c;
memccpy = 0x40000390;
memchr = 0x40000394;
memrchr = 0x40000398;
strcasecmp = 0x4000039c;
strcasestr = 0x400003a0;
strcat = 0x400003a4;
strdup = 0x400003a8;
strchr = 0x400003ac;
strcspn = 0x400003b0;
strcoll = 0x400003b4;
strlcat = 0x400003b8;
strlcpy = 0x400003bc;
strlwr = 0x400003c0;
strncasecmp = 0x400003c4;
strncat = 0x400003c8;
strndup = 0x400003cc;
strnlen = 0x400003d0;
strrchr = 0x400003d4;
strsep = 0x400003d8;
strspn = 0x400003dc;
strtok_r = 0x400003e0;
strupr = 0x400003e4;
longjmp = 0x400003e8;
setjmp = 0x400003ec;
abs = 0x400003f0;
div = 0x400003f4;
labs = 0x400003f8;
ldiv = 0x400003fc;
qsort = 0x40000400;
rand_r = 0x40000404;
rand = 0x40000408;
srand = 0x4000040c;
utoa = 0x40000410;
itoa = 0x40000414;
atoi = 0x40000418;
atol = 0x4000041c;
strtol = 0x40000420;
strtoul = 0x40000424;
PROVIDE( fflush = 0x40000428 );
PROVIDE( _fflush_r = 0x4000042c );
PROVIDE( _fwalk = 0x40000430 );
PROVIDE( _fwalk_reent = 0x40000434 );
PROVIDE( __smakebuf_r = 0x40000438 );
PROVIDE( __swhatbuf_r = 0x4000043c );
PROVIDE( __swbuf_r = 0x40000440 );
__swbuf = 0x40000444;
PROVIDE( __swsetup_r = 0x40000448 );
esp_rom_newlib_init_common_mutexes = 0x40000484;
memset = 0x40000488;
memcpy = 0x4000048c;
memmove = 0x40000490;
memcmp = 0x40000494;
strcpy = 0x40000498;
strncpy = 0x4000049c;
strcmp = 0x400004a0;
strncmp = 0x400004a4;
strlen = 0x400004a8;
strstr = 0x400004ac;
bzero = 0x400004b0;
_isatty_r = 0x400004b4;
sbrk = 0x400004b8;
isalnum = 0x400004bc;
isalpha = 0x400004c0;
isascii = 0x400004c4;
isblank = 0x400004c8;
iscntrl = 0x400004cc;
isdigit = 0x400004d0;
islower = 0x400004d4;
isgraph = 0x400004d8;
isprint = 0x400004dc;
ispunct = 0x400004e0;
isspace = 0x400004e4;
isupper = 0x400004e8;
toupper = 0x400004ec;
tolower = 0x400004f0;
toascii = 0x400004f4;
memccpy = 0x400004f8;
memchr = 0x400004fc;
memrchr = 0x40000500;
strcasecmp = 0x40000504;
strcasestr = 0x40000508;
strcat = 0x4000050c;
strdup = 0x40000510;
strchr = 0x40000514;
strcspn = 0x40000518;
strcoll = 0x4000051c;
strlcat = 0x40000520;
strlcpy = 0x40000524;
strlwr = 0x40000528;
strncasecmp = 0x4000052c;
strncat = 0x40000530;
strndup = 0x40000534;
strnlen = 0x40000538;
strrchr = 0x4000053c;
strsep = 0x40000540;
strspn = 0x40000544;
strtok_r = 0x40000548;
strupr = 0x4000054c;
longjmp = 0x40000550;
setjmp = 0x40000554;
abs = 0x40000558;
div = 0x4000055c;
labs = 0x40000560;
ldiv = 0x40000564;
qsort = 0x40000568;
rand_r = 0x4000056c;
rand = 0x40000570;
srand = 0x40000574;
utoa = 0x40000578;
itoa = 0x4000057c;
atoi = 0x40000580;
atol = 0x40000584;
strtol = 0x40000588;
strtoul = 0x4000058c;
fflush = 0x40000590;
_fflush_r = 0x40000594;
_fwalk = 0x40000598;
_fwalk_reent = 0x4000059c;
__smakebuf_r = 0x400005a0;
__swhatbuf_r = 0x400005a4;
__swbuf_r = 0x400005a8;
__swbuf = 0x400005ac;
__swsetup_r = 0x400005b0;
_strtod_l = 0x400005b4;
_strtod_r = 0x400005b8;
strtod_l = 0x400005bc;
strtod = 0x400005c0;
strtof_l = 0x400005c4;
strtof = 0x400005c8;
_strtol_r = 0x400005cc;
strtol_l = 0x400005d0;
_strtoul_r = 0x400005d4;
strtoul_l = 0x400005d8;
__match = 0x400005dc;
__hexnan = 0x400005e0;
__hexdig_fun = 0x400005e4;
__gethex = 0x400005e8;
_Balloc = 0x400005ec;
_Bfree = 0x400005f0;
__multadd = 0x400005f4;
__s2b = 0x400005f8;
__hi0bits = 0x400005fc;
__lo0bits = 0x40000600;
__i2b = 0x40000604;
__multiply = 0x40000608;
__pow5mult = 0x4000060c;
__lshift = 0x40000610;
__mcmp = 0x40000614;
__mdiff = 0x40000618;
__ulp = 0x4000061c;
__b2d = 0x40000620;
__d2b = 0x40000624;
__ratio = 0x40000628;
_mprec_log10 = 0x4000062c;
__copybits = 0x40000630;
__any_on = 0x40000634;
asctime = 0x40000638;
asctime_r = 0x4000063c;
atof = 0x40000640;
atoff = 0x40000644;
_dtoa_r = 0x40000648;
_wctomb_r = 0x4000064c;
__ascii_wctomb = 0x40000650;
_mbtowc_r = 0x40000654;
__ascii_mbtowc = 0x40000658;
puts = 0x4000065c;
putc = 0x40000660;
putchar = 0x40000664;
nan = 0x40000668;
nanf = 0x4000066c;
__errno = 0x40000670;
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffdc;
_global_impure_ptr = 0x3fcdffd8;
syscall_table_ptr = 0x3fcdffd8;
_global_impure_ptr = 0x3fcdffd4;

6
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld
View File

@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM version variables for esp32h2
*
* These addresses should be compatible with any ROM version for this chip.

4
components/esp_system/Kconfig
View File

@ -83,8 +83,8 @@ menu "ESP System Settings"
default y if IDF_TARGET_ESP32S2
default y if IDF_TARGET_ESP32C3
default y if IDF_TARGET_ESP32S3
default y if IDF_TARGET_ESP32H2
depends on !IDF_TARGET_ESP8684
default y if IDF_TARGET_ESP32H2_BETA_VERSION_1
depends on !IDF_TARGET_ESP8684 && !IDF_TARGET_ESP32H2_BETA_VERSION_2
config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
bool "Enable RTC fast memory for dynamic allocations"

26
components/esp_system/port/soc/esp32h2/system_internal.c
View File

@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "sdkconfig.h"
@ -95,7 +87,15 @@ void IRAM_ATTR esp_restart_noos(void)
// Reset timer/spi/uart
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
SET_PERI_REG_MASK(SYSTEM_MODEM_RST_EN_REG,
SYSTEM_IEEE802154BB_RST | SYSTEM_IEEE802154MAC_RST |
SYSTEM_BT_RST | SYSTEM_BTMAC_RST |
SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST
);
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
REG_WRITE(SYSTEM_MODEM_RST_EN_REG, 0);
// Reset dma
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);

2
components/esptool_py/Kconfig.projbuild
View File

@ -2,7 +2,7 @@ menu "Serial flasher config"
config ESPTOOLPY_NO_STUB
bool "Disable download stub"
default "y" if IDF_TARGET="esp32h2"
default "y" if IDF_TARGET_ESP32H2 && IDF_ENV_FPGA # TODO: IDF-4288
default "n"
help

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit 2b3221f9f24bacd982e025dc67f25dea956366bf
Subproject commit 8227361c9cda8f07c9b505b3b665ae69bc2fda8f

8
components/esptool_py/project_include.cmake
View File

@ -6,6 +6,14 @@ idf_build_get_property(python PYTHON)
idf_build_get_property(idf_path IDF_PATH)
set(chip_model ${target})
# TODO: remove this if block when esp32h2 beta1 is no longer supported
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
set(chip_model esp32h2beta1)
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
set(chip_model esp32h2beta2)
endif()
endif()
set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model})
set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py")

4
components/soc/esp32h2/CMakeLists.txt
View File

@ -19,9 +19,9 @@ target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
set(inc_file "include/soc/rev1")
set(inc_file "include/rev1" "include/rev1/soc")
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
set(inc_file "include/soc/rev2")
set(inc_file "include/rev2" "include/rev2/soc")
endif()
target_include_directories(${COMPONENT_LIB} PUBLIC . include ${inc_file})
else()

2
components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h → components/soc/esp32h2/include/rev1/soc/assist_debug_reg.h
View File

@ -6,11 +6,11 @@
#ifndef _SOC_ASSIST_DEBUG_REG_H_
#define _SOC_ASSIST_DEBUG_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */

20
components/soc/esp32h2/include/soc/gpio_reg.h → components/soc/esp32h2/include/rev1/soc/gpio_reg.h
View File

@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_REG_H_
#define _SOC_GPIO_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_PIN_CONFIG_MSB 12
#define GPIO_PIN_CONFIG_LSB 11
#define GPIO_PIN_CONFIG_MASK 0x00001800

2
components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h → components/soc/esp32h2/include/rev1/soc/gpio_sd_reg.h
View File

@ -6,11 +6,11 @@
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */

18
components/soc/esp32h2/include/soc/gpio_sig_map.h → components/soc/esp32h2/include/rev1/soc/gpio_sig_map.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_

2
components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h → components/soc/esp32h2/include/rev1/soc/interrupt_core0_reg.h
View File

@ -6,11 +6,11 @@
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE

2
components/soc/esp32h2/include/soc/rev1/io_mux_reg.h → components/soc/esp32h2/include/rev1/soc/io_mux_reg.h
View File

@ -6,7 +6,7 @@
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#include "soc.h"
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */

2
components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h → components/soc/esp32h2/include/rev1/soc/rtc_cntl_reg.h
View File

@ -21,11 +21,11 @@
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG

0
components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h → components/soc/esp32h2/include/rev1/soc/rtc_cntl_struct.h
View File

2
components/soc/esp32h2/include/soc/rev1/sensitive_reg.h → components/soc/esp32h2/include/rev1/soc/sensitive_reg.h
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@ -6,11 +6,11 @@
#ifndef _SOC_SENSITIVE_REG_H_
#define _SOC_SENSITIVE_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000)
/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */

10
components/soc/esp32h2/include/soc/soc_caps.h → components/soc/esp32h2/include/rev1/soc/soc_caps.h
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@ -1,10 +1,14 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
#pragma once
#include "sdkconfig.h"
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CPU_CORES_NUM 1
@ -80,11 +84,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#define SOC_GPIO_PIN_COUNT (26)
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#define SOC_GPIO_PIN_COUNT (22)
#endif
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.

2
components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h → components/soc/esp32h2/include/rev2/soc/assist_debug_reg.h
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@ -6,11 +6,11 @@
#ifndef _SOC_ASSIST_DEBUG_REG_H_
#define _SOC_ASSIST_DEBUG_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */

4861
components/soc/esp32h2/include/rev2/soc/gpio_reg.h Normal file
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File diff suppressed because it is too large Load Diff

2
components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h → components/soc/esp32h2/include/rev2/soc/gpio_sd_reg.h
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@ -6,11 +6,11 @@
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */

186
components/soc/esp32h2/include/rev2/soc/gpio_sig_map.h Normal file
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@ -0,0 +1,186 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_IDX 4
#define SPICS0_OUT_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define I2S_MCLK_IN_IDX 12
#define I2S_MCLK_OUT_IDX 12
#define I2SO_BCK_IN_IDX 13
#define I2SO_BCK_OUT_IDX 13
#define I2SO_WS_IN_IDX 14
#define I2SO_WS_OUT_IDX 14
#define I2SI_SD_IN_IDX 15
#define I2SO_SD_OUT_IDX 15
#define I2SI_BCK_IN_IDX 16
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define I2SO_SD1_OUT_IDX 18
#define CPU_TESTBUS0_IDX 20
#define CPU_TESTBUS1_IDX 21
#define CPU_TESTBUS2_IDX 22
#define CPU_TESTBUS3_IDX 23
#define CPU_TESTBUS4_IDX 24
#define CPU_TESTBUS5_IDX 25
#define CPU_TESTBUS6_IDX 26
#define CPU_TESTBUS7_IDX 27
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_IDX 36
#define USB_JTAG_TMS_IDX 37
#define USB_JTAG_TDI_IDX 38
#define USB_JTAG_TDO_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
#define USB_EXTPHY_SPEED_IDX 41
#define USB_EXTPHY_RCV_IDX 42
#define USB_EXTPHY_VPO_IDX 42
#define USB_EXTPHY_VMO_IDX 43
#define USB_EXTPHY_SUSPND_IDX 44
#define EXT_ADC_START_IDX 45
#define LEDC_LS_SIG_OUT0_IDX 45
#define LEDC_LS_SIG_OUT1_IDX 46
#define LEDC_LS_SIG_OUT2_IDX 47
#define LEDC_LS_SIG_OUT3_IDX 48
#define LEDC_LS_SIG_OUT4_IDX 49
#define LEDC_LS_SIG_OUT5_IDX 50
#define RMT_SIG_IN0_IDX 51
#define RMT_SIG_OUT0_IDX 51
#define RMT_SIG_IN1_IDX 52
#define RMT_SIG_OUT1_IDX 52
#define I2CEXT0_SCL_IN_IDX 53
#define I2CEXT0_SCL_OUT_IDX 53
#define I2CEXT0_SDA_IN_IDX 54
#define I2CEXT0_SDA_OUT_IDX 54
#define GPIO_SD0_OUT_IDX 55
#define GPIO_SD1_OUT_IDX 56
#define GPIO_SD2_OUT_IDX 57
#define GPIO_SD3_OUT_IDX 58
#define EVENT_MATRIX_IN0_IDX 59
#define TASK_MATRIX_OUT0_IDX 59
#define EVENT_MATRIX_IN1_IDX 60
#define TASK_MATRIX_OUT1_IDX 60
#define EVENT_MATRIX_IN2_IDX 61
#define TASK_MATRIX_OUT2_IDX 61
#define EVENT_MATRIX_IN3_IDX 62
#define TASK_MATRIX_OUT3_IDX 62
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_IDX 63
#define FSPIQ_IN_IDX 64
#define FSPIQ_OUT_IDX 64
#define FSPID_IN_IDX 65
#define FSPID_OUT_IDX 65
#define FSPIHD_IN_IDX 66
#define FSPIHD_OUT_IDX 66
#define FSPIWP_IN_IDX 67
#define FSPIWP_OUT_IDX 67
#define FSPICS0_IN_IDX 68
#define FSPICS0_OUT_IDX 68
#define FSPICS1_OUT_IDX 69
#define FSPICS2_OUT_IDX 70
#define FSPICS3_OUT_IDX 71
#define FSPICS4_OUT_IDX 72
#define FSPICS5_OUT_IDX 73
#define TWAI_RX_IDX 74
#define TWAI_TX_IDX 74
#define TWAI_BUS_OFF_ON_IDX 75
#define TWAI_CLKOUT_IDX 76
#define PCMFSYNC_IN_IDX 77
#define PCMFSYNC_OUT_IDX 77
#define PCMCLK_IN_IDX 78
#define PCMCLK_OUT_IDX 78
#define PCMDIN_IDX 79
#define PCMDOUT_IDX 79
#define CO_EXT_PRIORITY_IN_IDX 80
#define CO_EXT_PRIORITY_OUT_IDX 80
#define CO_EXT_ACTIVE_IN_IDX 81
#define CO_EXT_ACTIVE_OUT_IDX 81
#define MODEM_COEX_GRANT1_IDX 87
#define MODEM_COEX_GRANT2_IDX 88
#define ANT_SEL0_IDX 89
#define ANT_SEL1_IDX 90
#define ANT_SEL2_IDX 91
#define ANT_SEL3_IDX 92
#define ANT_SEL4_IDX 93
#define ANT_SEL5_IDX 94
#define ANT_SEL6_IDX 95
#define ANT_SEL7_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define SYNCERR_IDX 101
#define SYNC_FOUND_IDX 102
#define CH_IDX_IDX 103
#define SYNC_WINDOW_IDX 104
#define DATA_EN_IDX 105
#define DATA_IDX 106
#define PKT_TX_ON_IDX 107
#define PKT_RX_ON_IDX 108
#define TXRU_ON_IDX 109
#define RXRU_ON_IDX 110
#define LELC_ST3_IDX 111
#define LELC_ST2_IDX 112
#define LELC_ST1_IDX 113
#define LELC_ST0_IDX 114
#define CRCOK_IDX 115
#define CLK_GPIO_IDX 116
#define RADIO_START_IDX 117
#define SEQUENCE_ON_IDX 118
#define PUMP_CLK_IDX 119
#define PUMP_XPD_IDX 120
#define PUMP_DRV1_IDX 121
#define PUMP_DRV0_IDX 122
#define CLK_OUT_OUT1_IDX 123
#define CLK_OUT_OUT2_IDX 124
#define CLK_OUT_OUT3_IDX 125
#define SPICS1_OUT_IDX 126
#define USB_JTAG_TRST_IDX 127
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2109090
#endif /* _SOC_GPIO_SIG_MAP_H_ */

2
components/soc/esp32h2/include/soc/rev2/interrupt_core0_reg.h → components/soc/esp32h2/include/rev2/soc/interrupt_core0_reg.h
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@ -6,11 +6,11 @@
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE

2
components/soc/esp32h2/include/soc/rev2/io_mux_reg.h → components/soc/esp32h2/include/rev2/soc/io_mux_reg.h
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@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
#include "soc/soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */

2
components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h → components/soc/esp32h2/include/rev2/soc/rtc_cntl_reg.h
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@ -21,11 +21,11 @@
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG

3
components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h → components/soc/esp32h2/include/rev2/soc/rtc_cntl_struct.h
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@ -10,9 +10,8 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s{
union {
struct {
uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/

2
components/soc/esp32h2/include/soc/rev2/sensitive_reg.h → components/soc/esp32h2/include/rev2/soc/sensitive_reg.h
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@ -6,11 +6,11 @@
#ifndef _SOC_SENSITIVE_REG_H_
#define _SOC_SENSITIVE_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0)
/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */

271
components/soc/esp32h2/include/rev2/soc/soc_caps.h Normal file
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@ -0,0 +1,271 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CPU_CORES_NUM 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_AES_GDMA (1)
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- ADC CAPS -------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (26)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_AUTO_ENABLE (1) /*!< The dedicated GPIO peripheral is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_CODEC (1)
#define SOC_I2S_SUPPORTS_TDM (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
/*-------------------------- MPU CAPS ----------------------------------------*/
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
/*-------------------------- RTC CAPS --------------------------------------*/
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-H2 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_BT_PD (1)

13
components/soc/esp32h2/include/soc/rtc.h
View File

@ -146,19 +146,6 @@ typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
/**
* @brief CPU frequency values
*/
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
} rtc_cpu_freq_t;
#endif
/**
* @brief CPU clock source
*/

4
tools/ci/check_copyright_ignore.txt
View File

@ -934,7 +934,6 @@ components/esp_system/port/soc/esp32h2/apb_backup_dma.c
components/esp_system/port/soc/esp32h2/cache_err_int.c
components/esp_system/port/soc/esp32h2/cache_err_int.h
components/esp_system/port/soc/esp32h2/reset_reason.c
components/esp_system/port/soc/esp32h2/system_internal.c
components/esp_system/port/soc/esp32s2/cache_err_int.c
components/esp_system/port/soc/esp32s2/cache_err_int.h
components/esp_system/port/soc/esp32s2/reset_reason.c
@ -1948,7 +1947,6 @@ components/soc/esp32c3/sigmadelta_periph.c
components/soc/esp32c3/spi_periph.c
components/soc/esp32c3/uart_periph.c
components/soc/esp32h2/adc_periph.c
components/soc/esp32h2/gpio_periph.c
components/soc/esp32h2/gdma_periph.c
components/soc/esp32h2/i2c_periph.c
components/soc/esp32h2/i2s_periph.c
@ -1967,10 +1965,8 @@ components/soc/esp32h2/include/soc/efuse_struct.h
components/soc/esp32h2/include/soc/extmem_reg.h
components/soc/esp32h2/include/soc/fe_reg.h
components/soc/esp32h2/include/soc/gpio_pins.h
components/soc/esp32h2/include/soc/gpio_reg.h
components/soc/esp32h2/include/soc/gpio_sd_reg.h
components/soc/esp32h2/include/soc/gpio_sd_struct.h
components/soc/esp32h2/include/soc/gpio_sig_map.h
components/soc/esp32h2/include/soc/gpio_struct.h
components/soc/esp32h2/include/soc/hwcrypto_reg.h
components/soc/esp32h2/include/soc/i2c_reg.h