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822 FPGA rnv init

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This commit is contained in:
wuzhenghui 2021-09-02 20:48:39 +08:00 committed by laokaiyao
parent b9a84b96ce
commit 968c42d88c
30 changed files with 9776 additions and 882 deletions
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1
Kconfig
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@ -11,6 +11,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_ENV_FPGA
# This option is for internal use only
bool
default "y" if IDF_TARGET_ESP32H2_BETA_VERSION_2 # ESP32H2-TODO: IDF-3378
option env="IDF_ENV_FPGA"
config IDF_TARGET_ARCH_RISCV

4
components/esp_hw_support/port/esp32h2/rtc_clk_init.c
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@ -43,7 +43,11 @@ void rtc_clk_init(rtc_clk_config_t cfg)
* - CK8M_DFREQ value controls tuning of 8M clock.
* CLK_8M_DFREQ constant gives the best temperature characteristics.
*/
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
#endif
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
/* enable modem clk */

5
components/esp_hw_support/port/esp32h2/rtc_init.c
View File

@ -80,8 +80,13 @@ void rtc_init(rtc_config_t cfg)
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
}
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REGULATOR_REG, RTC_CNTL_DBOOST_FORCE_PU);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
#endif
// clear i2c_reset_protect pd force, need tested in low temperature.
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD);

70
components/esp_hw_support/port/esp32h2/rtc_sleep.c
View File

@ -75,7 +75,33 @@ void dcdc_ctl(uint32_t mode)
void regulator_set(regulator_cfg_t cfg)
{
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
// DIG REGULATOR0
if (cfg.dig_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
}
// DIG REGULATOR1
if (cfg.dig_regul1_en) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
}
// RTC REGULATOR0
if (cfg.rtc_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 0);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1);
}
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
// DIG REGULATOR0
if (cfg.dig_regul0_en) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_DIGULATOR_REG, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
@ -99,11 +125,30 @@ void regulator_set(regulator_cfg_t cfg)
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, 0);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PD, 1);
}
#endif
}
void regulator_slt(regulator_config_t regula_cfg)
{
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
// dig regulator
if (regula_cfg.dig_source == 1) {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
}
// rtc regulator
if (regula_cfg.rtc_source == 1) {
REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
} else {
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
}
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
// dig regulator
if (regula_cfg.dig_source == 1) {
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
REG_SET_FIELD(RTC_CNTL_DIGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
@ -119,13 +164,20 @@ void regulator_slt(regulator_config_t regula_cfg)
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
REG_SET_FIELD(RTC_CNTL_RTCULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
}
#endif
}
void dbias_switch_set(dbias_swt_cfg_t cfg)
{
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
#endif
}
void left_up_trx_fpu(bool fpu)
@ -186,7 +238,24 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
// ESP32-H2 TO-DO: IDF-3693
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
if (cfg.deep_slp) {
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
// SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
if (cfg.deep_slp) {
// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
// CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
@ -201,6 +270,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
// SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
}
#endif
/* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);

BIN
components/esp_rom/eagle.pro.rom.out Executable file
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Binary file not shown.

1130
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.ld
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File diff suppressed because it is too large Load Diff

184
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.libgcc.ld
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@ -1,7 +1,7 @@
/* ROM function interface esp32b1z.rom.libgcc.ld for esp32b1z
/* ROM function interface esp32h2.rom.libgcc.ld for esp32h2
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
* Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,93 +13,93 @@
***************************************/
/* Functions */
__absvdi2 = 0x40000770;
__absvsi2 = 0x40000774;
__adddf3 = 0x40000778;
__addsf3 = 0x4000077c;
__addvdi3 = 0x40000780;
__addvsi3 = 0x40000784;
__ashldi3 = 0x40000788;
__ashrdi3 = 0x4000078c;
__bswapdi2 = 0x40000790;
__bswapsi2 = 0x40000794;
__clear_cache = 0x40000798;
__clrsbdi2 = 0x4000079c;
__clrsbsi2 = 0x400007a0;
__clzdi2 = 0x400007a4;
__clzsi2 = 0x400007a8;
__cmpdi2 = 0x400007ac;
__ctzdi2 = 0x400007b0;
__ctzsi2 = 0x400007b4;
__divdc3 = 0x400007b8;
__divdf3 = 0x400007bc;
__divdi3 = 0x400007c0;
__divsc3 = 0x400007c4;
__divsf3 = 0x400007c8;
__divsi3 = 0x400007cc;
__eqdf2 = 0x400007d0;
__eqsf2 = 0x400007d4;
__extendsfdf2 = 0x400007d8;
__ffsdi2 = 0x400007dc;
__ffssi2 = 0x400007e0;
__fixdfdi = 0x400007e4;
__fixdfsi = 0x400007e8;
__fixsfdi = 0x400007ec;
__fixsfsi = 0x400007f0;
__fixunsdfsi = 0x400007f4;
__fixunssfdi = 0x400007f8;
__fixunssfsi = 0x400007fc;
__floatdidf = 0x40000800;
__floatdisf = 0x40000804;
__floatsidf = 0x40000808;
__floatsisf = 0x4000080c;
__floatundidf = 0x40000810;
__floatundisf = 0x40000814;
__floatunsidf = 0x40000818;
__floatunsisf = 0x4000081c;
__gcc_bcmp = 0x40000820;
__gedf2 = 0x40000824;
__gesf2 = 0x40000828;
__gtdf2 = 0x4000082c;
__gtsf2 = 0x40000830;
__ledf2 = 0x40000834;
__lesf2 = 0x40000838;
__lshrdi3 = 0x4000083c;
__ltdf2 = 0x40000840;
__ltsf2 = 0x40000844;
__moddi3 = 0x40000848;
__modsi3 = 0x4000084c;
__muldc3 = 0x40000850;
__muldf3 = 0x40000854;
__muldi3 = 0x40000858;
__mulsc3 = 0x4000085c;
__mulsf3 = 0x40000860;
__mulsi3 = 0x40000864;
__mulvdi3 = 0x40000868;
__mulvsi3 = 0x4000086c;
__nedf2 = 0x40000870;
__negdf2 = 0x40000874;
__negdi2 = 0x40000878;
__negsf2 = 0x4000087c;
__negvdi2 = 0x40000880;
__negvsi2 = 0x40000884;
__nesf2 = 0x40000888;
__paritysi2 = 0x4000088c;
__popcountdi2 = 0x40000890;
__popcountsi2 = 0x40000894;
__powidf2 = 0x40000898;
__powisf2 = 0x4000089c;
__subdf3 = 0x400008a0;
__subsf3 = 0x400008a4;
__subvdi3 = 0x400008a8;
__subvsi3 = 0x400008ac;
__truncdfsf2 = 0x400008b0;
__ucmpdi2 = 0x400008b4;
__udivdi3 = 0x400008b8;
__udivmoddi4 = 0x400008bc;
__udivsi3 = 0x400008c0;
__udiv_w_sdiv = 0x400008c4;
__umoddi3 = 0x400008c8;
__umodsi3 = 0x400008cc;
__unorddf2 = 0x400008d0;
__unordsf2 = 0x400008d4;
__absvdi2 = 0x40000738;
__absvsi2 = 0x4000073c;
__adddf3 = 0x40000740;
__addsf3 = 0x40000744;
__addvdi3 = 0x40000748;
__addvsi3 = 0x4000074c;
__ashldi3 = 0x40000750;
__ashrdi3 = 0x40000754;
__bswapdi2 = 0x40000758;
__bswapsi2 = 0x4000075c;
__clear_cache = 0x40000760;
__clrsbdi2 = 0x40000764;
__clrsbsi2 = 0x40000768;
__clzdi2 = 0x4000076c;
__clzsi2 = 0x40000770;
__cmpdi2 = 0x40000774;
__ctzdi2 = 0x40000778;
__ctzsi2 = 0x4000077c;
__divdc3 = 0x40000780;
__divdf3 = 0x40000784;
__divdi3 = 0x40000788;
__divsc3 = 0x4000078c;
__divsf3 = 0x40000790;
__divsi3 = 0x40000794;
__eqdf2 = 0x40000798;
__eqsf2 = 0x4000079c;
__extendsfdf2 = 0x400007a0;
__ffsdi2 = 0x400007a4;
__ffssi2 = 0x400007a8;
__fixdfdi = 0x400007ac;
__fixdfsi = 0x400007b0;
__fixsfdi = 0x400007b4;
__fixsfsi = 0x400007b8;
__fixunsdfsi = 0x400007bc;
__fixunssfdi = 0x400007c0;
__fixunssfsi = 0x400007c4;
__floatdidf = 0x400007c8;
__floatdisf = 0x400007cc;
__floatsidf = 0x400007d0;
__floatsisf = 0x400007d4;
__floatundidf = 0x400007d8;
__floatundisf = 0x400007dc;
__floatunsidf = 0x400007e0;
__floatunsisf = 0x400007e4;
__gcc_bcmp = 0x400007e8;
__gedf2 = 0x400007ec;
__gesf2 = 0x400007f0;
__gtdf2 = 0x400007f4;
__gtsf2 = 0x400007f8;
__ledf2 = 0x400007fc;
__lesf2 = 0x40000800;
__lshrdi3 = 0x40000804;
__ltdf2 = 0x40000808;
__ltsf2 = 0x4000080c;
__moddi3 = 0x40000810;
__modsi3 = 0x40000814;
__muldc3 = 0x40000818;
__muldf3 = 0x4000081c;
__muldi3 = 0x40000820;
__mulsc3 = 0x40000824;
__mulsf3 = 0x40000828;
__mulsi3 = 0x4000082c;
__mulvdi3 = 0x40000830;
__mulvsi3 = 0x40000834;
__nedf2 = 0x40000838;
__negdf2 = 0x4000083c;
__negdi2 = 0x40000840;
__negsf2 = 0x40000844;
__negvdi2 = 0x40000848;
__negvsi2 = 0x4000084c;
__nesf2 = 0x40000850;
__paritysi2 = 0x40000854;
__popcountdi2 = 0x40000858;
__popcountsi2 = 0x4000085c;
__powidf2 = 0x40000860;
__powisf2 = 0x40000864;
__subdf3 = 0x40000868;
__subsf3 = 0x4000086c;
__subvdi3 = 0x40000870;
__subvsi3 = 0x40000874;
__truncdfsf2 = 0x40000878;
__ucmpdi2 = 0x4000087c;
__udivdi3 = 0x40000880;
__udivmoddi4 = 0x40000884;
__udivsi3 = 0x40000888;
__udiv_w_sdiv = 0x4000088c;
__umoddi3 = 0x40000890;
__umodsi3 = 0x40000894;
__unorddf2 = 0x40000898;
__unordsf2 = 0x4000089c;

28
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib-nano.ld
View File

@ -1,7 +1,7 @@
/* ROM function interface esp32b1z.rom.newlib-nano.ld for esp32b1z
/* ROM function interface esp32h2.rom.newlib-nano.ld for esp32h2
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
* Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,15 +13,15 @@
***************************************/
/* Functions */
__sprint_r = 0x40000488;
_fiprintf_r = 0x4000048c;
_fprintf_r = 0x40000490;
_printf_common = 0x40000494;
_printf_i = 0x40000498;
_vfiprintf_r = 0x4000049c;
_vfprintf_r = 0x400004a0;
fiprintf = 0x400004a4;
fprintf = 0x400004a8;
printf = 0x400004ac;
vfiprintf = 0x400004b0;
vfprintf = 0x400004b4;
__sprint_r = 0x4000044c;
_fiprintf_r = 0x40000450;
_fprintf_r = 0x40000454;
_printf_common = 0x40000458;
_printf_i = 0x4000045c;
_vfiprintf_r = 0x40000460;
_vfprintf_r = 0x40000464;
fiprintf = 0x40000468;
fprintf = 0x4000046c;
printf = 0x40000470;
vfiprintf = 0x40000474;
vfprintf = 0x40000478;

156
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.newlib.ld
View File

@ -1,7 +1,7 @@
/* ROM function interface esp32b1z.rom.newlib.ld for esp32b1z
/* ROM function interface esp32h2.rom.newlib.ld for esp32h2
*
*
* Generated from ./interface-esp32b1z.yml md5sum a8cce65aa1422e5781ad0d729ef0a0a6
* Generated from ./interface-esp32h2.yml md5sum 47e064f8d2b991d372a72a89ab7d47d3
*
* Compatible with ROM where ECO version equal or greater to 0.
*
@ -13,82 +13,82 @@
***************************************/
/* Functions */
esp_rom_newlib_init_common_mutexes = 0x40000358;
memset = 0x4000035c;
memcpy = 0x40000360;
memmove = 0x40000364;
memcmp = 0x40000368;
strcpy = 0x4000036c;
strncpy = 0x40000370;
strcmp = 0x40000374;
strncmp = 0x40000378;
strlen = 0x4000037c;
strstr = 0x40000380;
bzero = 0x40000384;
_isatty_r = 0x40000388;
sbrk = 0x4000038c;
isalnum = 0x40000390;
isalpha = 0x40000394;
isascii = 0x40000398;
isblank = 0x4000039c;
iscntrl = 0x400003a0;
isdigit = 0x400003a4;
islower = 0x400003a8;
isgraph = 0x400003ac;
isprint = 0x400003b0;
ispunct = 0x400003b4;
isspace = 0x400003b8;
isupper = 0x400003bc;
toupper = 0x400003c0;
tolower = 0x400003c4;
toascii = 0x400003c8;
memccpy = 0x400003cc;
memchr = 0x400003d0;
memrchr = 0x400003d4;
strcasecmp = 0x400003d8;
strcasestr = 0x400003dc;
strcat = 0x400003e0;
strdup = 0x400003e4;
strchr = 0x400003e8;
strcspn = 0x400003ec;
strcoll = 0x400003f0;
strlcat = 0x400003f4;
strlcpy = 0x400003f8;
strlwr = 0x400003fc;
strncasecmp = 0x40000400;
strncat = 0x40000404;
strndup = 0x40000408;
strnlen = 0x4000040c;
strrchr = 0x40000410;
strsep = 0x40000414;
strspn = 0x40000418;
strtok_r = 0x4000041c;
strupr = 0x40000420;
longjmp = 0x40000424;
setjmp = 0x40000428;
abs = 0x4000042c;
div = 0x40000430;
labs = 0x40000434;
ldiv = 0x40000438;
qsort = 0x4000043c;
rand_r = 0x40000440;
rand = 0x40000444;
srand = 0x40000448;
utoa = 0x4000044c;
itoa = 0x40000450;
atoi = 0x40000454;
atol = 0x40000458;
strtol = 0x4000045c;
strtoul = 0x40000460;
PROVIDE( fflush = 0x40000464 );
PROVIDE( _fflush_r = 0x40000468 );
PROVIDE( _fwalk = 0x4000046c );
PROVIDE( _fwalk_reent = 0x40000470 );
PROVIDE( __smakebuf_r = 0x40000474 );
PROVIDE( __swhatbuf_r = 0x40000478 );
PROVIDE( __swbuf_r = 0x4000047c );
__swbuf = 0x40000480;
PROVIDE( __swsetup_r = 0x40000484 );
esp_rom_newlib_init_common_mutexes = 0x4000031c;
memset = 0x40000320;
memcpy = 0x40000324;
memmove = 0x40000328;
memcmp = 0x4000032c;
strcpy = 0x40000330;
strncpy = 0x40000334;
strcmp = 0x40000338;
strncmp = 0x4000033c;
strlen = 0x40000340;
strstr = 0x40000344;
bzero = 0x40000348;
_isatty_r = 0x4000034c;
sbrk = 0x40000350;
isalnum = 0x40000354;
isalpha = 0x40000358;
isascii = 0x4000035c;
isblank = 0x40000360;
iscntrl = 0x40000364;
isdigit = 0x40000368;
islower = 0x4000036c;
isgraph = 0x40000370;
isprint = 0x40000374;
ispunct = 0x40000378;
isspace = 0x4000037c;
isupper = 0x40000380;
toupper = 0x40000384;
tolower = 0x40000388;
toascii = 0x4000038c;
memccpy = 0x40000390;
memchr = 0x40000394;
memrchr = 0x40000398;
strcasecmp = 0x4000039c;
strcasestr = 0x400003a0;
strcat = 0x400003a4;
strdup = 0x400003a8;
strchr = 0x400003ac;
strcspn = 0x400003b0;
strcoll = 0x400003b4;
strlcat = 0x400003b8;
strlcpy = 0x400003bc;
strlwr = 0x400003c0;
strncasecmp = 0x400003c4;
strncat = 0x400003c8;
strndup = 0x400003cc;
strnlen = 0x400003d0;
strrchr = 0x400003d4;
strsep = 0x400003d8;
strspn = 0x400003dc;
strtok_r = 0x400003e0;
strupr = 0x400003e4;
longjmp = 0x400003e8;
setjmp = 0x400003ec;
abs = 0x400003f0;
div = 0x400003f4;
labs = 0x400003f8;
ldiv = 0x400003fc;
qsort = 0x40000400;
rand_r = 0x40000404;
rand = 0x40000408;
srand = 0x4000040c;
utoa = 0x40000410;
itoa = 0x40000414;
atoi = 0x40000418;
atol = 0x4000041c;
strtol = 0x40000420;
strtoul = 0x40000424;
PROVIDE( fflush = 0x40000428 );
PROVIDE( _fflush_r = 0x4000042c );
PROVIDE( _fwalk = 0x40000430 );
PROVIDE( _fwalk_reent = 0x40000434 );
PROVIDE( __smakebuf_r = 0x40000438 );
PROVIDE( __swhatbuf_r = 0x4000043c );
PROVIDE( __swbuf_r = 0x40000440 );
__swbuf = 0x40000444;
PROVIDE( __swsetup_r = 0x40000448 );
/* Data (.data, .bss, .rodata) */
syscall_table_ptr = 0x3fcdffdc;
_global_impure_ptr = 0x3fcdffd8;

2
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.version.ld
View File

@ -1,4 +1,4 @@
/* ROM version variables for esp32b1z
/* ROM version variables for esp32h2
*
* These addresses should be compatible with any ROM version for this chip.
*

2
components/esptool_py/Kconfig.projbuild
View File

@ -2,7 +2,9 @@ menu "Serial flasher config"
config ESPTOOLPY_NO_STUB
bool "Disable download stub"
default "y" if IDF_TARGET="esp32h2"
default "n"
help
The flasher tool sends a precompiled download stub first by default. That stub allows things
like compressed downloads and more. Usually you should not need to disable that feature

12
components/soc/esp32h2/CMakeLists.txt
View File

@ -16,4 +16,14 @@ set(srcs
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
set(inc_file "include/soc/rev1")
elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
set(inc_file "include/soc/rev2")
endif()
target_include_directories(${COMPONENT_LIB} PUBLIC . include ${inc_file})
else()
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
endif()

18
components/soc/esp32h2/gpio_periph.c
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"

18
components/soc/esp32h2/include/soc/assist_debug_reg.h → components/soc/esp32h2/include/soc/rev1/assist_debug_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ASSIST_DEBUG_REG_H_
#define _SOC_ASSIST_DEBUG_REG_H_

18
components/soc/esp32h2/include/soc/gpio_sd_reg.h → components/soc/esp32h2/include/soc/rev1/gpio_sd_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_

18
components/soc/esp32h2/include/soc/interrupt_core0_reg.h → components/soc/esp32h2/include/soc/rev1/interrupt_core0_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_

18
components/soc/esp32h2/include/soc/io_mux_reg.h → components/soc/esp32h2/include/soc/rev1/io_mux_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_

18
components/soc/esp32h2/include/soc/rtc_cntl_reg.h → components/soc/esp32h2/include/soc/rev1/rtc_cntl_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_CNTL_REG_H_
#define _SOC_RTC_CNTL_REG_H_

18
components/soc/esp32h2/include/soc/rtc_cntl_struct.h → components/soc/esp32h2/include/soc/rev1/rtc_cntl_struct.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus

18
components/soc/esp32h2/include/soc/sensitive_reg.h → components/soc/esp32h2/include/soc/rev1/sensitive_reg.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENSITIVE_REG_H_
#define _SOC_SENSITIVE_REG_H_

685
components/soc/esp32h2/include/soc/rev2/assist_debug_reg.h Normal file
View File

@ -0,0 +1,685 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ASSIST_DEBUG_REG_H_
#define _SOC_ASSIST_DEBUG_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xC)
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1C)
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2C)
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3C)
/* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable CPU Pdebug function, if enable, CPU will update PdebugPC.*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x1
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable recording function, if enable, assist_debug will update PdebugPC, so you
can read it.*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x1
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4C)
/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000F
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0xFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5C)
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000F
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0xFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6C)
/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7))
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(7))
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7
/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MODE 0x0000000F
#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
#define ASSIST_DEBUG_LOG_MODE_V 0xF
#define ASSIST_DEBUG_LOG_MODE_S 3
/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_ENA 0x00000007
#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
#define ASSIST_DEBUG_LOG_ENA_V 0x7
#define ASSIST_DEBUG_LOG_ENA_S 0
#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_DATA_0_S 0
#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF
#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF
#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0
#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7C)
/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MIN_S 0
#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MAX_S 0
#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_START_S 0
#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_END_S 0
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8C)
/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (BIT(1))
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x1
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1
/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0))
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0))
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
#define ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S))
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x1
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x1
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */
/*description: Need add description.*/
#define ASSIST_DEBUG_DATE 0x0FFFFFFF
#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S))
#define ASSIST_DEBUG_DATE_V 0xFFFFFFF
#define ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_ASSIST_DEBUG_REG_H_ */

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components/soc/esp32h2/include/soc/rev2/gpio_sd_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: This field is used to set a divider value to divide APB clock..*/
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: This field is used to set a divider value to divide APB clock..*/
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: This field is used to set a divider value to divide APB clock..*/
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xC)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: This field is used to set a divider value to divide APB clock..*/
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: Clock enable bit of configuration registers for sigma delta modulation..*/
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: Reserved..*/
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: Clock enable bit of sigma delta modulation..*/
#define GPIO_FUNCTION_CLK_EN (BIT(30))
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
#define GPIO_FUNCTION_CLK_EN_V 0x1
#define GPIO_FUNCTION_CLK_EN_S 30
#define GPIO_PAD_COMP_CONFIG_REG (DR_REG_GPIO_SD_BASE + 0x28)
/* GPIO_ZERO_DET_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: Zero Detect mode select..*/
#define GPIO_ZERO_DET_MODE 0x00000003
#define GPIO_ZERO_DET_MODE_M ((GPIO_ZERO_DET_MODE_V)<<(GPIO_ZERO_DET_MODE_S))
#define GPIO_ZERO_DET_MODE_V 0x3
#define GPIO_ZERO_DET_MODE_S 4
/* GPIO_DREF_COMP : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST..*/
#define GPIO_DREF_COMP 0x00000003
#define GPIO_DREF_COMP_M ((GPIO_DREF_COMP_V)<<(GPIO_DREF_COMP_S))
#define GPIO_DREF_COMP_V 0x3
#define GPIO_DREF_COMP_S 2
/* GPIO_MODE_COMP : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: 1 to enable external reference from PAD[0]. 0 to enable internal reference, mean
while PAD[0] can be used as a regular GPIO..*/
#define GPIO_MODE_COMP (BIT(1))
#define GPIO_MODE_COMP_M (BIT(1))
#define GPIO_MODE_COMP_V 0x1
#define GPIO_MODE_COMP_S 1
/* GPIO_XPD_COMP : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: Pad compare enable bit..*/
#define GPIO_XPD_COMP (BIT(0))
#define GPIO_XPD_COMP_M (BIT(0))
#define GPIO_XPD_COMP_V 0x1
#define GPIO_XPD_COMP_S 0
#define GPIO_PAD_COMP_FILTER_REG (DR_REG_GPIO_SD_BASE + 0x2C)
/* GPIO_ZERO_DET_FILTER_CNT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Zero Detect filter cycle length.*/
#define GPIO_ZERO_DET_FILTER_CNT 0xFFFFFFFF
#define GPIO_ZERO_DET_FILTER_CNT_M ((GPIO_ZERO_DET_FILTER_CNT_V)<<(GPIO_ZERO_DET_FILTER_CNT_S))
#define GPIO_ZERO_DET_FILTER_CNT_V 0xFFFFFFFF
#define GPIO_ZERO_DET_FILTER_CNT_S 0
#define GPIO_INT_RAW_REG (DR_REG_GPIO_SD_BASE + 0x80)
/* GPIO_PAD_COMP_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: Pad compare raw interrupt.*/
#define GPIO_PAD_COMP_INT_RAW (BIT(0))
#define GPIO_PAD_COMP_INT_RAW_M (BIT(0))
#define GPIO_PAD_COMP_INT_RAW_V 0x1
#define GPIO_PAD_COMP_INT_RAW_S 0
#define GPIO_INT_ST_REG (DR_REG_GPIO_SD_BASE + 0x84)
/* GPIO_PAD_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Pad compare masked interrupt.*/
#define GPIO_PAD_COMP_INT_ST (BIT(0))
#define GPIO_PAD_COMP_INT_ST_M (BIT(0))
#define GPIO_PAD_COMP_INT_ST_V 0x1
#define GPIO_PAD_COMP_INT_ST_S 0
#define GPIO_INT_ENA_REG (DR_REG_GPIO_SD_BASE + 0x88)
/* GPIO_PAD_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Pad compare interrupt enable.*/
#define GPIO_PAD_COMP_INT_ENA (BIT(0))
#define GPIO_PAD_COMP_INT_ENA_M (BIT(0))
#define GPIO_PAD_COMP_INT_ENA_V 0x1
#define GPIO_PAD_COMP_INT_ENA_S 0
#define GPIO_INT_CLR_REG (DR_REG_GPIO_SD_BASE + 0x8C)
/* GPIO_PAD_COMP_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Pad compare interrupt clear.*/
#define GPIO_PAD_COMP_INT_CLR (BIT(0))
#define GPIO_PAD_COMP_INT_CLR_M (BIT(0))
#define GPIO_PAD_COMP_INT_CLR_V 0x1
#define GPIO_PAD_COMP_INT_CLR_S 0
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0xFC)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2109250 ; */
/*description: Version control register..*/
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIOSD_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0
#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0
#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0
#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BB_INT_MAP_S 0
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0
#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C)
/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0
#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2C)
/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0
#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0
#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3C)
/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4C)
/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_UART_INTR_MAP_S 0
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5C)
/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0
#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CAN_INT_MAP_S 0
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6C)
/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F
#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F
#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0
#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7C)
/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F
#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F
#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0
#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8C)
/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9C)
/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA0)
/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA4)
/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA8)
/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xAC)
/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB0)
/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB4)
/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB8)
/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0
#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xBC)
/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_RSA_INT_MAP_S 0
#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC0)
/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_AES_INT_MAP_S 0
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC4)
/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SHA_INT_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC8)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xCC)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD0)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD4)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD8)
/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xDC)
/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE0)
/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE4)
/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE8)
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xEC)
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF0)
/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF4)
/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF8)
/* INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG3_T0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M ((INTERRUPT_CORE0_TG3_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_T0_INT_MAP_S))
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_S 0
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xFC)
/* INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG3_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_WDT_INT_MAP_S))
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S 0
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S))
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0
#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
/* INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_M ((INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_V)<<(INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_S))
#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_S 0
#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
/* INTERRUPT_CORE0_ZIGBEEBB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_M ((INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_V)<<(INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_S))
#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_S 0
#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S))
#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_COEX_INT_MAP_S 0
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/* INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M ((INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V)<<(INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S))
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S 0
#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ECC_INT_MAP_M ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S))
#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ECC_INT_MAP_S 0
#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_2_S 0
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/* INTERRUPT_CORE0_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0))
#define INTERRUPT_CORE0_REG_CLK_EN_M (BIT(0))
#define INTERRUPT_CORE0_REG_CLK_EN_V 0x1
#define INTERRUPT_CORE0_REG_CLK_EN_S 0
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19C)
/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0)
/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4)
/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8)
/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC)
/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0)
/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4)
/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B8)
/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F
#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF
#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2011090 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
#ifdef __cplusplus
}
#endif
#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */

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components/soc/esp32h2/include/soc/rev2/io_mux_reg.h Normal file
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@ -0,0 +1,268 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_VDD_SPI_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define SPI_HD_GPIO_NUM 16
#define SPI_WP_GPIO_NUM 15
#define SPI_CS0_GPIO_NUM 13
#define SPI_CLK_GPIO_NUM 17
#define SPI_D_GPIO_NUM 18
#define SPI_Q_GPIO_NUM 14
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 20
#define MAX_GPIO_NUM 24
#define DIG_IO_HOLD_BIT_SHIFT 0
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE + 0x4)
#define FUNC_GPIO0_FSPIQ 2
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE + 0x8)
#define FUNC_GPIO1_FSPICS0 2
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xC)
#define FUNC_MTMS_FSPIWP 2
#define FUNC_MTMS_GPIO2 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x10)
#define FUNC_MTDO_FSPIHD 2
#define FUNC_MTDO_GPIO3 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14)
#define FUNC_MTCK_FSPICLK 2
#define FUNC_MTCK_GPIO4 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
#define FUNC_MTDI_FSPID 2
#define FUNC_MTDI_GPIO5 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x2C)
#define FUNC_XTAL_32K_P_GPIO10 1
#define FUNC_XTAL_32K_P_GPIO10_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x30)
#define FUNC_XTAL_32K_N_GPIO11 1
#define FUNC_XTAL_32K_N_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x38)
#define FUNC_SPICS0_GPIO13 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x3C)
#define FUNC_SPIQ_GPIO14 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x40)
#define FUNC_SPIWP_GPIO15 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x44)
#define FUNC_SPIHD_GPIO16 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x48)
#define FUNC_SPICLK_GPIO17 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x4C)
#define FUNC_SPID_GPIO18 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x50)
#define FUNC_VDD_SPI_GPIO19 1
#define FUNC_VDD_SPI_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE + 0x54)
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x58)
#define FUNC_U0RXD_GPIO21 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x5C)
#define FUNC_U0TXD_GPIO22 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x64)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE + 0x68)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0

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components/soc/esp32h2/include/soc/rev2/rtc_cntl_reg.h Normal file
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1021
components/soc/esp32h2/include/soc/rev2/rtc_cntl_struct.h Normal file
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2532
components/soc/esp32h2/include/soc/rev2/sensitive_reg.h Normal file
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31
components/soc/esp32h2/include/soc/rtc.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
@ -154,6 +146,19 @@ typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
/**
* @brief CPU frequency values
*/
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
} rtc_cpu_freq_t;
#endif
/**
* @brief CPU clock source
*/

5
components/soc/esp32h2/include/soc/soc_caps.h
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@ -4,6 +4,7 @@
// include them here.
#pragma once
#include "sdkconfig.h"
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CPU_CORES_NUM 1
@ -79,7 +80,11 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
#define SOC_GPIO_PIN_COUNT (26)
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
#define SOC_GPIO_PIN_COUNT (22)
#endif
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.

7
tools/ci/check_copyright_ignore.txt
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@ -1949,6 +1949,7 @@ components/soc/esp32c3/spi_periph.c
components/soc/esp32c3/uart_periph.c
components/soc/esp32h2/adc_periph.c
components/soc/esp32h2/gpio_periph.c
components/soc/esp32h2/gdma_periph.c
components/soc/esp32h2/i2c_periph.c
components/soc/esp32h2/i2s_periph.c
components/soc/esp32h2/include/soc/adc_channel.h
@ -1956,7 +1957,6 @@ components/soc/esp32h2/include/soc/apb_ctrl_reg.h
components/soc/esp32h2/include/soc/apb_ctrl_struct.h
components/soc/esp32h2/include/soc/apb_saradc_reg.h
components/soc/esp32h2/include/soc/apb_saradc_struct.h
components/soc/esp32h2/include/soc/assist_debug_reg.h
components/soc/esp32h2/include/soc/bb_reg.h
components/soc/esp32h2/include/soc/boot_mode.h
components/soc/esp32h2/include/soc/clkout_channel.h
@ -1977,7 +1977,6 @@ components/soc/esp32h2/include/soc/i2c_reg.h
components/soc/esp32h2/include/soc/i2c_struct.h
components/soc/esp32h2/include/soc/i2s_reg.h
components/soc/esp32h2/include/soc/i2s_struct.h
components/soc/esp32h2/include/soc/interrupt_core0_reg.h
components/soc/esp32h2/include/soc/interrupt_reg.h
components/soc/esp32h2/include/soc/io_mux_reg.h
components/soc/esp32h2/include/soc/ledc_reg.h
@ -1987,14 +1986,10 @@ components/soc/esp32h2/include/soc/periph_defs.h
components/soc/esp32h2/include/soc/reset_reasons.h
components/soc/esp32h2/include/soc/rmt_reg.h
components/soc/esp32h2/include/soc/rmt_struct.h
components/soc/esp32h2/include/soc/rtc.h
components/soc/esp32h2/include/soc/rtc_caps.h
components/soc/esp32h2/include/soc/rtc_cntl_reg.h
components/soc/esp32h2/include/soc/rtc_cntl_struct.h
components/soc/esp32h2/include/soc/rtc_i2c_reg.h
components/soc/esp32h2/include/soc/rtc_i2c_struct.h
components/soc/esp32h2/include/soc/rtc_io_caps.h
components/soc/esp32h2/include/soc/sensitive_reg.h
components/soc/esp32h2/include/soc/sensitive_struct.h
components/soc/esp32h2/include/soc/soc.h
components/soc/esp32h2/include/soc/soc_caps.h