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ESP8684: add soc, riscv, newlib support

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This commit is contained in:
Cao Sen Miao 2021-11-06 17:25:49 +08:00
parent 09487761cf
commit 36f6d16b8d
93 changed files with 35703 additions and 129 deletions
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24
components/newlib/locks.c
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/lock.h>
#include <stdlib.h>
@ -252,7 +244,7 @@ static StaticSemaphore_t s_common_mutex;
static StaticSemaphore_t s_common_recursive_mutex;
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
#if ESP_ROM_HAS_RETARGETABLE_LOCKING
/* C3 and S3 ROMs are built without Newlib static lock symbols exported, and
* with an extra level of _LOCK_T indirection in mind.
* The following is a workaround for this:
@ -267,7 +259,7 @@ static StaticSemaphore_t s_common_recursive_mutex;
*/
#define ROM_NEEDS_MUTEX_OVERRIDE
#endif // defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
#endif // ESP_ROM_HAS_RETARGETABLE_LOCKING
#ifdef ROM_NEEDS_MUTEX_OVERRIDE
#define ROM_MUTEX_MAGIC 0xbb10c433
@ -393,7 +385,7 @@ void esp_newlib_locks_init(void)
__sinit_recursive_mutex = (_lock_t) &s_common_recursive_mutex;
extern _lock_t __sfp_recursive_mutex;
__sfp_recursive_mutex = (_lock_t) &s_common_recursive_mutex;
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP8684)
/* Newlib 3.3.0 is used in ROM, built with _RETARGETABLE_LOCKING.
* No access to lock variables for the purpose of ECO forward compatibility,
* however we have an API to initialize lock variables used in the ROM.

24
components/newlib/newlib_init.c
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@ -1,16 +1,8 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <string.h>
@ -39,6 +31,8 @@
#include "esp32c3/rom/libc_stubs.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/libc_stubs.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/libc_stubs.h"
#endif
static struct _reent s_reent;
@ -115,7 +109,7 @@ static struct syscall_stub_table s_stub_table = {
._printf_float = NULL,
._scanf_float = NULL,
#endif
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
/* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM
assertion failures (as function names & source file names will be similar)
*/
@ -138,7 +132,7 @@ void esp_newlib_init(void)
syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table;
#elif CONFIG_IDF_TARGET_ESP32S2
syscall_table_ptr_pro = &s_stub_table;
#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
syscall_table_ptr = &s_stub_table;
#endif

22
components/newlib/port/esp_time_impl.c
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <time.h>
#include <sys/time.h>
@ -48,6 +40,10 @@
#include "esp32h2/rom/rtc.h"
#include "esp32h2/clk.h"
#include "esp32h2/rtc.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/rtc.h"
#include "esp_private/esp_clk.h"
#include "esp8684/rtc.h"
#endif

2
components/newlib/test/test_newlib.c
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@ -141,7 +141,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]")
#if defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_SPIRAM)
TEST_ASSERT(fn_in_rom(atoi));
TEST_ASSERT(fn_in_rom(strtol));
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2)
#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP8684)
/* S3 and C3 always use these from ROM */
TEST_ASSERT(fn_in_rom(atoi));
TEST_ASSERT(fn_in_rom(strtol));

3
components/newlib/test/test_time.c
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@ -42,6 +42,9 @@
#include "esp32h2/clk.h"
#include "esp32h2/rtc.h"
#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp_private/esp_clk.h"
#define TARGET_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP8684_DEFAULT_CPU_FREQ_MHZ
#endif
#if portNUM_PROCESSORS == 2

2
components/riscv/CMakeLists.txt
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@ -1,7 +1,7 @@
idf_build_get_property(target IDF_TARGET)
# should test arch here not target: IDF-1754
if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2")
if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2" AND NOT "${target}" STREQUAL "esp8684")
return()
endif()

5
components/riscv/include/riscv/csr.h
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@ -81,6 +81,11 @@ extern "C" {
RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
} while(0)
/*Only set PMPCFG entries*/
#define PMP_ENTRY_CFG_SET(ENTRY, CFG) do {\
RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
} while(0)
/********************************************************
Trigger Module register fields (Debug specification)
********************************************************/

6
components/soc/esp32/include/soc/soc_caps.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -63,9 +63,11 @@
#define SOC_EMAC_SUPPORTED 1
#define SOC_CPU_CORES_NUM 2
#define SOC_ULP_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_CCOMP_TIMER_SUPPORTED 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
/*-------------------------- ADC CAPS ----------------------------------------*/
/**

18
components/soc/esp32c3/include/soc/cache_memory.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_

3
components/soc/esp32c3/include/soc/soc_caps.h
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@ -22,6 +22,9 @@
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)

18
components/soc/esp32h2/include/soc/cache_memory.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_

3
components/soc/esp32h2/include/soc/soc_caps.h
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@ -19,6 +19,9 @@
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- AES CAPS -----------------------------------------*/

18
components/soc/esp32s2/include/soc/cache_memory.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_

5
components/soc/esp32s2/include/soc/soc_caps.h
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@ -39,7 +39,6 @@
#define SOC_USB_OTG_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
#define SOC_ULP_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_CCOMP_TIMER_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
@ -51,8 +50,12 @@
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- ADC CAPS ----------------------------------------*/
/*!< SAR ADC Module*/

18
components/soc/esp32s3/include/soc/cache_memory.h
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@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus

4
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -24,7 +24,6 @@
#define SOC_BT_SUPPORTED 1
#define SOC_USB_OTG_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_CCOMP_TIMER_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
@ -34,7 +33,10 @@
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_SDMMC_HOST_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1

15
components/soc/esp8684/CMakeLists.txt Normal file
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@ -0,0 +1,15 @@
set(srcs
"adc_periph.c"
"gdma_periph.c"
"gpio_periph.c"
"interrupts.c"
"spi_periph.c"
"ledc_periph.c"
"i2c_periph.c"
"uart_periph.c"
"timer_periph.c")
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
target_include_directories(${COMPONENT_LIB} PUBLIC . include)

19
components/soc/esp8684/adc_periph.c Normal file
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@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
},
/* ADC2 */
{
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
}
};

21
components/soc/esp8684/gdma_periph.c Normal file
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@ -0,0 +1,21 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gdma_periph.h"
const gdma_signal_conn_t gdma_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_GDMA_MODULE,
.pairs = {
[0] = {
.rx_irq_id = ETS_DMA_CH0_INTR_SOURCE,
.tx_irq_id = ETS_DMA_CH0_INTR_SOURCE,
},
}
}
}
};

55
components/soc/esp8684/gpio_periph.c Normal file
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@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"
const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
IO_MUX_GPIO3_REG,
IO_MUX_GPIO4_REG,
IO_MUX_GPIO5_REG,
IO_MUX_GPIO6_REG,
IO_MUX_GPIO7_REG,
IO_MUX_GPIO8_REG,
IO_MUX_GPIO9_REG,
IO_MUX_GPIO10_REG,
IO_MUX_GPIO11_REG,
IO_MUX_GPIO12_REG,
IO_MUX_GPIO13_REG,
IO_MUX_GPIO14_REG,
IO_MUX_GPIO15_REG,
IO_MUX_GPIO16_REG,
IO_MUX_GPIO17_REG,
IO_MUX_GPIO18_REG,
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
};
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
BIT(0), //GPIO0
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(5), //GPIO6
BIT(6), //GPIO7
BIT(3), //GPIO8
BIT(4), //GPIO9
BIT(0), //GPIO10
BIT(15), //GPIO11
BIT(10), //GPIO12
BIT(12), //GPIO13
BIT(8), //GPIO14
BIT(7), //GPIO15
BIT(9), //GPIO16
BIT(11), //GPIO17
BIT(1), //GPIO18
BIT(2), //GPIO19
BIT(13), //GPIO20
};

175
components/soc/esp8684/i2c_bbpll.h Normal file
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@ -0,0 +1,175 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file i2c_apll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal configuration
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
.module = PERIPH_I2C0_MODULE,
},
};

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components/soc/esp8684/include/soc/adc_channel.h Normal file
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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ADC_CHANNEL_H
#define _SOC_ADC_CHANNEL_H
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4
#define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC2_GPIO5_CHANNEL ADC2_CHANNEL_0
#define ADC2_CHANNEL_0_GPIO_NUM 5
#endif

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components/soc/esp8684/include/soc/apb_ctrl_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: reg_rst_tick_cnt.*/
#define APB_CTRL_RST_TICK_CNT (BIT(12))
#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
#define APB_CTRL_RST_TICK_CNT_V 0x1
#define APB_CTRL_RST_TICK_CNT_S 12
/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: reg_clk_en.*/
#define APB_CTRL_CLK_EN (BIT(11))
#define APB_CTRL_CLK_EN_M (BIT(11))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 11
/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: reg_clk_320m_en.*/
#define APB_CTRL_CLK_320M_EN (BIT(10))
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
#define APB_CTRL_CLK_320M_EN_V 0x1
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: reg_pre_div_cnt.*/
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
#define APB_CTRL_PRE_DIV_CNT_S 0
#define APB_CTRL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: reg_tick_enable.*/
#define APB_CTRL_TICK_ENABLE (BIT(16))
#define APB_CTRL_TICK_ENABLE_M (BIT(16))
#define APB_CTRL_TICK_ENABLE_V 0x1
#define APB_CTRL_TICK_ENABLE_S 16
/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: reg_ck8m_tick_num.*/
#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
#define APB_CTRL_CK8M_TICK_NUM_S 8
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: reg_xtal_tick_num.*/
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
#define APB_CTRL_XTAL_TICK_NUM_S 0
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8)
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: reg_clk_xtal_oen.*/
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
#define APB_CTRL_CLK_XTAL_OEN_S 10
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: reg_clk40x_bb_oen.*/
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
#define APB_CTRL_CLK40X_BB_OEN_S 9
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: reg_clk_dac_cpu_oen.*/
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: reg_clk_adc_inf_oen.*/
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: reg_clk_320m_oen.*/
#define APB_CTRL_CLK_320M_OEN (BIT(6))
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
#define APB_CTRL_CLK_320M_OEN_V 0x1
#define APB_CTRL_CLK_320M_OEN_S 6
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: reg_clk160_oen.*/
#define APB_CTRL_CLK160_OEN (BIT(5))
#define APB_CTRL_CLK160_OEN_M (BIT(5))
#define APB_CTRL_CLK160_OEN_V 0x1
#define APB_CTRL_CLK160_OEN_S 5
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: reg_clk80_oen.*/
#define APB_CTRL_CLK80_OEN (BIT(4))
#define APB_CTRL_CLK80_OEN_M (BIT(4))
#define APB_CTRL_CLK80_OEN_V 0x1
#define APB_CTRL_CLK80_OEN_S 4
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: reg_clk_bb_oen.*/
#define APB_CTRL_CLK_BB_OEN (BIT(3))
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
#define APB_CTRL_CLK_BB_OEN_V 0x1
#define APB_CTRL_CLK_BB_OEN_S 3
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: reg_clk44_oen.*/
#define APB_CTRL_CLK44_OEN (BIT(2))
#define APB_CTRL_CLK44_OEN_M (BIT(2))
#define APB_CTRL_CLK44_OEN_V 0x1
#define APB_CTRL_CLK44_OEN_S 2
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: reg_clk22_oen.*/
#define APB_CTRL_CLK22_OEN (BIT(1))
#define APB_CTRL_CLK22_OEN_M (BIT(1))
#define APB_CTRL_CLK22_OEN_V 0x1
#define APB_CTRL_CLK22_OEN_S 1
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: reg_clk20_oen.*/
#define APB_CTRL_CLK20_OEN (BIT(0))
#define APB_CTRL_CLK20_OEN_M (BIT(0))
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_bb_cfg.*/
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_S 0
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_bb_cfg_2.*/
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14)
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: reg_wifi_clk_en.*/
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_rst.*/
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: reg_peri_io_swap.*/
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
#define APB_CTRL_PERI_IO_SWAP_S 0
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: reg_ext_mem_pms_lock.*/
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace0_attr.*/
#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C)
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace1_attr.*/
#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace2_attr.*/
#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace3_attr.*/
#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_flash_ace0_addr_s.*/
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C)
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
/*description: reg_flash_ace1_addr_s.*/
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
/*description: reg_flash_ace2_addr_s.*/
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
/*description: reg_flash_ace3_addr_s.*/
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace0_size.*/
#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C)
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace1_size.*/
#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace2_size.*/
#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace3_size.*/
#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: reg_spi_mem_reject_cde.*/
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: reg_spi_mem_reject_clr.*/
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: reg_spi_mem_reject_int.*/
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C)
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_spi_mem_reject_addr.*/
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: reg_sdio_win_access_en.*/
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: reg_redcy_andor.*/
#define APB_CTRL_REDCY_ANDOR (BIT(31))
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
#define APB_CTRL_REDCY_ANDOR_V 0x1
#define APB_CTRL_REDCY_ANDOR_S 31
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: reg_redcy_sig0.*/
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_S 0
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: reg_redcy_nandor.*/
#define APB_CTRL_REDCY_NANDOR (BIT(31))
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
#define APB_CTRL_REDCY_NANDOR_V 0x1
#define APB_CTRL_REDCY_NANDOR_S 31
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: reg_redcy_sig1.*/
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: reg_freq_mem_force_pd.*/
#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7))
#define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7))
#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1
#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7
/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: reg_freq_mem_force_pu.*/
#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6))
#define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6))
#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1
#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: reg_dc_mem_force_pd.*/
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: reg_dc_mem_force_pu.*/
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: reg_pbus_mem_force_pd.*/
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: reg_pbus_mem_force_pu.*/
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reg_agc_mem_force_pd.*/
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: reg_agc_mem_force_pu.*/
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0)
/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: reg_nobypass_cpu_iso_rst.*/
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: reg_retention_link_addr.*/
#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF
#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF
#define APB_CTRL_RETENTION_LINK_ADDR_S 0
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA4)
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
hen only when have access the sram have clock.*/
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
en only when have access the rom have clock.*/
#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xA8)
/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
/*description: Set 1 to let sram power down.*/
#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
#define APB_CTRL_SRAM_POWER_DOWN_V 0xF
#define APB_CTRL_SRAM_POWER_DOWN_S 3
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set 1 to let rom power down.*/
#define APB_CTRL_ROM_POWER_DOWN 0x00000007
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
#define APB_CTRL_ROM_POWER_DOWN_V 0x7
#define APB_CTRL_ROM_POWER_DOWN_S 0
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xAC)
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
/*description: Set 1 to let sram power up.*/
#define APB_CTRL_SRAM_POWER_UP 0x0000000F
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
#define APB_CTRL_SRAM_POWER_UP_V 0xF
#define APB_CTRL_SRAM_POWER_UP_S 3
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set 1 to let rom power up.*/
#define APB_CTRL_ROM_POWER_UP 0x00000007
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
#define APB_CTRL_ROM_POWER_UP_V 0x7
#define APB_CTRL_ROM_POWER_UP_S 0
#define APB_CTRL_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xB0)
/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: reg_rnd_data.*/
#define APB_CTRL_RND_DATA 0xFFFFFFFF
#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
#define APB_CTRL_RND_DATA_V 0xFFFFFFFF
#define APB_CTRL_RND_DATA_S 0
#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xB4)
/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: reg_peri_backup_ena.*/
#define APB_CTRL_PERI_BACKUP_ENA (BIT(31))
#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31))
#define APB_CTRL_PERI_BACKUP_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_ENA_S 31
/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: reg_peri_backup_to_mem.*/
#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30))
#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30))
#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1
#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30
/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: reg_peri_backup_start.*/
#define APB_CTRL_PERI_BACKUP_START (BIT(29))
#define APB_CTRL_PERI_BACKUP_START_M (BIT(29))
#define APB_CTRL_PERI_BACKUP_START_V 0x1
#define APB_CTRL_PERI_BACKUP_START_S 29
/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
/*description: reg_peri_backup_size.*/
#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF
#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF
#define APB_CTRL_PERI_BACKUP_SIZE_S 19
/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
/*description: reg_peri_backup_tout_thres.*/
#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9
/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
/*description: reg_peri_backup_burst_limit.*/
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
/*description: reg_peri_backup_flow_err.*/
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1
#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xB8)
/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: reg_backup_apb_start_addr.*/
#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_BACKUP_APB_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xBC)
/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: reg_backup_mem_start_addr.*/
#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xC0)
/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_raw.*/
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_raw.*/
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xC4)
/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_st.*/
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_st.*/
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xC8)
/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_ena.*/
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_ena.*/
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xD0)
/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_clr.*/
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1
/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_clr.*/
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0
#define APB_CTRL_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
/*description: reg_dateVersion control.*/
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
#define APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_CTRL_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct apb_ctrl_dev_s{
union {
struct {
uint32_t pre_div : 10; /*reg_pre_div_cnt*/
uint32_t clk_320m_en : 1; /*reg_clk_320m_en*/
uint32_t clk_en : 1; /*reg_clk_en*/
uint32_t rst_tick : 1; /*reg_rst_tick_cnt*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t xtal_tick : 8; /*reg_xtal_tick_num*/
uint32_t ck8m_tick : 8; /*reg_ck8m_tick_num*/
uint32_t tick_enable : 1; /*reg_tick_enable*/
uint32_t reserved17 : 15; /*Reserved.*/
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t clk20_oen : 1; /*reg_clk20_oen*/
uint32_t clk22_oen : 1; /*reg_clk22_oen*/
uint32_t clk44_oen : 1; /*reg_clk44_oen*/
uint32_t clk_bb_oen : 1; /*reg_clk_bb_oen*/
uint32_t clk80_oen : 1; /*reg_clk80_oen*/
uint32_t clk160_oen : 1; /*reg_clk160_oen*/
uint32_t clk_320m_oen : 1; /*reg_clk_320m_oen*/
uint32_t clk_adc_inf_oen : 1; /*reg_clk_adc_inf_oen*/
uint32_t clk_dac_cpu_oen : 1; /*reg_clk_dac_cpu_oen*/
uint32_t clk40x_bb_oen : 1; /*reg_clk40x_bb_oen*/
uint32_t clk_xtal_oen : 1; /*reg_clk_xtal_oen*/
uint32_t reserved11 : 21; /*Reserved.*/
};
uint32_t val;
} clk_out_en;
uint32_t wifi_bb_cfg;
uint32_t wifi_bb_cfg_2;
uint32_t wifi_clk_en;
uint32_t wifi_rst_en;
union {
struct {
uint32_t peri_io_swap : 8; /*reg_peri_io_swap*/
uint32_t reserved8 : 24; /*Reserved.*/
};
uint32_t val;
} host_inf_sel;
union {
struct {
uint32_t ext_mem_pms_lock : 1; /*reg_ext_mem_pms_lock*/
uint32_t reserved1 : 31; /*Reserved.*/
};
uint32_t val;
} ext_mem_pms_lock;
uint32_t reserved_24;
union {
struct {
uint32_t flash_ace0_attr : 2; /*reg_flash_ace0_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr : 2; /*reg_flash_ace1_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr : 2; /*reg_flash_ace2_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr : 2; /*reg_flash_ace3_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr;
uint32_t flash_ace1_addr;
uint32_t flash_ace2_addr;
uint32_t flash_ace3_addr;
union {
struct {
uint32_t flash_ace0_size : 13; /*reg_flash_ace0_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size : 13; /*reg_flash_ace1_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size : 13; /*reg_flash_ace2_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size : 13; /*reg_flash_ace3_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace3_size;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
union {
struct {
uint32_t spi_mem_reject_int : 1; /*reg_spi_mem_reject_int*/
uint32_t spi_mem_reject_clr : 1; /*reg_spi_mem_reject_clr*/
uint32_t spi_mem_reject_cde : 5; /*reg_spi_mem_reject_cde*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr;
union {
struct {
uint32_t sdio_win_access_en : 1; /*reg_sdio_win_access_en*/
uint32_t reserved1 : 31; /*Reserved.*/
};
uint32_t val;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0 : 31; /*reg_redcy_sig0*/
uint32_t redcy_andor : 1; /*reg_redcy_andor*/
};
uint32_t val;
} redcy_sig0;
union {
struct {
uint32_t redcy_sig1 : 31; /*reg_redcy_sig1*/
uint32_t redcy_nandor : 1; /*reg_redcy_nandor*/
};
uint32_t val;
} redcy_sig1;
union {
struct {
uint32_t agc_mem_force_pu : 1; /*reg_agc_mem_force_pu*/
uint32_t agc_mem_force_pd : 1; /*reg_agc_mem_force_pd*/
uint32_t pbus_mem_force_pu : 1; /*reg_pbus_mem_force_pu*/
uint32_t pbus_mem_force_pd : 1; /*reg_pbus_mem_force_pd*/
uint32_t dc_mem_force_pu : 1; /*reg_dc_mem_force_pu*/
uint32_t dc_mem_force_pd : 1; /*reg_dc_mem_force_pd*/
uint32_t freq_mem_force_pu : 1; /*reg_freq_mem_force_pu*/
uint32_t freq_mem_force_pd : 1; /*reg_freq_mem_force_pd*/
uint32_t reserved8 : 24; /*Reserved.*/
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t retention_link_addr : 27; /*reg_retention_link_addr*/
uint32_t nobypass_cpu_iso_rst : 1; /*reg_nobypass_cpu_iso_rst*/
uint32_t reserved28 : 4; /*Reserved.*/
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t rom_clkgate_force_on : 3; /*Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock*/
uint32_t sram_clkgate_force_on : 4; /*Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down : 3; /*Set 1 to let rom power down*/
uint32_t sram_power_down : 4; /*Set 1 to let sram power down*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up : 3; /*Set 1 to let rom power up*/
uint32_t sram_power_up : 4; /*Set 1 to let sram power up*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} mem_power_up;
uint32_t rnd_data;
union {
struct {
uint32_t reserved0 : 1; /*Reserved.*/
uint32_t peri_backup_flow_err : 2; /*reg_peri_backup_flow_err*/
uint32_t reserved3 : 1; /*Reserved.*/
uint32_t peri_backup_burst_limit : 5; /*reg_peri_backup_burst_limit*/
uint32_t peri_backup_tout_thres : 10; /*reg_peri_backup_tout_thres*/
uint32_t peri_backup_size : 10; /*reg_peri_backup_size*/
uint32_t peri_backup_start : 1; /*reg_peri_backup_start*/
uint32_t peri_backup_to_mem : 1; /*reg_peri_backup_to_mem*/
uint32_t peri_backup_ena : 1; /*reg_peri_backup_ena*/
};
uint32_t val;
} peri_backup_config;
uint32_t peri_backup_addr;
uint32_t peri_backup_mem_addr;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_raw*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_raw*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_raw;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_st*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_st*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_st;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_ena*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_ena*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_ena;
uint32_t reserved_cc;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_clr*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_clr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_clr;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date;
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_CTRL_STRUCT_H_ */

638
components/soc/esp8684/include/soc/apb_saradc_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_APB_SARADC_REG_H_
#define _SOC_APB_SARADC_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
/*description: wait arbit signal stable after sar_done.*/
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks.*/
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_SARADC_XPD_SAR_FORCE_S 27
/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/
#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23))
#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR_PATT_P_CLEAR_S 23
/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */
/*description: 0 ~ 15 means length 1 ~ 16.*/
#define APB_SARADC_SAR_PATT_LEN 0x00000007
#define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
#define APB_SARADC_SAR_PATT_LEN_V 0x7
#define APB_SARADC_SAR_PATT_LEN_S 15
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider.*/
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_SARADC_SAR_CLK_DIV_S 7
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: Need add description.*/
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_V 0x1
#define APB_SARADC_SAR_CLK_GATED_S 6
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_START (BIT(1))
#define APB_SARADC_START_M (BIT(1))
#define APB_SARADC_START_V 0x1
#define APB_SARADC_START_S 1
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_START_FORCE_M (BIT(0))
#define APB_SARADC_START_FORCE_V 0x1
#define APB_SARADC_START_FORCE_S 0
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger.*/
#define APB_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_TIMER_EN_M (BIT(24))
#define APB_SARADC_TIMER_EN_V 0x1
#define APB_SARADC_TIMER_EN_S 24
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
/*description: to set saradc timer target.*/
#define APB_SARADC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
#define APB_SARADC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_TIMER_TARGET_S 12
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
#define APB_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SAR2_INV_M (BIT(10))
#define APB_SARADC_SAR2_INV_V 0x1
#define APB_SARADC_SAR2_INV_S 10
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/
#define APB_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SAR1_INV_M (BIT(9))
#define APB_SARADC_SAR1_INV_V 0x1
#define APB_SARADC_SAR1_INV_S 9
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number.*/
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_SARADC_MAX_MEAS_NUM_S 1
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_FILTER_FACTOR0 0x00000007
#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
#define APB_SARADC_FILTER_FACTOR0_V 0x7
#define APB_SARADC_FILTER_FACTOR0_S 29
/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_FILTER_FACTOR1 0x00000007
#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
#define APB_SARADC_FILTER_FACTOR1_V 0x7
#define APB_SARADC_FILTER_FACTOR1_S 26
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xC)
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: Need add description.*/
#define APB_SARADC_STANDBY_WAIT 0x000000FF
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
#define APB_SARADC_STANDBY_WAIT_V 0xFF
#define APB_SARADC_STANDBY_WAIT_S 16
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: Need add description.*/
#define APB_SARADC_RSTB_WAIT 0x000000FF
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
#define APB_SARADC_RSTB_WAIT_V 0xFF
#define APB_SARADC_RSTB_WAIT_S 8
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: Need add description.*/
#define APB_SARADC_XPD_WAIT 0x000000FF
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
#define APB_SARADC_XPD_WAIT_V 0xFF
#define APB_SARADC_XPD_WAIT_S 0
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_S 0
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_S 0
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'hffffff ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/
#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF
#define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF
#define APB_SARADC_SAR_PATT_TAB1_S 0
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1C)
/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'hffffff ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/
#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF
#define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF
#define APB_SARADC_SAR_PATT_TAB2_S 0
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31))
#define APB_SARADC1_ONETIME_SAMPLE_V 0x1
#define APB_SARADC1_ONETIME_SAMPLE_S 31
/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30))
#define APB_SARADC2_ONETIME_SAMPLE_V 0x1
#define APB_SARADC2_ONETIME_SAMPLE_S 30
/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_ONETIME_START_M (BIT(29))
#define APB_SARADC_ONETIME_START_V 0x1
#define APB_SARADC_ONETIME_START_S 29
/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */
/*description: Need add description.*/
#define APB_SARADC_ONETIME_CHANNEL 0x0000000F
#define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
#define APB_SARADC_ONETIME_CHANNEL_V 0xF
#define APB_SARADC_ONETIME_CHANNEL_S 25
/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_ONETIME_ATTEN 0x00000003
#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
#define APB_SARADC_ONETIME_ATTEN_V 0x3
#define APB_SARADC_ONETIME_ATTEN_S 23
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority.*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority.*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority.*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiterapb priority.*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant.*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller.*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller.*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller.*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: enable apb_adc1_filter.*/
#define APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_FILTER_RESET_M (BIT(31))
#define APB_SARADC_FILTER_RESET_V 0x1
#define APB_SARADC_FILTER_RESET_S 31
/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */
/*description: apb_adc1_filter_factor.*/
#define APB_SARADC_FILTER_CHANNEL0 0x0000000F
#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
#define APB_SARADC_FILTER_CHANNEL0_V 0xF
#define APB_SARADC_FILTER_CHANNEL0_S 22
/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */
/*description: Need add description.*/
#define APB_SARADC_FILTER_CHANNEL1 0x0000000F
#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
#define APB_SARADC_FILTER_CHANNEL1_V 0xF
#define APB_SARADC_FILTER_CHANNEL1_S 18
#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2C)
/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC1_DATA 0x0001FFFF
#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
#define APB_SARADC_ADC1_DATA_V 0x1FFFF
#define APB_SARADC_ADC1_DATA_S 0
#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC2_DATA 0x0001FFFF
#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
#define APB_SARADC_ADC2_DATA_S 0
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES0_LOW 0x00001FFF
#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
#define APB_SARADC_THRES0_LOW_V 0x1FFF
#define APB_SARADC_THRES0_LOW_S 18
/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES0_HIGH 0x00001FFF
#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
#define APB_SARADC_THRES0_HIGH_S 5
/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_CHANNEL 0x0000000F
#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
#define APB_SARADC_THRES0_CHANNEL_V 0xF
#define APB_SARADC_THRES0_CHANNEL_S 0
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES1_LOW 0x00001FFF
#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
#define APB_SARADC_THRES1_LOW_V 0x1FFF
#define APB_SARADC_THRES1_LOW_S 18
/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES1_HIGH 0x00001FFF
#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
#define APB_SARADC_THRES1_HIGH_S 5
/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_CHANNEL 0x0000000F
#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
#define APB_SARADC_THRES1_CHANNEL_V 0xF
#define APB_SARADC_THRES1_CHANNEL_S 0
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3C)
/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_THRES0_EN_M (BIT(31))
#define APB_SARADC_THRES0_EN_V 0x1
#define APB_SARADC_THRES0_EN_S 31
/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_THRES1_EN_M (BIT(30))
#define APB_SARADC_THRES1_EN_V 0x1
#define APB_SARADC_THRES1_EN_S 30
/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES2_EN (BIT(29))
#define APB_SARADC_THRES2_EN_M (BIT(29))
#define APB_SARADC_THRES2_EN_V 0x1
#define APB_SARADC_THRES2_EN_S 29
/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES3_EN (BIT(28))
#define APB_SARADC_THRES3_EN_M (BIT(28))
#define APB_SARADC_THRES3_EN_V 0x1
#define APB_SARADC_THRES3_EN_S 28
/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
#define APB_SARADC_THRES_ALL_EN_V 0x1
#define APB_SARADC_THRES_ALL_EN_S 27
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES0_LOW_INT_ENA_S 27
/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1
#define APB_SARADC_THRES0_LOW_INT_RAW_S 27
/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1
#define APB_SARADC_THRES1_LOW_INT_RAW_S 26
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_ST_S 29
/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_ST_S 28
/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES0_LOW_INT_ST_S 27
/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4C)
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1
#define APB_SARADC_THRES0_LOW_INT_CLR_S 27
/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1
#define APB_SARADC_THRES1_LOW_INT_CLR_S 26
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: enable apb_adc use spi_dma.*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_V 0x1
#define APB_SARADC_APB_ADC_TRANS_S 31
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: reset_apb_adc_state.*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
/*description: Set this bit to enable clk_apll.*/
#define APB_SARADC_CLK_SEL 0x00000003
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
#define APB_SARADC_CLK_SEL_V 0x3
#define APB_SARADC_CLK_SEL_S 21
/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: Need add description.*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (BIT(20))
#define APB_SARADC_CLK_EN_V 0x1
#define APB_SARADC_CLK_EN_S 20
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value.*/
#define APB_SARADC_CLKM_DIV_A 0x0000003F
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
#define APB_SARADC_CLKM_DIV_A_V 0x3F
#define APB_SARADC_CLKM_DIV_A_S 14
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
/*description: Fractional clock divider numerator value.*/
#define APB_SARADC_CLKM_DIV_B 0x0000003F
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
#define APB_SARADC_CLKM_DIV_B_V 0x3F
#define APB_SARADC_CLKM_DIV_B_S 8
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
/*description: Integral I2S clock divider value.*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
#define APB_SARADC_CLKM_DIV_NUM_S 0
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (BIT(22))
#define APB_SARADC_TSENS_PU_V 0x1
#define APB_SARADC_TSENS_PU_S 22
/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FF
#define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
#define APB_SARADC_TSENS_CLK_DIV_V 0xFF
#define APB_SARADC_TSENS_CLK_DIV_S 14
/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (BIT(13))
#define APB_SARADC_TSENS_IN_INV_V 0x1
#define APB_SARADC_TSENS_IN_INV_S 13
/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_OUT 0x000000FF
#define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
#define APB_SARADC_TSENS_OUT_V 0xFF
#define APB_SARADC_TSENS_OUT_S 0
#define APB_SARADC_ APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5C)
/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_V 0x1
#define APB_SARADC_TSENS_CLK_SEL_S 15
/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_CLK_INV (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_M (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_V 0x1
#define APB_SARADC_TSENS_CLK_INV_S 14
/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_XPD_FORCE 0x00000003
#define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
#define APB_SARADC_TSENS_XPD_FORCE_V 0x3
#define APB_SARADC_TSENS_XPD_FORCE_S 12
/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
/*description: Need add description.*/
#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF
#define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF
#define APB_SARADC_TSENS_XPD_WAIT_S 0
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */
/*description: Need add description.*/
#define APB_SARADC_CALI_CFG 0x0001FFFF
#define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
#define APB_SARADC_CALI_CFG_V 0x1FFFF
#define APB_SARADC_CALI_CFG_S 0
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02107210 ; */
/*description: Need add description.*/
#define APB_SARADC_DATE 0xFFFFFFFF
#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
#define APB_SARADC_DATE_V 0xFFFFFFFF
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_APB_SARADC_STRUCT_H_
#define _SOC_APB_SARADC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force : 1; /*Need add description*/
uint32_t start : 1; /*Need add description*/
uint32_t reserved2 : 4; /*Reserved 0: single mode, 1: double mode, 2: alternate mode*/
uint32_t sar_clk_gated : 1; /*Need add description*/
uint32_t sar_clk_div : 8; /*SAR clock divider*/
uint32_t sar_patt_len : 3; /* 0 ~ 15 means length 1 ~ 16*/
uint32_t reserved18 : 5; /*Reserved*/
uint32_t sar_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t reserved24 : 3; /*Reserved*/
uint32_t xpd_sar_force : 2; /*force option to xpd sar blocks*/
uint32_t reserved29 : 1; /*Reserved*/
uint32_t wait_arb_cycle : 2; /*wait arbit signal stable after sar_done*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t meas_num_limit : 1; /*Need add description*/
uint32_t max_meas_num : 8; /*max conversion number*/
uint32_t sar1_inv : 1; /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/
uint32_t sar2_inv : 1; /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/
uint32_t reserved11 : 1; /*Reserved1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target : 12; /*to set saradc timer target*/
uint32_t timer_en : 1; /*to enable saradc timer trigger*/
uint32_t reserved25 : 7; /*Reserved*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t reserved0 : 26; /*Reserved*/
uint32_t filter_factor1 : 3; /*Need add description*/
uint32_t filter_factor0 : 3; /*Need add description*/
};
uint32_t val;
} filter_ctrl1;
union {
struct {
uint32_t xpd_wait : 8; /*Need add description*/
uint32_t rstb_wait : 8; /*Need add description*/
uint32_t standby_wait : 8; /*Need add description*/
uint32_t reserved24 : 8; /*Reserved*/
};
uint32_t val;
} fsm_wait;
uint32_t sar1_status;
uint32_t sar2_status;
union {
struct {
uint32_t sar_patt_tab1 : 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t reserved24 : 8; /*Reserved*/
};
uint32_t val;
} sar_patt_tab[2];
union {
struct {
uint32_t reserved0 : 23; /*Reserved*/
uint32_t onetime_atten : 2; /*Need add description*/
uint32_t onetime_channel : 4; /*Need add description*/
uint32_t onetime_start : 1; /*Need add description*/
uint32_t adc2_onetime_sample : 1; /*Need add description*/
uint32_t adc1_onetime_sample : 1; /*Need add description*/
};
uint32_t val;
} onetime_sample;
union {
struct {
uint32_t reserved0 : 2; /*Reserved*/
uint32_t adc_arb_apb_force : 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force : 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force : 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force : 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority : 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority : 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority : 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority : 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13 : 19; /*Reserved*/
};
uint32_t val;
} apb_adc_arb_ctrl;
union {
struct {
uint32_t reserved0 : 18; /*Reserved*/
uint32_t filter_channel1 : 4; /*Need add description*/
uint32_t filter_channel0 : 4; /*apb_adc1_filter_factor*/
uint32_t reserved26 : 5; /*Reserved*/
uint32_t filter_reset : 1; /*enable apb_adc1_filter*/
};
uint32_t val;
} filter_ctrl0;
union {
struct {
uint32_t adc1_data : 17; /*Need add description*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} apb_saradc1_data_status;
union {
struct {
uint32_t adc2_data : 17; /*Need add description*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} apb_saradc2_data_status;
union {
struct {
uint32_t thres0_channel : 4; /*Need add description*/
uint32_t reserved4 : 1; /*Reserved*/
uint32_t thres0_high : 13; /*saradc1's thres0 monitor thres*/
uint32_t thres0_low : 13; /*saradc1's thres0 monitor thres*/
uint32_t reserved31 : 1; /*Reserved*/
};
uint32_t val;
} thres0_ctrl;
union {
struct {
uint32_t thres1_channel : 4; /*Need add description*/
uint32_t reserved4 : 1; /*Reserved*/
uint32_t thres1_high : 13; /*saradc1's thres0 monitor thres*/
uint32_t thres1_low : 13; /*saradc1's thres0 monitor thres*/
uint32_t reserved31 : 1; /*Reserved*/
};
uint32_t val;
} thres1_ctrl;
union {
struct {
uint32_t reserved0 : 27; /*Reserved*/
uint32_t thres_all_en : 1; /*Need add description*/
uint32_t thres3_en : 1; /*Need add description*/
uint32_t thres2_en : 1; /*Need add description*/
uint32_t thres1_en : 1; /*Need add description*/
uint32_t thres0_en : 1; /*Need add description*/
};
uint32_t val;
} thres_ctrl;
union {
struct {
uint32_t reserved0 : 26; /*Reserved*/
uint32_t thres1_low : 1; /*Need add description*/
uint32_t thres0_low : 1; /*Need add description*/
uint32_t thres1_high : 1; /*Need add description*/
uint32_t thres0_high : 1; /*Need add description*/
uint32_t adc2_done : 1; /*Need add description*/
uint32_t adc1_done : 1; /*Need add description*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t reserved0 : 26; /*Reserved*/
uint32_t thres1_low : 1; /*Need add description*/
uint32_t thres0_low : 1; /*Need add description*/
uint32_t thres1_high : 1; /*Need add description*/
uint32_t thres0_high : 1; /*Need add description*/
uint32_t adc2_done : 1; /*Need add description*/
uint32_t adc1_done : 1; /*Need add description*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t reserved0 : 26; /*Reserved*/
uint32_t thres1_low : 1; /*Need add description*/
uint32_t thres0_low : 1; /*Need add description*/
uint32_t thres1_high : 1; /*Need add description*/
uint32_t thres0_high : 1; /*Need add description*/
uint32_t adc2_done : 1; /*Need add description*/
uint32_t adc1_done : 1; /*Need add description*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t reserved0 : 26; /*Reserved*/
uint32_t thres1_low : 1; /*Need add description*/
uint32_t thres0_low : 1; /*Need add description*/
uint32_t thres1_high : 1; /*Need add description*/
uint32_t thres0_high : 1; /*Need add description*/
uint32_t adc2_done : 1; /*Need add description*/
uint32_t adc1_done : 1; /*Need add description*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_adc_eof_num : 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
uint32_t reserved16 : 14; /*Reserved*/
uint32_t apb_adc_reset_fsm : 1; /*reset_apb_adc_state*/
uint32_t apb_adc_trans : 1; /*enable apb_adc use spi_dma*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t clkm_div_num : 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b : 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a : 6; /*Fractional clock divider denominator value*/
uint32_t clk_en : 1; /*Need add description*/
uint32_t clk_sel : 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23 : 9; /*Reserved*/
};
uint32_t val;
} apb_adc_clkm_conf;
union {
struct {
uint32_t tsens_out : 8; /*Need add description*/
uint32_t reserved8 : 5; /*Reserved*/
uint32_t tsens_in_inv : 1; /*Need add description*/
uint32_t tsens_clk_div : 8; /*Need add description*/
uint32_t tsens_pu : 1; /*Need add description*/
uint32_t reserved23 : 9; /*Reserved*/
};
uint32_t val;
} apb_tsens_ctrl;
union {
struct {
uint32_t tsens_xpd_wait : 12; /*Need add description*/
uint32_t tsens_xpd_force : 2; /*Need add description*/
uint32_t tsens_clk_inv : 1; /*Need add description*/
uint32_t tsens_clk_sel : 1; /*Need add description*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} apb_tsens_ctrl2;
union {
struct {
uint32_t cali_cfg : 17; /*Need add description*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} cali;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date;
} apb_saradc_dev_t;
extern apb_saradc_dev_t APB_SARADC;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_STRUCT_H_ */

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* enbale sp underlow monitor
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* enbale sp overflow monitor
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* sp underlow monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* sp overflow monitor interupt status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
* enbale sp underlow monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
* enbale sp overflow monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clr register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* clr sp underlow monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* clr sp overflow monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* stack min value
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration regsiter
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* stack max value
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* stack monitor pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* This regsiter stores the PC when trigger stack monitor.
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* record enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* record status regsiter
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* record status regsiter
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* clock gate register
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* clock gate register
*/
#define ASSIST_DEBUG_CLK_EN (BIT(0))
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
#define ASSIST_DEBUG_CLK_EN_S 0
/** ASSIST_DEBUG_DATE_REG register
* version register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34627616;
* version register
*/
#define ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/* Some of the baseband control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_FFT_FORCE_PD (BIT(2))
#define BB_FFT_FORCE_PD_M (BIT(2))
#define BB_FFT_FORCE_PD_V 1
#define BB_FFT_FORCE_PD_S 2
#define BB_DC_EST_FORCE_PU (BIT(1))
#define BB_DC_EST_FORCE_PU_M (BIT(1))
#define BB_DC_EST_FORCE_PU_V 1
#define BB_DC_EST_FORCE_PU_S 1
#define BB_DC_EST_FORCE_PD (BIT(0))
#define BB_DC_EST_FORCE_PD_M (BIT(0))
#define BB_DC_EST_FORCE_PD_V 1
#define BB_DC_EST_FORCE_PD_S 0

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_01XX(v) (((v)&0x0c)==0x04)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_0100(v) (((v)&0x0f)==0x04)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_0110(v) (((v)&0x0f)==0x06)
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_0111(v) (((v)&0x0f)==0x07)
/*Diagnostic Mode1+USB download Mode*/
#define IS_0000(v) (((v)&0x0f)==0x00)
/*SPI(or SDIO_V1) download Mode*/
#define IS_0001(v) (((v)&0x0f)==0x01)
/*Diagnostic Mode0+UART0 download Mode*/
#define IS_0010(v) (((v)&0x0f)==0x02)
/*ATE/ANALOG Mode*/
#define IS_0011(v) (((v)&0x0f)==0x03)
/*print control*/
#define IS_X1XX(v) (((v)&0x04)==0x04)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
#define ETS_PRINT_CONTROL_HIGH_LEVEL() IS_X1XX(BOOT_MODE_GET())
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_0010(BOOT_MODE_GET())
#define ETS_IS_USB_BOOT() IS_0000(BOOT_MODE_GET())
/*all spi boot including spi/legacy*/
#define ETS_IS_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
/*all faster spi boot including spi*/
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
#if SUPPORT_SDIO_DOWNLOAD
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0100(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, raising edge output*/
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0101(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0110(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, raising edge output*/
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0111(BOOT_MODE_GET())
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0001(BOOT_MODE_GET())
/*do not include joint download mode*/
#define ETS_IS_SDIO_BOOT() IS_0001(BOOT_MODE_GET())
#else
/*do not include joint download mode*/
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0001(BOOT_MODE_GET())
#endif
/*joint download boot*/
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_01XX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_0011(BOOT_MODE_GET())
/*used by ETS_IS_SDIO_UART_BOOT*/
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#define SEL_SPI_SLAVE_BOOT BIT2
#define SEL_USB_BOOT BIT3
#endif /* _SOC_BOOT_MODE_H_ */

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/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "esp8684/rom/cache.h"
/*IRAM0 is connected with Cache IBUS0*/
#define MMU_PAGE_MODE MMU_Get_Page_Mode()
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
/*DRAM0 is connected with Cache DBUS0*/
#define DRAM0_ADDRESS_LOW 0x3C000000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + (0x100000 << (MMU_PAGE_MODE)))
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
#define ESP_CACHE_TEMP_ADDR 0x3C000000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
//IDF-3821
// #define MMU_SIZE 0x100
#define CACHE_IBUS 0
#define CACHE_IBUS_MMU_START 0
#define CACHE_IBUS_MMU_END 0x100
#define CACHE_DBUS 1
#define CACHE_DBUS_MMU_START 0
#define CACHE_DBUS_MMU_END 0x100
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
#define CACHE_DROM_MMU_MAX_END 0x100
#define ICACHE_MMU_SIZE 0x100
#define DCACHE_MMU_SIZE 0x100
#define MMU_BUS_START(i) 0
#define MMU_BUS_SIZE(i) 0x100
#define MMU_INVALID BIT(6)
#define MMU_TYPE 0
#define MMU_ACCESS_FLASH 0
#define CACHE_MAX_SYNC_NUM 0x400000
#define CACHE_MAX_LOCK_NUM 0x8000
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
#define MMU_TABLE_INVALID_VAL MMU_INVALID
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK (MMU_TABLE_INVALID_VAL - 1)
#define MMU_PAGE_SIZE (0x4000 << (MMU_PAGE_MODE))
#define INVALID_PHY_PAGE (MMU_PAGE_SIZE - 1)
#define BUS_ADDR_SIZE (0x100000 << (MMU_PAGE_MODE))
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_PMS_MASK 0xffffff
#define CACHE_ICACHE_LOW_SHIFT 0
#define CACHE_ICACHE_HIGH_SHIFT 2
#define CACHE_DCACHE_LOW_SHIFT 4
#define CACHE_DCACHE_HIGH_SHIFT 6
#define CACHE_MEMORY_IBANK0_ADDR 0x4037C000
#ifdef __cplusplus
}
#endif
#endif /*_CACHE_MEMORY_H_ */

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/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_CLKOUT_CHANNEL_H
#define _SOC_CLKOUT_CHANNEL_H
//CLKOUT channels
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
#endif

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include <stdint.h>
#include "esp_attr.h"
#include "esp_attr.h"
#include "esp8684/dport_access.h"
#include "soc.h"
#include "uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif
#endif /* _DPORT_ACCESS_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_REG_H_
#define _SOC_EFUSE_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
/* EFUSE_PGM_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 0th 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_0 0xFFFFFFFF
#define EFUSE_PGM_DATA_0_M ((EFUSE_PGM_DATA_0_V)<<(EFUSE_PGM_DATA_0_S))
#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_0_S 0
#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
/* EFUSE_PGM_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 1st 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_1 0xFFFFFFFF
#define EFUSE_PGM_DATA_1_M ((EFUSE_PGM_DATA_1_V)<<(EFUSE_PGM_DATA_1_S))
#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_1_S 0
#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
/* EFUSE_PGM_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 2nd 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_2 0xFFFFFFFF
#define EFUSE_PGM_DATA_2_M ((EFUSE_PGM_DATA_2_V)<<(EFUSE_PGM_DATA_2_S))
#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_2_S 0
#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xC)
/* EFUSE_PGM_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 3rd 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_3 0xFFFFFFFF
#define EFUSE_PGM_DATA_3_M ((EFUSE_PGM_DATA_3_V)<<(EFUSE_PGM_DATA_3_S))
#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_3_S 0
#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
/* EFUSE_PGM_DATA_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 4th 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_4 0xFFFFFFFF
#define EFUSE_PGM_DATA_4_M ((EFUSE_PGM_DATA_4_V)<<(EFUSE_PGM_DATA_4_S))
#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_4_S 0
#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
/* EFUSE_PGM_DATA_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 5th 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_5 0xFFFFFFFF
#define EFUSE_PGM_DATA_5_M ((EFUSE_PGM_DATA_5_V)<<(EFUSE_PGM_DATA_5_S))
#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_5_S 0
#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 6th 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_6 0xFFFFFFFF
#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S))
#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_6_S 0
#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1C)
/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 7th 32-bit data to be programmed..*/
#define EFUSE_PGM_DATA_7 0xFFFFFFFF
#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S))
#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF
#define EFUSE_PGM_DATA_7_S 0
#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 0th 32-bit RS code to be programmed..*/
#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF
#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S))
#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF
#define EFUSE_PGM_RS_DATA_0_S 0
#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 1st 32-bit RS code to be programmed..*/
#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF
#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S))
#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF
#define EFUSE_PGM_RS_DATA_1_S 0
#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The content of the 2nd 32-bit RS code to be programmed..*/
#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF
#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S))
#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF
#define EFUSE_PGM_RS_DATA_2_S 0
#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2C)
/* EFUSE_WR_DIS : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: Disable programming of individual eFuses..*/
#define EFUSE_WR_DIS 0x000000FF
#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
#define EFUSE_WR_DIS_V 0xFF
#define EFUSE_WR_DIS_S 0
#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
/* EFUSE_RPT4_RESERVED : RO ;bitpos:[31:22] ;default: 10'h0 ; */
/*description: Reserved (used for four backups method)..*/
#define EFUSE_RPT4_RESERVED 0x000003FF
#define EFUSE_RPT4_RESERVED_M ((EFUSE_RPT4_RESERVED_V)<<(EFUSE_RPT4_RESERVED_S))
#define EFUSE_RPT4_RESERVED_V 0x3FF
#define EFUSE_RPT4_RESERVED_S 22
/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: The bit be set to enable secure boot..*/
#define EFUSE_SECURE_BOOT_EN (BIT(21))
#define EFUSE_SECURE_BOOT_EN_M (BIT(21))
#define EFUSE_SECURE_BOOT_EN_V 0x1
#define EFUSE_SECURE_BOOT_EN_S 21
/* EFUSE_FLASH_TPUW : RO ;bitpos:[20:17] ;default: 4'h0 ; */
/*description: Configures flash waiting time after power-up, in unit of ms. If the value is les
s than 15, the waiting time is the configurable value. Otherwise, the waiting t
ime is twice the configurable value..*/
#define EFUSE_FLASH_TPUW 0x0000000F
#define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
#define EFUSE_FLASH_TPUW_V 0xF
#define EFUSE_FLASH_TPUW_S 17
/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: Set this bit to enable secure UART download mode..*/
#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(16))
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(16))
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 16
/* EFUSE_DIS_DIRECT_BOOT : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: This bit set means disable direct_boot mode..*/
#define EFUSE_DIS_DIRECT_BOOT (BIT(15))
#define EFUSE_DIS_DIRECT_BOOT_M (BIT(15))
#define EFUSE_DIS_DIRECT_BOOT_V 0x1
#define EFUSE_DIS_DIRECT_BOOT_S 15
/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7)..*/
#define EFUSE_DIS_DOWNLOAD_MODE (BIT(14))
#define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(14))
#define EFUSE_DIS_DOWNLOAD_MODE_V 0x1
#define EFUSE_DIS_DOWNLOAD_MODE_S 14
/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: Set this bit to force ROM code to send a resume command during SPI boot..*/
#define EFUSE_FORCE_SEND_RESUME (BIT(13))
#define EFUSE_FORCE_SEND_RESUME_M (BIT(13))
#define EFUSE_FORCE_SEND_RESUME_V 0x1
#define EFUSE_FORCE_SEND_RESUME_S 13
/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: Set this bit to disable usb printing..*/
#define EFUSE_UART_PRINT_CONTROL 0x00000003
#define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
#define EFUSE_UART_PRINT_CONTROL_V 0x3
#define EFUSE_UART_PRINT_CONTROL_S 11
/* EFUSE_XTS_KEY_LENGTH_256 : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwi
se, XTS_AES use 128-bit eFuse data in BLOCK3..*/
#define EFUSE_XTS_KEY_LENGTH_256 (BIT(10))
#define EFUSE_XTS_KEY_LENGTH_256_M (BIT(10))
#define EFUSE_XTS_KEY_LENGTH_256_V 0x1
#define EFUSE_XTS_KEY_LENGTH_256_S 10
/* EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT : RO ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. e
ven number of 1: disable..*/
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT 0x00000007
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_M ((EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V)<<(EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S))
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_V 0x7
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_S 7
/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit be set to disable manual encryption..*/
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(6))
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(6))
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 6
/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit be set to disable icache in download mode..*/
#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(5))
#define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(5))
#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1
#define EFUSE_DIS_DOWNLOAD_ICACHE_S 5
/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to disable pad jtag..*/
#define EFUSE_DIS_PAD_JTAG (BIT(4))
#define EFUSE_DIS_PAD_JTAG_M (BIT(4))
#define EFUSE_DIS_PAD_JTAG_V 0x1
#define EFUSE_DIS_PAD_JTAG_S 4
/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1
: 80000. 2: 160000. 3:320000..*/
#define EFUSE_WDT_DELAY_SEL 0x00000003
#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
#define EFUSE_WDT_DELAY_SEL_V 0x3
#define EFUSE_WDT_DELAY_SEL_S 2
/* EFUSE_KEY0_RD_DIS : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: The bit be set to disable software read high/low 128-bit of BLK3..*/
#define EFUSE_KEY0_RD_DIS 0x00000003
#define EFUSE_KEY0_RD_DIS_M ((EFUSE_KEY0_RD_DIS_V)<<(EFUSE_KEY0_RD_DIS_S))
#define EFUSE_KEY0_RD_DIS_V 0x3
#define EFUSE_KEY0_RD_DIS_S 0
#define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34)
/* EFUSE_SYSTEM_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Stores the bits [0:31] of system data..*/
#define EFUSE_SYSTEM_DATA0 0xFFFFFFFF
#define EFUSE_SYSTEM_DATA0_M ((EFUSE_SYSTEM_DATA0_V)<<(EFUSE_SYSTEM_DATA0_S))
#define EFUSE_SYSTEM_DATA0_V 0xFFFFFFFF
#define EFUSE_SYSTEM_DATA0_S 0
#define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38)
/* EFUSE_SYSTEM_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Stores the bits [32:63] of system data..*/
#define EFUSE_SYSTEM_DATA1 0xFFFFFFFF
#define EFUSE_SYSTEM_DATA1_M ((EFUSE_SYSTEM_DATA1_V)<<(EFUSE_SYSTEM_DATA1_S))
#define EFUSE_SYSTEM_DATA1_V 0xFFFFFFFF
#define EFUSE_SYSTEM_DATA1_S 0
#define EFUSE_RD_BLK1_DATA2_REG (DR_REG_EFUSE_BASE + 0x3C)
/* EFUSE_SYSTEM_DATA2 : RO ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Stores the bits [64:87] of system data..*/
#define EFUSE_SYSTEM_DATA2 0x00FFFFFF
#define EFUSE_SYSTEM_DATA2_M ((EFUSE_SYSTEM_DATA2_V)<<(EFUSE_SYSTEM_DATA2_S))
#define EFUSE_SYSTEM_DATA2_V 0xFFFFFF
#define EFUSE_SYSTEM_DATA2_S 0
#define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40)
/* EFUSE_MAC_ID_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the bit [0:31] of MAC..*/
#define EFUSE_MAC_ID_LOW 0xFFFFFFFF
#define EFUSE_MAC_ID_LOW_M ((EFUSE_MAC_ID_LOW_V)<<(EFUSE_MAC_ID_LOW_S))
#define EFUSE_MAC_ID_LOW_V 0xFFFFFFFF
#define EFUSE_MAC_ID_LOW_S 0
#define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44)
/* EFUSE_LDO_VOL_BIAS_CONFIG_LOW : RO ;bitpos:[31:29] ;default: 3'h0 ; */
/*description: Store the bit [0:2] of ido configuration parameters..*/
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW 0x00000007
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_M ((EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V)<<(EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S))
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_V 0x7
#define EFUSE_LDO_VOL_BIAS_CONFIG_LOW_S 29
/* EFUSE_RF_REF_I_BIAS_CONFIG : RO ;bitpos:[28:25] ;default: 4'h0 ; */
/*description: Store rf configuration parameters..*/
#define EFUSE_RF_REF_I_BIAS_CONFIG 0x0000000F
#define EFUSE_RF_REF_I_BIAS_CONFIG_M ((EFUSE_RF_REF_I_BIAS_CONFIG_V)<<(EFUSE_RF_REF_I_BIAS_CONFIG_S))
#define EFUSE_RF_REF_I_BIAS_CONFIG_V 0xF
#define EFUSE_RF_REF_I_BIAS_CONFIG_S 25
/* EFUSE_BLK2_EFUSE_VERSION : RO ;bitpos:[24:22] ;default: 3'h0 ; */
/*description: Store efuse version..*/
#define EFUSE_BLK2_EFUSE_VERSION 0x00000007
#define EFUSE_BLK2_EFUSE_VERSION_M ((EFUSE_BLK2_EFUSE_VERSION_V)<<(EFUSE_BLK2_EFUSE_VERSION_S))
#define EFUSE_BLK2_EFUSE_VERSION_V 0x7
#define EFUSE_BLK2_EFUSE_VERSION_S 22
/* EFUSE_PKG_VERSION : RO ;bitpos:[21:19] ;default: 3'h0 ; */
/*description: Store package version..*/
#define EFUSE_PKG_VERSION 0x00000007
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0x7
#define EFUSE_PKG_VERSION_S 19
/* EFUSE_WAFER_VERSION : RO ;bitpos:[18:16] ;default: 3'h0 ; */
/*description: Store wafer version..*/
#define EFUSE_WAFER_VERSION 0x00000007
#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S))
#define EFUSE_WAFER_VERSION_V 0x7
#define EFUSE_WAFER_VERSION_S 16
/* EFUSE_MAC_ID_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: Store the bit [31:47] of MAC..*/
#define EFUSE_MAC_ID_HIGH 0x0000FFFF
#define EFUSE_MAC_ID_HIGH_M ((EFUSE_MAC_ID_HIGH_V)<<(EFUSE_MAC_ID_HIGH_S))
#define EFUSE_MAC_ID_HIGH_V 0xFFFF
#define EFUSE_MAC_ID_HIGH_S 0
#define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48)
/* EFUSE_PVT_LOW : RO ;bitpos:[31:27] ;default: 5'h0 ; */
/*description: Store the bit [0:4] of pvt..*/
#define EFUSE_PVT_LOW 0x0000001F
#define EFUSE_PVT_LOW_M ((EFUSE_PVT_LOW_V)<<(EFUSE_PVT_LOW_S))
#define EFUSE_PVT_LOW_V 0x1F
#define EFUSE_PVT_LOW_S 27
/* EFUSE_LDO_VOL_BIAS_CONFIG_HIGH : RO ;bitpos:[26:0] ;default: 27'h0 ; */
/*description: Store the bit [3:29] of ido configuration parameters..*/
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH 0x07FFFFFF
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_M ((EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V)<<(EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S))
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_V 0x7FFFFFF
#define EFUSE_LDO_VOL_BIAS_CONFIG_HIGH_S 0
#define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4C)
/* EFUSE_ADC_CALIBRATION_0 : RO ;bitpos:[31:10] ;default: 22'h0 ; */
/*description: Store the bit [0:21] of ADC calibration data..*/
#define EFUSE_ADC_CALIBRATION_0 0x003FFFFF
#define EFUSE_ADC_CALIBRATION_0_M ((EFUSE_ADC_CALIBRATION_0_V)<<(EFUSE_ADC_CALIBRATION_0_S))
#define EFUSE_ADC_CALIBRATION_0_V 0x3FFFFF
#define EFUSE_ADC_CALIBRATION_0_S 10
/* EFUSE_PVT_HIGH : RO ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: Store the bit [5:14] of pvt..*/
#define EFUSE_PVT_HIGH 0x000003FF
#define EFUSE_PVT_HIGH_M ((EFUSE_PVT_HIGH_V)<<(EFUSE_PVT_HIGH_S))
#define EFUSE_PVT_HIGH_V 0x3FF
#define EFUSE_PVT_HIGH_S 0
#define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50)
/* EFUSE_ADC_CALIBRATION_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the bit [22:53] of ADC calibration data..*/
#define EFUSE_ADC_CALIBRATION_1 0xFFFFFFFF
#define EFUSE_ADC_CALIBRATION_1_M ((EFUSE_ADC_CALIBRATION_1_V)<<(EFUSE_ADC_CALIBRATION_1_S))
#define EFUSE_ADC_CALIBRATION_1_V 0xFFFFFFFF
#define EFUSE_ADC_CALIBRATION_1_S 0
#define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54)
/* EFUSE_ADC_CALIBRATION_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the bit [54:85] of ADC calibration data..*/
#define EFUSE_ADC_CALIBRATION_2 0xFFFFFFFF
#define EFUSE_ADC_CALIBRATION_2_M ((EFUSE_ADC_CALIBRATION_2_V)<<(EFUSE_ADC_CALIBRATION_2_S))
#define EFUSE_ADC_CALIBRATION_2_V 0xFFFFFFFF
#define EFUSE_ADC_CALIBRATION_2_S 0
#define EFUSE_RD_BLK2_DATA6_REG (DR_REG_EFUSE_BASE + 0x58)
/* EFUSE_BLK2_RESERVED_DATA_0 : RO ;bitpos:[31:11] ;default: 21'h0 ; */
/*description: Store the bit [0:20] of block2 reserved data..*/
#define EFUSE_BLK2_RESERVED_DATA_0 0x001FFFFF
#define EFUSE_BLK2_RESERVED_DATA_0_M ((EFUSE_BLK2_RESERVED_DATA_0_V)<<(EFUSE_BLK2_RESERVED_DATA_0_S))
#define EFUSE_BLK2_RESERVED_DATA_0_V 0x1FFFFF
#define EFUSE_BLK2_RESERVED_DATA_0_S 11
/* EFUSE_ADC_CALIBRATION_3 : RO ;bitpos:[10:0] ;default: 11'h0 ; */
/*description: Store the bit [86:96] of ADC calibration data..*/
#define EFUSE_ADC_CALIBRATION_3 0x000007FF
#define EFUSE_ADC_CALIBRATION_3_M ((EFUSE_ADC_CALIBRATION_3_V)<<(EFUSE_ADC_CALIBRATION_3_S))
#define EFUSE_ADC_CALIBRATION_3_V 0x7FF
#define EFUSE_ADC_CALIBRATION_3_S 0
#define EFUSE_RD_BLK2_DATA7_REG (DR_REG_EFUSE_BASE + 0x5C)
/* EFUSE_BLK2_RESERVED_DATA_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the bit [21:52] of block2 reserved data..*/
#define EFUSE_BLK2_RESERVED_DATA_1 0xFFFFFFFF
#define EFUSE_BLK2_RESERVED_DATA_1_M ((EFUSE_BLK2_RESERVED_DATA_1_V)<<(EFUSE_BLK2_RESERVED_DATA_1_S))
#define EFUSE_BLK2_RESERVED_DATA_1_V 0xFFFFFFFF
#define EFUSE_BLK2_RESERVED_DATA_1_S 0
#define EFUSE_RD_BLK3_DATA0_REG (DR_REG_EFUSE_BASE + 0x60)
/* EFUSE_BLK3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the first 32-bit of Block3..*/
#define EFUSE_BLK3_DATA0 0xFFFFFFFF
#define EFUSE_BLK3_DATA0_M ((EFUSE_BLK3_DATA0_V)<<(EFUSE_BLK3_DATA0_S))
#define EFUSE_BLK3_DATA0_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA0_S 0
#define EFUSE_RD_BLK3_DATA1_REG (DR_REG_EFUSE_BASE + 0x64)
/* EFUSE_BLK3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the second 32-bit of Block3..*/
#define EFUSE_BLK3_DATA1 0xFFFFFFFF
#define EFUSE_BLK3_DATA1_M ((EFUSE_BLK3_DATA1_V)<<(EFUSE_BLK3_DATA1_S))
#define EFUSE_BLK3_DATA1_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA1_S 0
#define EFUSE_RD_BLK3_DATA2_REG (DR_REG_EFUSE_BASE + 0x68)
/* EFUSE_BLK3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the third 32-bit of Block3..*/
#define EFUSE_BLK3_DATA2 0xFFFFFFFF
#define EFUSE_BLK3_DATA2_M ((EFUSE_BLK3_DATA2_V)<<(EFUSE_BLK3_DATA2_S))
#define EFUSE_BLK3_DATA2_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA2_S 0
#define EFUSE_RD_BLK3_DATA3_REG (DR_REG_EFUSE_BASE + 0x6C)
/* EFUSE_BLK3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the fourth 32-bit of Block3..*/
#define EFUSE_BLK3_DATA3 0xFFFFFFFF
#define EFUSE_BLK3_DATA3_M ((EFUSE_BLK3_DATA3_V)<<(EFUSE_BLK3_DATA3_S))
#define EFUSE_BLK3_DATA3_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA3_S 0
#define EFUSE_RD_BLK3_DATA4_REG (DR_REG_EFUSE_BASE + 0x70)
/* EFUSE_BLK3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the fifth 32-bit of Block3..*/
#define EFUSE_BLK3_DATA4 0xFFFFFFFF
#define EFUSE_BLK3_DATA4_M ((EFUSE_BLK3_DATA4_V)<<(EFUSE_BLK3_DATA4_S))
#define EFUSE_BLK3_DATA4_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA4_S 0
#define EFUSE_RD_BLK3_DATA5_REG (DR_REG_EFUSE_BASE + 0x74)
/* EFUSE_BLK3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the sixth 32-bit of Block3..*/
#define EFUSE_BLK3_DATA5 0xFFFFFFFF
#define EFUSE_BLK3_DATA5_M ((EFUSE_BLK3_DATA5_V)<<(EFUSE_BLK3_DATA5_S))
#define EFUSE_BLK3_DATA5_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA5_S 0
#define EFUSE_RD_BLK3_DATA6_REG (DR_REG_EFUSE_BASE + 0x78)
/* EFUSE_BLK3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the seventh 32-bit of Block3..*/
#define EFUSE_BLK3_DATA6 0xFFFFFFFF
#define EFUSE_BLK3_DATA6_M ((EFUSE_BLK3_DATA6_V)<<(EFUSE_BLK3_DATA6_S))
#define EFUSE_BLK3_DATA6_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA6_S 0
#define EFUSE_RD_BLK3_DATA7_REG (DR_REG_EFUSE_BASE + 0x7C)
/* EFUSE_BLK3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Store the eighth 32-bit of Block3..*/
#define EFUSE_BLK3_DATA7 0xFFFFFFFF
#define EFUSE_BLK3_DATA7_M ((EFUSE_BLK3_DATA7_V)<<(EFUSE_BLK3_DATA7_S))
#define EFUSE_BLK3_DATA7_V 0xFFFFFFFF
#define EFUSE_BLK3_DATA7_S 0
#define EFUSE_RD_REPEAT_ERR_REG (DR_REG_EFUSE_BASE + 0x80)
/* EFUSE_RPT4_RESERVED_ERR : RO ;bitpos:[31:22] ;default: 12'h0 ; */
/*description: Reserved..*/
#define EFUSE_RPT4_RESERVED_ERR 0x000003FF
#define EFUSE_RPT4_RESERVED_ERR_M ((EFUSE_RPT4_RESERVED_ERR_V)<<(EFUSE_RPT4_RESERVED_ERR_S))
#define EFUSE_RPT4_RESERVED_ERR_V 0x3FF
#define EFUSE_RPT4_RESERVED_ERR_S 22
/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: If any bit in this filed is 1, then it indicates a programming error..*/
#define EFUSE_SECURE_BOOT_EN_ERR (BIT(21))
#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(21))
#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1
#define EFUSE_SECURE_BOOT_EN_ERR_S 21
/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[20:17] ;default: 4'h0 ; */
/*description: If any bit in this filed is 1, then it indicates a programming error..*/
#define EFUSE_FLASH_TPUW_ERR 0x0000000F
#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S))
#define EFUSE_FLASH_TPUW_ERR_V 0xF
#define EFUSE_FLASH_TPUW_ERR_S 17
/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: If any bit in this filed is 1, then it indicates a programming error..*/
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(16))
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(16))
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1
#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 16
/* EFUSE_DIS_DIRECT_BOOT_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
/*description: If any bit in this filed is 1, then it indicates a programming error..*/
#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(15))
#define EFUSE_DIS_DIRECT_BOOT_ERR_M (BIT(15))
#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x1
#define EFUSE_DIS_DIRECT_BOOT_ERR_S 15
/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: If any bit in this filed is 1, then it indicates a programming error..*/
#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(14))
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(14))
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 14
/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error..*/
#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13))
#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(13))
#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1
#define EFUSE_FORCE_SEND_RESUME_ERR_S 13
/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[12:11] ;default: 2'h0 ; */
/*description: If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error..*/
#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003
#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S))
#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3
#define EFUSE_UART_PRINT_CONTROL_ERR_S 11
/* EFUSE_XTS_KEY_LENGTH_256_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error..*/
#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(10))
#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (BIT(10))
#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x1
#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 10
/* EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO ;bitpos:[9:7] ;default: 3'h0 ; */
/*description: If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming
error..*/
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR 0x00000007
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S))
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V 0x7
#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S 7
/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming
error..*/
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(6))
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(6))
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 6
/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: If any bit in this filed is 1, then it indicates a programming error..*/
#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(5))
#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(5))
#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1
#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 5
/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error..*/
#define EFUSE_DIS_PAD_JTAG_ERR (BIT(4))
#define EFUSE_DIS_PAD_JTAG_ERR_M (BIT(4))
#define EFUSE_DIS_PAD_JTAG_ERR_V 0x1
#define EFUSE_DIS_PAD_JTAG_ERR_S 4
/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error..*/
#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003
#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S))
#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3
#define EFUSE_WDT_DELAY_SEL_ERR_S 2
/* EFUSE_KEY0_RD_DIS_ERR : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: If any bit in RD_DIS is 1, then it indicates a programming error..*/
#define EFUSE_KEY0_RD_DIS_ERR 0x00000003
#define EFUSE_KEY0_RD_DIS_ERR_M ((EFUSE_KEY0_RD_DIS_ERR_V)<<(EFUSE_KEY0_RD_DIS_ERR_S))
#define EFUSE_KEY0_RD_DIS_ERR_V 0x3
#define EFUSE_KEY0_RD_DIS_ERR_S 0
#define EFUSE_RD_RS_ERR_REG (DR_REG_EFUSE_BASE + 0x84)
/* EFUSE_BLK3_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: 0: Means no failure and that the block3 data is reliable 1: Means that programmi
ng user data failed and the number of error bytes is over 6..*/
#define EFUSE_BLK3_FAIL (BIT(11))
#define EFUSE_BLK3_FAIL_M (BIT(11))
#define EFUSE_BLK3_FAIL_V 0x1
#define EFUSE_BLK3_FAIL_S 11
/* EFUSE_BLK3_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
/*description: The value of this signal means the number of error bytes in block3..*/
#define EFUSE_BLK3_ERR_NUM 0x00000007
#define EFUSE_BLK3_ERR_NUM_M ((EFUSE_BLK3_ERR_NUM_V)<<(EFUSE_BLK3_ERR_NUM_S))
#define EFUSE_BLK3_ERR_NUM_V 0x7
#define EFUSE_BLK3_ERR_NUM_S 8
/* EFUSE_BLK2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: 0: Means no failure and that the data of block2 is reliable 1: Means that progra
mming user data failed and the number of error bytes is over 6..*/
#define EFUSE_BLK2_FAIL (BIT(7))
#define EFUSE_BLK2_FAIL_M (BIT(7))
#define EFUSE_BLK2_FAIL_V 0x1
#define EFUSE_BLK2_FAIL_S 7
/* EFUSE_BLK2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
/*description: The value of this signal means the number of error bytes in block2..*/
#define EFUSE_BLK2_ERR_NUM 0x00000007
#define EFUSE_BLK2_ERR_NUM_M ((EFUSE_BLK2_ERR_NUM_V)<<(EFUSE_BLK2_ERR_NUM_S))
#define EFUSE_BLK2_ERR_NUM_V 0x7
#define EFUSE_BLK2_ERR_NUM_S 4
/* EFUSE_BLK1_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: 0: Means no failure and that the data of block1 is reliable 1: Means that progra
mming user data failed and the number of error bytes is over 6..*/
#define EFUSE_BLK1_FAIL (BIT(3))
#define EFUSE_BLK1_FAIL_M (BIT(3))
#define EFUSE_BLK1_FAIL_V 0x1
#define EFUSE_BLK1_FAIL_S 3
/* EFUSE_BLK1_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
/*description: The value of this signal means the number of error bytes in block1..*/
#define EFUSE_BLK1_ERR_NUM 0x00000007
#define EFUSE_BLK1_ERR_NUM_M ((EFUSE_BLK1_ERR_NUM_V)<<(EFUSE_BLK1_ERR_NUM_S))
#define EFUSE_BLK1_ERR_NUM_V 0x7
#define EFUSE_BLK1_ERR_NUM_S 0
#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x88)
/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: Set this bit and force to enable clock signal of eFuse memory..*/
#define EFUSE_CLK_EN (BIT(16))
#define EFUSE_CLK_EN_M (BIT(16))
#define EFUSE_CLK_EN_V 0x1
#define EFUSE_CLK_EN_S 16
/* EFUSE_EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to force eFuse SRAM into working mode..*/
#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2))
#define EFUSE_EFUSE_MEM_FORCE_PU_M (BIT(2))
#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x1
#define EFUSE_EFUSE_MEM_FORCE_PU_S 2
/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: Set this bit and force to activate clock signal of eFuse SRAM..*/
#define EFUSE_MEM_CLK_FORCE_ON (BIT(1))
#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1))
#define EFUSE_MEM_CLK_FORCE_ON_V 0x1
#define EFUSE_MEM_CLK_FORCE_ON_S 1
/* EFUSE_EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to force eFuse SRAM into power-saving mode..*/
#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0))
#define EFUSE_EFUSE_MEM_FORCE_PD_M (BIT(0))
#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x1
#define EFUSE_EFUSE_MEM_FORCE_PD_S 0
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8C)
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/
#define EFUSE_OP_CODE 0x0000FFFF
#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
#define EFUSE_OP_CODE_V 0xFFFF
#define EFUSE_OP_CODE_S 0
#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x90)
/* EFUSE_BLK0_VALID_BIT_CNT : RO ;bitpos:[15:10] ;default: 8'h0 ; */
/*description: Record the number of bit '1' in BLOCK0..*/
#define EFUSE_BLK0_VALID_BIT_CNT 0x0000003F
#define EFUSE_BLK0_VALID_BIT_CNT_M ((EFUSE_BLK0_VALID_BIT_CNT_V)<<(EFUSE_BLK0_VALID_BIT_CNT_S))
#define EFUSE_BLK0_VALID_BIT_CNT_V 0x3F
#define EFUSE_BLK0_VALID_BIT_CNT_S 10
/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The value of OTP_VDDQ_IS_SW..*/
#define EFUSE_OTP_VDDQ_IS_SW (BIT(9))
#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9))
#define EFUSE_OTP_VDDQ_IS_SW_V 0x1
#define EFUSE_OTP_VDDQ_IS_SW_S 9
/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The value of OTP_PGENB_SW..*/
#define EFUSE_OTP_PGENB_SW (BIT(8))
#define EFUSE_OTP_PGENB_SW_M (BIT(8))
#define EFUSE_OTP_PGENB_SW_V 0x1
#define EFUSE_OTP_PGENB_SW_S 8
/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The value of OTP_CSB_SW..*/
#define EFUSE_OTP_CSB_SW (BIT(7))
#define EFUSE_OTP_CSB_SW_M (BIT(7))
#define EFUSE_OTP_CSB_SW_V 0x1
#define EFUSE_OTP_CSB_SW_S 7
/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The value of OTP_STROBE_SW..*/
#define EFUSE_OTP_STROBE_SW (BIT(6))
#define EFUSE_OTP_STROBE_SW_M (BIT(6))
#define EFUSE_OTP_STROBE_SW_V 0x1
#define EFUSE_OTP_STROBE_SW_S 6
/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The value of OTP_VDDQ_C_SYNC2..*/
#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5))
#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5))
#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1
#define EFUSE_OTP_VDDQ_C_SYNC2_S 5
/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The value of OTP_LOAD_SW..*/
#define EFUSE_OTP_LOAD_SW (BIT(4))
#define EFUSE_OTP_LOAD_SW_M (BIT(4))
#define EFUSE_OTP_LOAD_SW_V 0x1
#define EFUSE_OTP_LOAD_SW_S 4
/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: Indicates the state of the eFuse state machine..*/
#define EFUSE_STATE 0x0000000F
#define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
#define EFUSE_STATE_V 0xF
#define EFUSE_STATE_S 0
#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x94)
/* EFUSE_BLK_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: The serial number of the block to be programmed. Value 0-3 corresponds to block
number 0-3, respectively..*/
#define EFUSE_BLK_NUM 0x00000003
#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
#define EFUSE_BLK_NUM_V 0x3
#define EFUSE_BLK_NUM_S 2
/* EFUSE_PGM_CMD : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to send programming command..*/
#define EFUSE_PGM_CMD (BIT(1))
#define EFUSE_PGM_CMD_M (BIT(1))
#define EFUSE_PGM_CMD_V 0x1
#define EFUSE_PGM_CMD_S 1
/* EFUSE_READ_CMD : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to send read command..*/
#define EFUSE_READ_CMD (BIT(0))
#define EFUSE_READ_CMD_M (BIT(0))
#define EFUSE_READ_CMD_V 0x1
#define EFUSE_READ_CMD_S 0
#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x98)
/* EFUSE_PGM_DONE_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw bit signal for pgm_done interrupt..*/
#define EFUSE_PGM_DONE_INT_RAW (BIT(1))
#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1))
#define EFUSE_PGM_DONE_INT_RAW_V 0x1
#define EFUSE_PGM_DONE_INT_RAW_S 1
/* EFUSE_READ_DONE_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw bit signal for read_done interrupt..*/
#define EFUSE_READ_DONE_INT_RAW (BIT(0))
#define EFUSE_READ_DONE_INT_RAW_M (BIT(0))
#define EFUSE_READ_DONE_INT_RAW_V 0x1
#define EFUSE_READ_DONE_INT_RAW_S 0
#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x9C)
/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The status signal for pgm_done interrupt..*/
#define EFUSE_PGM_DONE_INT_ST (BIT(1))
#define EFUSE_PGM_DONE_INT_ST_M (BIT(1))
#define EFUSE_PGM_DONE_INT_ST_V 0x1
#define EFUSE_PGM_DONE_INT_ST_S 1
/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The status signal for read_done interrupt..*/
#define EFUSE_READ_DONE_INT_ST (BIT(0))
#define EFUSE_READ_DONE_INT_ST_M (BIT(0))
#define EFUSE_READ_DONE_INT_ST_V 0x1
#define EFUSE_READ_DONE_INT_ST_S 0
#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x100)
/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable signal for pgm_done interrupt..*/
#define EFUSE_PGM_DONE_INT_ENA (BIT(1))
#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1))
#define EFUSE_PGM_DONE_INT_ENA_V 0x1
#define EFUSE_PGM_DONE_INT_ENA_S 1
/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The enable signal for read_done interrupt..*/
#define EFUSE_READ_DONE_INT_ENA (BIT(0))
#define EFUSE_READ_DONE_INT_ENA_M (BIT(0))
#define EFUSE_READ_DONE_INT_ENA_V 0x1
#define EFUSE_READ_DONE_INT_ENA_S 0
#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x104)
/* EFUSE_PGM_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: The clear signal for pgm_done interrupt..*/
#define EFUSE_PGM_DONE_INT_CLR (BIT(1))
#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1))
#define EFUSE_PGM_DONE_INT_CLR_V 0x1
#define EFUSE_PGM_DONE_INT_CLR_S 1
/* EFUSE_READ_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear signal for read_done interrupt..*/
#define EFUSE_READ_DONE_INT_CLR (BIT(0))
#define EFUSE_READ_DONE_INT_CLR_M (BIT(0))
#define EFUSE_READ_DONE_INT_CLR_V 0x1
#define EFUSE_READ_DONE_INT_CLR_S 0
#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x108)
/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: Reduces the power supply of the programming voltage..*/
#define EFUSE_OE_CLR (BIT(17))
#define EFUSE_OE_CLR_M (BIT(17))
#define EFUSE_OE_CLR_V 0x1
#define EFUSE_OE_CLR_S 17
/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
/*description: Controls the rising period of the programming voltage..*/
#define EFUSE_DAC_NUM 0x000000FF
#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S))
#define EFUSE_DAC_NUM_V 0xFF
#define EFUSE_DAC_NUM_S 9
/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Don't care..*/
#define EFUSE_DAC_CLK_PAD_SEL (BIT(8))
#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8))
#define EFUSE_DAC_CLK_PAD_SEL_V 0x1
#define EFUSE_DAC_CLK_PAD_SEL_S 8
/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */
/*description: Controls the division factor of the rising clock of the programming voltage..*/
#define EFUSE_DAC_CLK_DIV 0x000000FF
#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
#define EFUSE_DAC_CLK_DIV_V 0xFF
#define EFUSE_DAC_CLK_DIV_S 0
#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x10C)
/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */
/*description: Configures the initial read time of eFuse..*/
#define EFUSE_READ_INIT_NUM 0x000000FF
#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
#define EFUSE_READ_INIT_NUM_V 0xFF
#define EFUSE_READ_INIT_NUM_S 24
/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
/*description: Configures setup time for efuse read..*/
#define EFUSE_TSUR_A 0x000000FF
#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S))
#define EFUSE_TSUR_A_V 0xFF
#define EFUSE_TSUR_A_S 16
/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
/*description: Configures pulse time for efuse read..*/
#define EFUSE_TRD 0x000000FF
#define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S))
#define EFUSE_TRD_V 0xFF
#define EFUSE_TRD_S 8
/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
/*description: Configures hold time for efuse read..*/
#define EFUSE_THR_A 0x000000FF
#define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S))
#define EFUSE_THR_A_V 0xFF
#define EFUSE_THR_A_S 0
#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110)
/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */
/*description: Configures pulse time for burning '1' bit..*/
#define EFUSE_TPGM 0x0000FFFF
#define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S))
#define EFUSE_TPGM_V 0xFFFF
#define EFUSE_TPGM_S 16
/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
/*description: Configures pulse time for burning '0' bit..*/
#define EFUSE_TPGM_INACTIVE 0x000000FF
#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S))
#define EFUSE_TPGM_INACTIVE_V 0xFF
#define EFUSE_TPGM_INACTIVE_S 8
/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
/*description: Configures hold time for efuse program..*/
#define EFUSE_THP_A 0x000000FF
#define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S))
#define EFUSE_THP_A_V 0xFF
#define EFUSE_THP_A_S 0
#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x114)
/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h3000 ; */
/*description: Configures the power up time for VDDQ..*/
#define EFUSE_PWR_ON_NUM 0x0000FFFF
#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
#define EFUSE_PWR_ON_NUM_V 0xFFFF
#define EFUSE_PWR_ON_NUM_S 8
/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
/*description: Configures setup time for efuse program..*/
#define EFUSE_TSUP_A 0x000000FF
#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S))
#define EFUSE_TSUP_A_V 0xFF
#define EFUSE_TSUP_A_S 0
#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x118)
/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */
/*description: Configures the power outage time for VDDQ..*/
#define EFUSE_PWR_OFF_NUM 0x0000FFFF
#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S))
#define EFUSE_PWR_OFF_NUM_V 0xFFFF
#define EFUSE_PWR_OFF_NUM_S 0
#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC)
/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
/*description: Stores eFuse version..*/
#define EFUSE_DATE 0x0FFFFFFF
#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
#define EFUSE_DATE_V 0xFFFFFFF
#define EFUSE_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_EFUSE_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0;
uint32_t pgm_data1;
uint32_t pgm_data2;
uint32_t pgm_data3;
uint32_t pgm_data4;
uint32_t pgm_data5;
uint32_t pgm_data6;
uint32_t pgm_data7;
uint32_t pgm_check_value0;
uint32_t pgm_check_value1;
uint32_t pgm_check_value2;
union {
struct {
uint32_t reg_wr_dis : 8; /*Disable programming of individual eFuses.*/
uint32_t reserved8 : 24; /*Reserved.*/
};
uint32_t val;
} rd_wr_dis;
union {
struct {
uint32_t reg_rd_dis : 2; /*The bit be set to disable software read high/low 128-bit of BLK3.*/
uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable pad jtag.*/
uint32_t reg_dis_download_icache : 1; /*The bit be set to disable icache in download mode.*/
uint32_t reg_dis_download_manual_encrypt: 1; /*The bit be set to disable manual encryption.*/
uint32_t reg_spi_boot_encrypt_decrypt_cnt: 3; /*These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
uint32_t reg_xts_key_length_256 : 1; /*The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3.*/
uint32_t reg_uart_print_control : 2; /*Set this bit to disable usb printing.*/
uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).*/
uint32_t reg_dis_direct_boot : 1; /*This bit set means disable direct_boot mode.*/
uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/
uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value.*/
uint32_t reg_secure_boot_en : 1; /*The bit be set to enable secure boot.*/
uint32_t reg_rpt4_reserved : 10; /*Reserved (used for four backups method).*/
};
uint32_t val;
} rd_repeat_data0;
uint32_t rd_blk1_data0;
uint32_t rd_blk1_data1;
union {
struct {
uint32_t reg_system_data2 : 24; /*Stores the bits [64:87] of system data.*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
} rd_blk1_data2;
uint32_t rd_blk2_data0;
union {
struct {
uint32_t reg_mac_id_high : 16; /*Store the bit [31:47] of MAC.*/
uint32_t reg_wafer_version : 3; /*Store wafer version.*/
uint32_t reg_pkg_version : 3; /*Store package version.*/
uint32_t reg_blk2_efuse_version : 3; /*Store efuse version.*/
uint32_t reg_rf_ref_i_bias_config : 4; /*Store rf configuration parameters.*/
uint32_t reg_ldo_vol_bias_config_low : 3; /*Store the bit [0:2] of ido configuration parameters.*/
};
uint32_t val;
} rd_blk2_data1;
union {
struct {
uint32_t reg_ldo_vol_bias_config_high : 27; /*Store the bit [3:29] of ido configuration parameters.*/
uint32_t reg_pvt_low : 5; /*Store the bit [0:4] of pvt.*/
};
uint32_t val;
} rd_blk2_data2;
union {
struct {
uint32_t reg_pvt_high : 10; /*Store the bit [5:14] of pvt.*/
uint32_t reg_adc_calibration_0 : 22; /*Store the bit [0:21] of ADC calibration data.*/
};
uint32_t val;
} rd_blk2_data3;
uint32_t rd_blk2_data4;
uint32_t rd_blk2_data5;
union {
struct {
uint32_t reg_adc_calibration_3 : 11; /*Store the bit [86:96] of ADC calibration data.*/
uint32_t reg_blk2_reserved_data_0 : 21; /*Store the bit [0:20] of block2 reserved data.*/
};
uint32_t val;
} rd_blk2_data6;
uint32_t rd_blk2_data7;
uint32_t rd_blk3_data0;
uint32_t rd_blk3_data1;
uint32_t rd_blk3_data2;
uint32_t rd_blk3_data3;
uint32_t rd_blk3_data4;
uint32_t rd_blk3_data5;
uint32_t rd_blk3_data6;
uint32_t rd_blk3_data7;
union {
struct {
uint32_t reg_rd_dis_err : 2; /*If any bit in RD_DIS is 1, then it indicates a programming error.*/
uint32_t reg_wdt_delay_sel_err : 2; /*If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.*/
uint32_t reg_dis_pad_jtag_err : 1; /*If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.*/
uint32_t reg_dis_download_icache : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/
uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.*/
uint32_t reg_spi_boot_encrypt_decrypt_cnt_err: 3; /*If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error.*/
uint32_t reg_xts_key_length_256_err : 1; /*If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.*/
uint32_t reg_uart_print_control_err : 2; /*If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.*/
uint32_t reg_force_send_resume_err : 1; /*If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.*/
uint32_t reg_dis_download_mode_err : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/
uint32_t reg_dis_direct_boot_err : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/
uint32_t reg_enable_security_download_err: 1; /*If any bit in this filed is 1, then it indicates a programming error.*/
uint32_t reg_flash_tpuw_err : 4; /*If any bit in this filed is 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_en_err : 1; /*If any bit in this filed is 1, then it indicates a programming error.*/
uint32_t reg_rpt4_reserved_err : 10; /*Reserved.*/
};
uint32_t val;
} rd_repeat_err;
union {
struct {
uint32_t blk1_err_num : 3; /*The value of this signal means the number of error bytes in block1.*/
uint32_t blk1_fail : 1; /*0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_t blk2_err_num : 3; /*The value of this signal means the number of error bytes in block2.*/
uint32_t blk2_fail : 1; /*0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_t blk3_err_num : 3; /*The value of this signal means the number of error bytes in block3.*/
uint32_t blk3_fail : 1; /*0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_t reserved12 : 20; /*Reserved.*/
};
uint32_t val;
} rd_rs_err;
union {
struct {
uint32_t reg_efuse_mem_force_pd : 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/
uint32_t reg_mem_clk_force_on : 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/
uint32_t reg_efuse_mem_force_pu : 1; /*Set this bit to force eFuse SRAM into working mode.*/
uint32_t reserved3 : 13; /*Reserved.*/
uint32_t reg_clk_en : 1; /*Set this bit and force to enable clock signal of eFuse memory.*/
uint32_t reserved17 : 15; /*Reserved.*/
};
uint32_t val;
} clk;
union {
struct {
uint32_t reg_op_code : 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
uint32_t reserved16 : 16; /*Reserved.*/
};
uint32_t val;
} conf;
union {
struct {
uint32_t reg_state : 4; /*Indicates the state of the eFuse state machine.*/
uint32_t reg_otp_load_sw : 1; /*The value of OTP_LOAD_SW.*/
uint32_t reg_otp_vddq_c_sync2 : 1; /*The value of OTP_VDDQ_C_SYNC2.*/
uint32_t reg_otp_strobe_sw : 1; /*The value of OTP_STROBE_SW.*/
uint32_t reg_otp_csb_sw : 1; /*The value of OTP_CSB_SW.*/
uint32_t reg_otp_pgenb_sw : 1; /*The value of OTP_PGENB_SW.*/
uint32_t reg_otp_vddq_is_sw : 1; /*The value of OTP_VDDQ_IS_SW.*/
uint32_t reg_blk0_valid_bit_cnt : 6; /*Record the number of bit '1' in BLOCK0.*/
uint32_t reserved16 : 16; /*Reserved.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t reg_read_cmd : 1; /*Set this bit to send read command.*/
uint32_t reg_pgm_cmd : 1; /*Set this bit to send programming command.*/
uint32_t reg_blk_num : 2; /*The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively.*/
uint32_t reserved4 : 28; /*Reserved.*/
};
uint32_t val;
} cmd;
union {
struct {
uint32_t reg_read_done_int_raw : 1; /*The raw bit signal for read_done interrupt.*/
uint32_t reg_pgm_done_int_raw : 1; /*The raw bit signal for pgm_done interrupt.*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t reg_read_done_int_st : 1; /*The status signal for read_done interrupt.*/
uint32_t reg_pgm_done_int_st : 1; /*The status signal for pgm_done interrupt.*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} int_st;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
union {
struct {
uint32_t reg_read_done_int_ena : 1; /*The enable signal for read_done interrupt.*/
uint32_t reg_pgm_done_int_ena : 1; /*The enable signal for pgm_done interrupt.*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t reg_read_done_int_clr : 1; /*The clear signal for read_done interrupt.*/
uint32_t reg_pgm_done_int_clr : 1; /*The clear signal for pgm_done interrupt.*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t reg_dac_clk_div : 8; /*Controls the division factor of the rising clock of the programming voltage.*/
uint32_t reg_dac_clk_pad_sel : 1; /*Don't care.*/
uint32_t reg_dac_num : 8; /*Controls the rising period of the programming voltage.*/
uint32_t reg_oe_clr : 1; /*Reduces the power supply of the programming voltage.*/
uint32_t reserved18 : 14; /*Reserved.*/
};
uint32_t val;
} dac_conf;
union {
struct {
uint32_t reg_thr_a : 8; /*Configures hold time for efuse read.*/
uint32_t reg_trd : 8; /*Configures pulse time for efuse read.*/
uint32_t reg_tsur_a : 8; /*Configures setup time for efuse read.*/
uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/
};
uint32_t val;
} rd_tim_conf;
union {
struct {
uint32_t reg_thp_a : 8; /*Configures hold time for efuse program.*/
uint32_t reg_tpgm_inactive : 8; /*Configures pulse time for burning '0' bit.*/
uint32_t reg_tpgm : 16; /*Configures pulse time for burning '1' bit.*/
};
uint32_t val;
} wr_tim_conf0;
union {
struct {
uint32_t reg_tsup_a : 8; /*Configures setup time for efuse program.*/
uint32_t reg_pwr_on_num : 16; /*Configures the power up time for VDDQ.*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
} wr_tim_conf1;
union {
struct {
uint32_t reg_pwr_off_num : 16; /*Configures the power outage time for VDDQ.*/
uint32_t reserved16 : 16; /*Reserved.*/
};
uint32_t val;
} wr_tim_conf2;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
uint32_t reg_efuse_date : 28; /*Stores eFuse version.*/
uint32_t reserved28 : 4; /*Reserved.*/
};
uint32_t val;
} date;
} efuse_dev_t;
extern efuse_dev_t EFUSE;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_EFUSE_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_EXTMEM_REG_H_
#define _SOC_EXTMEM_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)
/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/
#define EXTMEM_ICACHE_ENABLE (BIT(0))
#define EXTMEM_ICACHE_ENABLE_M (BIT(0))
#define EXTMEM_ICACHE_ENABLE_V 0x1
#define EXTMEM_ICACHE_ENABLE_S 0
#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4)
/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/
#define EXTMEM_ICACHE_SHUT_DBUS (BIT(1))
#define EXTMEM_ICACHE_SHUT_DBUS_M (BIT(1))
#define EXTMEM_ICACHE_SHUT_DBUS_V 0x1
#define EXTMEM_ICACHE_SHUT_DBUS_S 1
/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/
#define EXTMEM_ICACHE_SHUT_IBUS (BIT(0))
#define EXTMEM_ICACHE_SHUT_IBUS_M (BIT(0))
#define EXTMEM_ICACHE_SHUT_IBUS_V 0x1
#define EXTMEM_ICACHE_SHUT_IBUS_S 0
#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8)
/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up.*/
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2
/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power d
own.*/
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1
/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to close clock gating of icache tag memory. 1: close gating, 0:
open clock gating..*/
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0
#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28)
/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to indicate invalidate operation is finished..*/
#define EXTMEM_ICACHE_SYNC_DONE (BIT(1))
#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1))
#define EXTMEM_ICACHE_SYNC_DONE_V 0x1
#define EXTMEM_ICACHE_SYNC_DONE_S 1
/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W/SS ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
fter invalidate operation done..*/
#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0))
#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0))
#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1
#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0
#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2C)
/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The bits are used to configure the start virtual address for clean operations. I
t should be combined with ICACHE_SYNC_SIZE_REG..*/
#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE_SYNC_ADDR_S 0
#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30)
/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
/*description: The bits are used to configure the length for sync operations. The bits are the
counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/
#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF
#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF
#define EXTMEM_ICACHE_SYNC_SIZE_S 0
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x54)
/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */
/*description: The bits are used to configure the start virtual address of ibus to access flash
. The register is used to give constraints to ibus access counter..*/
#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x58)
/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h423fffff ; */
/*description: The bits are used to configure the end virtual address of ibus to access flash.
The register is used to give constraints to ibus access counter..*/
#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x5C)
/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3c000000 ; */
/*description: The bits are used to configure the start virtual address of dbus to access flash
. The register is used to give constraints to dbus access counter..*/
#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x60)
/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3c3fffff ; */
/*description: The bits are used to configure the end virtual address of dbus to access flash.
The register is used to give constraints to dbus access counter..*/
#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0
#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x64)
/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to clear dbus counter..*/
#define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1))
#define EXTMEM_DBUS_ACS_CNT_CLR_M (BIT(1))
#define EXTMEM_DBUS_ACS_CNT_CLR_V 0x1
#define EXTMEM_DBUS_ACS_CNT_CLR_S 1
/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to clear ibus counter..*/
#define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0))
#define EXTMEM_IBUS_ACS_CNT_CLR_M (BIT(0))
#define EXTMEM_IBUS_ACS_CNT_CLR_V 0x1
#define EXTMEM_IBUS_ACS_CNT_CLR_S 0
#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x78)
/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by dbus counter overflow..*/
#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8))
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8))
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8
/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by ibus counter overflow..*/
#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7
/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by mmu entry fault..*/
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by preload configurations fault..*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by sync configurations fault..*/
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0))
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0))
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0
#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x7C)
/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by dbus counter overflow..*/
#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8))
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8))
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8
/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by ibus counter overflow..*/
#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7))
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7
/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by mmu entry fault..*/
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by preload configurations fault..*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by sync configurations fault..*/
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0))
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0))
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0
#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x80)
/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow
..*/
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10))
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10))
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10
/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl
ow..*/
#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9))
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9))
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9
/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o
verflow..*/
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8))
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8))
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8
/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl
ow..*/
#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7))
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7))
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7
/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by mmu entry fault..*/
#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5))
#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1
#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by preload configurations fault..*/
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1
/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by sync configurations fault..*/
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0))
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0))
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0
#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x84)
/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by dbus trying to write icache.*/
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5))
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (BIT(5))
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x1
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5
/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by authentication fail..*/
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4
/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
dbus is disabled which include speculative access..*/
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x1
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3
/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by authentication fail..*/
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2
/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by ibus trying to write icache.*/
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1
/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
ibus is disabled which include speculative access..*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0
#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x88)
/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by dbus trying to write icache.*/
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5))
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (BIT(5))
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x1
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5
/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by authentication fail..*/
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4
/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
dbus is disabled or icache is disabled which include speculative access..*/
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3
/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by authentication fail..*/
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2
/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by ibus trying to write icache.*/
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1
/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
ibus is disabled or icache is disabled which include speculative access..*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0
#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x8C)
/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by dbus trying to write icache.*/
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5))
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (BIT(5))
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5
/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by authentication fail..*/
#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4))
#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1
#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4
/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by cpu access icache while the core0_dbus
is disabled or icache is disabled which include speculative access..*/
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3))
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3
/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by authentication fail..*/
#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2))
#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1
#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2
/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1))
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1
/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus
is disabled or icache is disabled which include speculative access..*/
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0))
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0
#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x90)
/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate the world of CPU access dbus when authentication fai
l. 0: WORLD0, 1: WORLD1.*/
#define EXTMEM_CORE0_DBUS_WORLD (BIT(3))
#define EXTMEM_CORE0_DBUS_WORLD_M (BIT(3))
#define EXTMEM_CORE0_DBUS_WORLD_V 0x1
#define EXTMEM_CORE0_DBUS_WORLD_S 3
/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati
on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
#define EXTMEM_CORE0_DBUS_ATTR 0x00000007
#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
#define EXTMEM_CORE0_DBUS_ATTR_V 0x7
#define EXTMEM_CORE0_DBUS_ATTR_S 0
#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x94)
/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: The bits are used to indicate the virtual address of CPU access dbus when authen
tication fail..*/
#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF
#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF
#define EXTMEM_CORE0_DBUS_VADDR_S 0
#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x98)
/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The bit is used to indicate the world of CPU access ibus when authentication fai
l. 0: WORLD0, 1: WORLD1.*/
#define EXTMEM_CORE0_IBUS_WORLD (BIT(3))
#define EXTMEM_CORE0_IBUS_WORLD_M (BIT(3))
#define EXTMEM_CORE0_IBUS_WORLD_V 0x1
#define EXTMEM_CORE0_IBUS_WORLD_S 3
/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati
on fail. 0: invalidate, 1: execute-able, 2: read-able.*/
#define EXTMEM_CORE0_IBUS_ATTR 0x00000007
#define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
#define EXTMEM_CORE0_IBUS_ATTR_V 0x7
#define EXTMEM_CORE0_IBUS_ATTR_S 0
#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x9C)
/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: The bits are used to indicate the virtual address of CPU access ibus when authe
ntication fail..*/
#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF
#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF
#define EXTMEM_CORE0_IBUS_VADDR_S 0
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0xA0)
/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */
/*description: The right-most 3 bits are used to indicate the operations which cause mmu fault
occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
7: external dma rx. The most significant bit is used to indicate this operation
occurs in which one icache..*/
#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F
#define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF
#define EXTMEM_CACHE_MMU_FAULT_CODE_S 10
/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/
#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000000FF
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0xFF
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0
#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0xA4)
/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The bits are used to indicate the virtual address which cause mmu fault...*/
#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF
#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF
#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0
#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0xA8)
/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable wrap around mode when read data from flash..*/
#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0))
#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0))
#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1
#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0
#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0xAC)
/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2))
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2))
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2
/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1))
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1))
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1
/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to enable clock gating to save power when access mmu memory, 0:
enable, 1: disable.*/
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0))
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0))
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0
#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0xB0)
/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */
/*description: The bit is used to indicate whether icache main fsm is in idle state or not. 1:
in idle state, 0: not in idle state.*/
#define EXTMEM_ICACHE_STATE 0x00000FFF
#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
#define EXTMEM_ICACHE_STATE_V 0xFFF
#define EXTMEM_ICACHE_STATE_S 0
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0xB4)
/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Reserved..*/
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1))
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1))
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1
/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Reserved..*/
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0))
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0))
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0xB8)
/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: The bit is used to close clock gating of external memory encrypt and decrypt clo
ck. 1: close gating, 0: open clock gating..*/
#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2))
#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2))
#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1
#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2
/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating,
0: open clock gating..*/
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1))
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1))
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1
/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
open clock gating..*/
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0))
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0))
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0
#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xBC)
/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to clear the interrupt by icache pre-load done..*/
#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2))
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2))
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2
/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable the interrupt by icache pre-load done..*/
#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1))
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1
/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt by icache pre-load done..*/
#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0))
#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0))
#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1
#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0
#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0xC0)
/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to clear the interrupt by icache sync done..*/
#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2))
#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2))
#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1
#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2
/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to enable the interrupt by icache sync done..*/
#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1))
#define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1))
#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1
#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1
/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to indicate the interrupt by icache sync done..*/
#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0))
#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0))
#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1
#define EXTMEM_ICACHE_SYNC_INT_ST_S 0
#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0xC4)
/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus.*/
#define EXTMEM_CACHE_MMU_OWNER 0x0000000F
#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
#define EXTMEM_CACHE_MMU_OWNER_V 0xF
#define EXTMEM_CACHE_MMU_OWNER_S 0
#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0xC8)
/* EXTMEM_CACHE_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB.*/
#define EXTMEM_CACHE_MMU_PAGE_SIZE 0x00000003
#define EXTMEM_CACHE_MMU_PAGE_SIZE_M ((EXTMEM_CACHE_MMU_PAGE_SIZE_V)<<(EXTMEM_CACHE_MMU_PAGE_SIZE_S))
#define EXTMEM_CACHE_MMU_PAGE_SIZE_V 0x3
#define EXTMEM_CACHE_MMU_PAGE_SIZE_S 3
/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: The bit is used to enable cache trace function..*/
#define EXTMEM_CACHE_TRACE_ENA (BIT(2))
#define EXTMEM_CACHE_TRACE_ENA_M (BIT(2))
#define EXTMEM_CACHE_TRACE_ENA_V 0x1
#define EXTMEM_CACHE_TRACE_ENA_S 2
/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: The bit is used to disable checking mmu entry fault by sync operation..*/
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1))
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1))
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1
/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to disable checking mmu entry fault by preload operation..*/
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0))
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0))
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0
#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0xCC)
/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The bit is used to indicate icache freeze success.*/
#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2))
#define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2))
#define EXTMEM_ICACHE_FREEZE_DONE_V 0x1
#define EXTMEM_ICACHE_FREEZE_DONE_S 2
/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert
hit if CPU miss.*/
#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1))
#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1))
#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1
#define EXTMEM_ICACHE_FREEZE_MODE_S 1
/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to enable icache freeze mode.*/
#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0))
#define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0))
#define EXTMEM_ICACHE_FREEZE_ENA_V 0x1
#define EXTMEM_ICACHE_FREEZE_ENA_S 0
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0xD0)
/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: The bit is used to activate icache atomic operation protection. In this case, sy
nc/lock operation can not interrupt miss-work. This feature does not work during
invalidateAll operation..*/
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0))
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0))
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0
#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0xD4)
/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The bit is used to disable request recording which could cause performance issue.*/
#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0))
#define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0))
#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1
#define EXTMEM_CACHE_REQUEST_BYPASS_S 0
#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100)
/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock gate enable..*/
#define EXTMEM_CLK_EN (BIT(0))
#define EXTMEM_CLK_EN_M (BIT(0))
#define EXTMEM_CLK_EN_V 0x1
#define EXTMEM_CLK_EN_S 0
#define EXTMEM_REG_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC)
/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2107050 ; */
/*description: version information.*/
#define EXTMEM_DATE 0x0FFFFFFF
#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
#define EXTMEM_DATE_V 0xFFFFFFF
#define EXTMEM_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_EXTMEM_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
/* Some of the RF frontend control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE_IQ_EST_FORCE_PD (BIT(4))
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
#define FE_IQ_EST_FORCE_PD_V 1
#define FE_IQ_EST_FORCE_PD_S 4
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
#define FE2_TX_INF_FORCE_PU (BIT(10))
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
#define FE2_TX_INF_FORCE_PU_V 1
#define FE2_TX_INF_FORCE_PU_S 10
#define FE2_TX_INF_FORCE_PD (BIT(9))
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
#define FE2_TX_INF_FORCE_PD_V 1
#define FE2_TX_INF_FORCE_PD_S 9

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UART0 (2)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GDMA_STRUCT_H_
#define _SOC_GDMA_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct gdma_dev_s {
struct {
union {
struct {
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t infifo_ovf : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_t outfifo_ovf : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} raw;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_ovf : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} st;
union {
struct {
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_ovf : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} ena;
union {
struct {
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_ovf : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} clr;
} intr[1];
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
uint32_t reserved_1c;
uint32_t reserved_20;
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
union {
struct {
uint32_t ahb_testmode : 3; /*reserved*/
uint32_t reserved3 : 1; /*reserved*/
uint32_t ahb_testaddr : 2; /*reserved*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} ahb_test;
union {
struct {
uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/
uint32_t reserved1 : 1;
uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/
uint32_t clk_en : 1; /*reg_clk_en*/
uint32_t reserved4 : 28;
};
uint32_t val;
} misc_conf;
uint32_t date;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
struct {
struct {
union {
struct {
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_t in_loop_test : 1; /*reserved*/
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} in_conf0;
union {
struct {
uint32_t reserved0 : 12;
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} in_conf1;
union {
struct {
uint32_t infifo_full : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
uint32_t infifo_empty : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_t infifo_cnt : 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_t reserved8 : 15; /*reserved*/
uint32_t in_remain_under_1b : 1; /*reserved*/
uint32_t in_remain_under_2b : 1; /*reserved*/
uint32_t in_remain_under_3b : 1; /*reserved*/
uint32_t in_remain_under_4b : 1; /*reserved*/
uint32_t in_buf_hungry : 1; /*reserved*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} infifo_status;
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} in_pop;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} in_link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} in_state;
uint32_t in_suc_eof_des_addr;
uint32_t in_err_eof_des_addr;
uint32_t in_dscr;
uint32_t in_dscr_bf0;
uint32_t in_dscr_bf1;
union {
struct {
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} in_pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} in_peri_sel;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
} in;
struct {
union {
struct {
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
uint32_t reserved6 : 26;
};
uint32_t val;
} out_conf0;
union {
struct {
uint32_t reserved0 : 12;
uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} out_conf1;
union {
struct {
uint32_t outfifo_full : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
uint32_t outfifo_empty : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_t outfifo_cnt : 6; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
uint32_t reserved8 : 15; /*reserved*/
uint32_t out_remain_under_1b : 1; /*reserved*/
uint32_t out_remain_under_2b : 1; /*reserved*/
uint32_t out_remain_under_3b : 1; /*reserved*/
uint32_t out_remain_under_4b : 1; /*reserved*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} outfifo_status;
union {
struct {
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} out_push;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */
uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
uint32_t reserved24 : 8;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t out_dscr_state : 2; /*reserved*/
uint32_t out_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} out_state;
uint32_t out_eof_des_addr;
uint32_t out_eof_bfr_des_addr;
uint32_t out_dscr;
uint32_t out_dscr_bf0;
uint32_t out_dscr_bf1;
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} out_pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} out_peri_sel;
} out;
} channel[1];
} gdma_dev_t;
extern gdma_dev_t GDMA;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_DMA_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x1E)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x1F)
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_IDX 4
#define SPICS0_OUT_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define SPIQ_MONITOR_IDX 15
#define SPID_MONITOR_IDX 16
#define SPIHD_MONITOR_IDX 17
#define SPIWP_MONITOR_IDX 18
#define SPICS1_OUT_IDX 19
#define CPU_TESTBUS0_IDX 20
#define CPU_TESTBUS1_IDX 21
#define CPU_TESTBUS2_IDX 22
#define CPU_TESTBUS3_IDX 23
#define CPU_TESTBUS4_IDX 24
#define CPU_TESTBUS5_IDX 25
#define CPU_TESTBUS6_IDX 26
#define CPU_TESTBUS7_IDX 27
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define EXT_ADC_START_IDX 45
#define LEDC_LS_SIG_OUT0_IDX 45
#define LEDC_LS_SIG_OUT1_IDX 46
#define LEDC_LS_SIG_OUT2_IDX 47
#define LEDC_LS_SIG_OUT3_IDX 48
#define LEDC_LS_SIG_OUT4_IDX 49
#define LEDC_LS_SIG_OUT5_IDX 50
#define RMT_SIG_IN0_IDX 51
#define RMT_SIG_OUT0_IDX 51
#define RMT_SIG_IN1_IDX 52
#define RMT_SIG_OUT1_IDX 52
#define I2CEXT0_SCL_IN_IDX 53
#define I2CEXT0_SCL_OUT_IDX 53
#define I2CEXT0_SDA_IN_IDX 54
#define I2CEXT0_SDA_OUT_IDX 54
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_IDX 63
#define FSPIQ_IN_IDX 64
#define FSPIQ_OUT_IDX 64
#define FSPID_IN_IDX 65
#define FSPID_OUT_IDX 65
#define FSPIHD_IN_IDX 66
#define FSPIHD_OUT_IDX 66
#define FSPIWP_IN_IDX 67
#define FSPIWP_OUT_IDX 67
#define FSPICS0_IN_IDX 68
#define FSPICS0_OUT_IDX 68
#define FSPICS1_OUT_IDX 69
#define FSPICS2_OUT_IDX 70
#define FSPICS3_OUT_IDX 71
#define FSPICS4_OUT_IDX 72
#define FSPICS5_OUT_IDX 73
#define EXTERN_PRIORITY_I_IDX 77
#define EXTERN_PRIORITY_O_IDX 77
#define EXTERN_ACTIVE_I_IDX 78
#define EXTERN_ACTIVE_O_IDX 78
#define GPIO_EVENT_MATRIX_IN0_IDX 79
#define GPIO_TASK_MATRIX_OUT0_IDX 79
#define GPIO_EVENT_MATRIX_IN1_IDX 80
#define GPIO_TASK_MATRIX_OUT1_IDX 80
#define GPIO_EVENT_MATRIX_IN2_IDX 81
#define GPIO_TASK_MATRIX_OUT2_IDX 81
#define GPIO_EVENT_MATRIX_IN3_IDX 82
#define GPIO_TASK_MATRIX_OUT3_IDX 82
#define BB_DIAG8_OUT_IDX 83
#define BB_DIAG9_OUT_IDX 84
#define BB_DIAG10_OUT_IDX 85
#define BB_DIAG11_OUT_IDX 86
#define BB_DIAG12_OUT_IDX 87
#define BB_DIAG13_OUT_IDX 88
#define ANT_SEL0_IDX 89
#define ANT_SEL1_IDX 90
#define ANT_SEL2_IDX 91
#define ANT_SEL3_IDX 92
#define ANT_SEL4_IDX 93
#define ANT_SEL5_IDX 94
#define ANT_SEL6_IDX 95
#define ANT_SEL7_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define BLE_DBG_SYNCERR_IDX 101
#define BLE_DBG_SYNC_FOUND_IDX 102
#define BLE_DBG_CH_IDX_IDX 103
#define BLE_DBG_SYNC_WINDOW_IDX 104
#define BLE_DBG_DATA_EN_IDX 105
#define BLE_DBG_DATA_IDX 106
#define BLE_DBG_PKT_TX_ON_IDX 107
#define BLE_DBG_PKT_RX_ON_IDX 108
#define BLE_DBG_TXRU_ON_IDX 109
#define BLE_DBG_RXRU_ON_IDX 110
#define BLE_DBG_LELC_ST0_IDX 111
#define BLE_DBG_LELC_ST1_IDX 112
#define BLE_DBG_LELC_ST2_IDX 113
#define BLE_DBG_LELC_ST3_IDX 114
#define BLE_DBG_CRCOK_IDX 115
#define BLE_DBG_CLK_GPIO_IDX 116
#define BLE_DBG_RADIO_START_IDX 117
#define BLE_DBG_SEQUENCE_ON_IDX 118
#define BLE_DBG_COEX_BT_ON_IDX 119
#define BLE_DBG_COEX_WIFI_ON_IDX 120
#define CLK_OUT_OUT1_IDX 123
#define CLK_OUT_OUT2_IDX 124
#define CLK_OUT_OUT3_IDX 125
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2106190
#endif /* _SOC_GPIO_SIG_MAP_H_ */

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration register */
/** Type of bt_select register
* GPIO bit select register
*/
typedef union {
struct {
/** bt_sel : R/W; bitpos: [31:0]; default: 0;
* GPIO bit select register
*/
uint32_t bt_sel:32;
};
uint32_t val;
} gpio_bt_select_reg_t;
/** Type of out register
* GPIO output register
*/
typedef union {
struct {
/** out_data_orig : R/W/SS; bitpos: [24:0]; default: 0;
* GPIO output register for GPIO0-24
*/
uint32_t out_data_orig:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_out_reg_t;
/** Type of out_w1ts register
* GPIO output set register
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [24:0]; default: 0;
* GPIO output set register for GPIO0-24
*/
uint32_t out_w1ts:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* GPIO output clear register
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [24:0]; default: 0;
* GPIO output clear register for GPIO0-24
*/
uint32_t out_w1tc:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_out_w1tc_reg_t;
/** Type of sdio_select register
* GPIO sdio select register
*/
typedef union {
struct {
/** sdio_sel : R/W; bitpos: [7:0]; default: 0;
* GPIO sdio select register
*/
uint32_t sdio_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_sdio_select_reg_t;
/** Type of enable register
* GPIO output enable register
*/
typedef union {
struct {
/** enable_data : R/W/SS; bitpos: [24:0]; default: 0;
* GPIO output enable register for GPIO0-24
*/
uint32_t enable_data:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_enable_reg_t;
/** Type of enable_w1ts register
* GPIO output enable set register
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [24:0]; default: 0;
* GPIO output enable set register for GPIO0-24
*/
uint32_t enable_w1ts:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* GPIO output enable clear register
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [24:0]; default: 0;
* GPIO output enable clear register for GPIO0-24
*/
uint32_t enable_w1tc:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_enable_w1tc_reg_t;
/** Type of strap register
* pad strapping register
*/
typedef union {
struct {
/** strapping : RO; bitpos: [15:0]; default: 0;
* pad strapping register
*/
uint32_t strapping:16;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_strap_reg_t;
/** Type of in register
* GPIO input register
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [24:0]; default: 0;
* GPIO input register for GPIO0-24
*/
uint32_t in_data_next:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_in_reg_t;
/** Type of status register
* GPIO interrupt status register
*/
typedef union {
struct {
/** status_interrupt : R/W/SS; bitpos: [24:0]; default: 0;
* GPIO interrupt status register for GPIO0-24
*/
uint32_t status_interrupt:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status_reg_t;
/** Type of status_w1ts register
* GPIO interrupt status set register
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [24:0]; default: 0;
* GPIO interrupt status set register for GPIO0-24
*/
uint32_t status_w1ts:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* GPIO interrupt status clear register
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [24:0]; default: 0;
* GPIO interrupt status clear register for GPIO0-24
*/
uint32_t status_w1tc:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_status_w1tc_reg_t;
/** Type of pcpu_int register
* GPIO PRO_CPU interrupt status register
*/
typedef union {
struct {
/** procpu_int : RO; bitpos: [24:0]; default: 0;
* GPIO PRO_CPU interrupt status register for GPIO0-24
*/
uint32_t procpu_int:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_pcpu_int_reg_t;
/** Type of pcpu_nmi_int register
* GPIO PRO_CPU(not shielded) interrupt status register
*/
typedef union {
struct {
/** procpu_nmi_int : RO; bitpos: [24:0]; default: 0;
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24
*/
uint32_t procpu_nmi_int:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_pcpu_nmi_int_reg_t;
/** Type of cpusdio_int register
* GPIO CPUSDIO interrupt status register
*/
typedef union {
struct {
/** sdio_int : RO; bitpos: [24:0]; default: 0;
* GPIO CPUSDIO interrupt status register for GPIO0-24
*/
uint32_t sdio_int:25;
uint32_t reserved_25:7;
};
uint32_t val;
} gpio_cpusdio_int_reg_t;
/** Type of pin0 register
* GPIO pin configuration register
*/
typedef union {
struct {
/** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync2_bypass:2;
/** pad_driver : R/W; bitpos: [2]; default: 0;
* set this bit to select pad driver. 1:open-drain. 0:normal.
*/
uint32_t pad_driver:1;
/** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync1_bypass:2;
uint32_t reserved_5:2;
/** int_type : R/W; bitpos: [9:7]; default: 0;
* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
* at high level
*/
uint32_t int_type:3;
/** wakeup_enable : R/W; bitpos: [10]; default: 0;
* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
*/
uint32_t wakeup_enable:1;
/** config : R/W; bitpos: [12:11]; default: 0;
* reserved
*/
uint32_t config:2;
/** int_ena : R/W; bitpos: [17:13]; default: 0;
* set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
* interrupt.
*/
uint32_t int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin_reg_t;
/** Type of status_next register
* GPIO interrupt source register
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [25:0]; default: 0;
* GPIO interrupt source register for GPIO0-24
*/
uint32_t status_interrupt_next:26;
uint32_t reserved_26:6;
};
uint32_t val;
} gpio_status_next_reg_t;
/** Type of in_sel_cfg register
* GPIO input function configuration register
*/
typedef union {
struct {
/** in_sel : R/W; bitpos: [4:0]; default: 0;
* set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
* high level. s=0x3C: set this port always low level.
*/
uint32_t func_sel:5;
/** in_inv_sel : R/W; bitpos: [5]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
uint32_t sig_in_inv:1;
/** in_sel : R/W; bitpos: [6]; default: 0;
* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
*/
uint32_t sig_in_sel:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gpio_func_in_sel_cfg_reg_t;
/** Type of out_sel_cfg register
* GPIO output function select register
*/
typedef union {
struct {
/** out_sel : R/W; bitpos: [7:0]; default: 128;
* The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
* output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
* GPIO_OUT_REG[n].
*/
uint32_t func_sel:8;
/** out_inv_sel : R/W; bitpos: [8]; default: 0;
* set this bit to invert output signal.1:invert.0:not invert.
*/
uint32_t inv_sel:1;
/** oen_sel : R/W; bitpos: [9]; default: 0;
* set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
* enable signal.0:use peripheral output enable signal.
*/
uint32_t oen_sel:1;
/** oen_inv_sel : R/W; bitpos: [10]; default: 0;
* set this bit to invert output enable signal.1:invert.0:not invert.
*/
uint32_t oen_inv_sel:1;
uint32_t reserved_11:21;
};
uint32_t val;
} gpio_func_out_sel_cfg_reg_t;
/** Type of clock_gate_reg register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_clock_gate_reg_reg_t;
/** Type of reg_date_reg register
* GPIO version register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 34627984;
* version register
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_reg_date_reg_reg_t;
typedef struct {
volatile gpio_bt_select_reg_t bt_select;
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;
volatile gpio_out_w1tc_reg_t out_w1tc;
uint32_t reserved_010[3];
volatile gpio_sdio_select_reg_t sdio_select;
volatile gpio_enable_reg_t enable;
volatile gpio_enable_w1ts_reg_t enable_w1ts;
volatile gpio_enable_w1tc_reg_t enable_w1tc;
uint32_t reserved_02c[3];
volatile gpio_strap_reg_t strap;
volatile gpio_in_reg_t in;
uint32_t reserved_040;
volatile gpio_status_reg_t status;
volatile gpio_status_w1ts_reg_t status_w1ts;
volatile gpio_status_w1tc_reg_t status_w1tc;
uint32_t reserved_050[3];
volatile gpio_pcpu_int_reg_t pcpu_int;
volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
volatile gpio_cpusdio_int_reg_t cpusdio_int;
uint32_t reserved_068[3];
volatile gpio_pin_reg_t pin[25];
uint32_t reserved_0d8[29];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_150;
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128];
uint32_t reserved_354[128];
volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[25];
uint32_t reserved_5b8[29];
volatile gpio_clock_gate_reg_reg_t clock_gate_reg;
uint32_t reserved_630[51];
volatile gpio_reg_date_reg_reg_t reg_date_reg;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc.h"
#define SHA_MODE_SHA1 0
#define SHA_MODE_SHA224 1
#define SHA_MODE_SHA256 2
/* SHA acceleration registers */
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
#define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C)
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
#endif

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
/* INTERRUPT_CORE0_WIFI_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_M ((INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S))
#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_S 0
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
/* INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M ((INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S))
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0
#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
/* INTERRUPT_CORE0_WIFI_PWR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_M ((INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S))
#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_S 0
#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC)
/* INTERRUPT_CORE0_WIFI_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_WIFI_BB_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_M ((INTERRUPT_CORE0_WIFI_BB_INT_MAP_V)<<(INTERRUPT_CORE0_WIFI_BB_INT_MAP_S))
#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_WIFI_BB_INT_MAP_S 0
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0
#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1C)
/* INTERRUPT_CORE0_LP_TIMER_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_LP_TIMER_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_M ((INTERRUPT_CORE0_LP_TIMER_INT_MAP_V)<<(INTERRUPT_CORE0_LP_TIMER_INT_MAP_S))
#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_LP_TIMER_INT_MAP_S 0
#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S))
#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_COEX_INT_MAP_S 0
#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
/* INTERRUPT_CORE0_BLE_TIMER_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_M ((INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S))
#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_S 0
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S))
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2C)
/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3C)
/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_UART_INTR_MAP_S 0
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4C)
/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0
#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5C)
/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6C)
/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7C)
/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SHA_INT_MAP_S 0
#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8C)
/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ECC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_ECC_INT_MAP_M ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S))
#define INTERRUPT_CORE0_ECC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_ECC_INT_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9C)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA0)
/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA4)
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xA8)
/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xAC)
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB0)
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB4)
/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CLK_EN (BIT(0))
#define INTERRUPT_CORE0_CLK_EN_M (BIT(0))
#define INTERRUPT_CORE0_CLK_EN_V 0x1
#define INTERRUPT_CORE0_CLK_EN_S 0
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xB8)
/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xBC)
/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC0)
/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC4)
/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xC8)
/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xCC)
/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD0)
/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD4)
/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xD8)
/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xDC)
/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE0)
/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE4)
/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xE8)
/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xEC)
/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF0)
/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF4)
/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xF8)
/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xFC)
/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F
#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF
#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
/*description: Need add description.*/
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
#ifdef __cplusplus
}
#endif
#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "interrupt_core0_reg.h"

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_IO_MUX_REG_H_
#define _SOC_IO_MUX_REG_H_
#pragma once
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0TXD_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U0RXD_GPIO_NUM 19
#define U0TXD_GPIO_NUM 20
#define SPI_HD_GPIO_NUM 12
#define SPI_WP_GPIO_NUM 13
#define SPI_CS0_GPIO_NUM 14
#define SPI_CLK_GPIO_NUM 15
#define SPI_D_GPIO_NUM 16
#define SPI_Q_GPIO_NUM 17
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 20
#define MAX_GPIO_NUM 24
#define DIG_IO_HOLD_BIT_SHIFT 0
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x4)
#define FUNC_XTAL_32K_P_GPIO0 1
#define FUNC_XTAL_32K_P_GPIO0_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x8)
#define FUNC_XTAL_32K_N_GPIO1 1
#define FUNC_XTAL_32K_N_GPIO1_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0xC)
#define FUNC_GPIO2_FSPIQ 2
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14)
#define FUNC_MTMS_FSPIHD 2
#define FUNC_MTMS_GPIO4 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
#define FUNC_MTDI_FSPIWP 2
#define FUNC_MTDI_GPIO5 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1C)
#define FUNC_MTCK_FSPICLK 2
#define FUNC_MTCK_GPIO6 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20)
#define FUNC_MTDO_FSPID 2
#define FUNC_MTDO_GPIO7 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C)
#define FUNC_GPIO10_FSPICS0 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x30)
#define FUNC_VDD_SPI_GPIO11 1
#define FUNC_VDD_SPI_GPIO11_0 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x34)
#define FUNC_SPIHD_GPIO12 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x38)
#define FUNC_SPIWP_GPIO13 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x3C)
#define FUNC_SPICS0_GPIO14 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x40)
#define FUNC_SPICLK_GPIO15 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x44)
#define FUNC_SPID_GPIO16 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x48)
#define FUNC_SPIQ_GPIO17 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE + 0x4C)
#define FUNC_GPIO18_GPIO18 1
#define FUNC_GPIO18_GPIO18_0 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x50)
#define FUNC_U0RXD_GPIO19 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x54)
#define FUNC_U0TXD_GPIO20 1
#define FUNC_U0TXD_U0TXD 0
#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C
LK_OUT_out3 can be found in peripheral output signals..*/
#define IO_MUX_CLK_OUT3 0x0000000F
#define IO_MUX_CLK_OUT3_M ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
#define IO_MUX_CLK_OUT3_V 0xF
#define IO_MUX_CLK_OUT3_S 8
/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[7:4] ;default: 4'hf ; */
/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C
LK_OUT_out2 can be found in peripheral output signals..*/
#define IO_MUX_CLK_OUT2 0x0000000F
#define IO_MUX_CLK_OUT2_M ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
#define IO_MUX_CLK_OUT2_V 0xF
#define IO_MUX_CLK_OUT2_S 4
/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[3:0] ;default: 4'hf ; */
/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C
LK_OUT_out1 can be found in peripheral output signals..*/
#define IO_MUX_CLK_OUT1 0x0000000F
#define IO_MUX_CLK_OUT1_M ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
#define IO_MUX_CLK_OUT1_V 0xF
#define IO_MUX_CLK_OUT1_S 0
/* IO_MUX_DATE_REG : R/W ;bitpos:[27:0] ;default: 28'h2106190 ; */
/*description: Version control register.*/
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xFC)
#define IO_MUX_DATE_REG_M ((IO_MUX_DATE_REG_V)<<(IO_MUX_DATE_REG_S))
#define IO_MUX_DATE_REG_V 0xFFFFFFF
#define IO_MUX_DATE_REG_S 0
#endif

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
struct {
uint32_t timer_sel : 2; /*This field is used to select one of timers for channel $n.; ; 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3*/
uint32_t sig_out_en : 1; /*Set this bit to enable signal output on channel $n.*/
uint32_t idle_lv : 1; /*This bit is used to control the output value when channel $n is inactive (when LEDC_SIG_OUT_EN_CH$n is 0).*/
uint32_t low_speed_update : 1; /*This bit is used to update LEDC_HPOINT_CH$n, LEDC_DUTY_START_CH$n, LEDC_SIG_OUT_EN_CH$n, LEDC_TIMER_SEL_CH$n, LEDC_DUTY_NUM_CH$n, LEDC_DUTY_CYCLE_CH$n, LEDC_DUTY_SCALE_CH$n, LEDC_DUTY_INC_CH$n, and LEDC_OVF_CNT_EN_CH$n fields for channel $n, and will be automatically cleared by hardware.*/
uint32_t ovf_num : 10; /*This register is used to configure the maximum times of overflow minus 1.; ; The LEDC_OVF_CNT_CH$n_INT interrupt will be triggered when channel $n overflows for (LEDC_OVF_NUM_CH$n + 1) times.*/
uint32_t ovf_cnt_en : 1; /*This bit is used to enable the ovf_cnt of channel $n.*/
uint32_t ovf_cnt_rst : 1; /*Set this bit to reset the ovf_cnt of channel $n.*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} conf0;
union {
struct {
uint32_t hpoint : 14; /*The output value changes to high when the selected timers has reached the value specified by this register.*/
uint32_t reserved14 : 18; /*Reserved*/
};
uint32_t val;
} hpoint;
union {
struct {
uint32_t duty : 19; /*This register is used to change the output duty by controlling the Lpoint.; ; The output value turns to low when the selected timers has reached the Lpoint.*/
uint32_t reserved19 : 13; /*Reserved*/
};
uint32_t val;
} duty;
union {
struct {
uint32_t duty_scale : 10; /*This register is used to configure the changing step scale of duty on channel $n.*/
uint32_t duty_cycle : 10; /*The duty will change every LEDC_DUTY_CYCLE_CH$n on channel $n.*/
uint32_t duty_num : 10; /*This register is used to control the number of times the duty cycle will be changed.*/
uint32_t duty_inc : 1; /*This register is used to increase or decrease the duty of output signal on channel $n. 1: Increase; 0: Decrease.*/
uint32_t duty_start : 1; /*Other configured fields in LEDC_CH$n_CONF1_REG will start to take effect when this bit is set to 1.*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t duty_read : 19; /*This register stores the current duty of output signal on channel $n.*/
uint32_t reserved19 : 13; /*Reserved*/
};
uint32_t val;
} duty_rd;
} channel[6];
} channel_group[1];
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
struct {
struct {
union {
struct {
uint32_t duty_resolution : 4; /*This register is used to control the range of the counter in timer $x.*/
uint32_t clock_divider : 18; /*This register is used to configure the divisor for the divider in timer $x.; ; The least significant eight bits represent the fractional part.*/
uint32_t pause : 1; /*This bit is used to suspend the counter in timer $x.*/
uint32_t rst : 1; /*This bit is used to reset timer $x. The counter will show 0 after reset.*/
uint32_t tick_sel : 1; /*This bit is used to select clock for timer $x. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.; ; 1'h0: SLOW_CLK 1'h1: REF_TICK*/
uint32_t low_speed_update : 1; /*Set this bit to update LEDC_CLK_DIV_TIMER$x and LEDC_TIMER$x_DUTY_RES.*/
uint32_t reserved26 : 6; /*Reserved*/
};
uint32_t val;
} conf;
union {
struct {
uint32_t timer_cnt : 14; /*This register stores the current counter value of timer $x.*/
uint32_t reserved14 : 18; /*Reserved*/
};
uint32_t val;
} value;
} timer[4];
} timer_group[1];
union {
struct {
uint32_t lstimer0_ovf : 1; /*Triggered when the timer$x has reached its maximum counter value.*/
uint32_t lstimer1_ovf : 1; /*Triggered when the timer$x has reached its maximum counter value.*/
uint32_t lstimer2_ovf : 1; /*Triggered when the timer$x has reached its maximum counter value.*/
uint32_t lstimer3_ovf : 1; /*Triggered when the timer$x has reached its maximum counter value.*/
uint32_t duty_chng_end_ch0 : 1; /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
uint32_t duty_chng_end_ch1 : 1; /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
uint32_t duty_chng_end_ch2 : 1; /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
uint32_t duty_chng_end_ch3 : 1; /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
uint32_t duty_chng_end_ch4 : 1; /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
uint32_t duty_chng_end_ch5 : 1; /*Interrupt raw bit for channel $n. Triggered when the gradual change of duty has finished.*/
uint32_t ovf_cnt_ch0 : 1; /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
uint32_t ovf_cnt_ch1 : 1; /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
uint32_t ovf_cnt_ch2 : 1; /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
uint32_t ovf_cnt_ch3 : 1; /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
uint32_t ovf_cnt_ch4 : 1; /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
uint32_t ovf_cnt_ch5 : 1; /*Interrupt raw bit for channel $n. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH$n.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t lstimer0_ovf : 1; /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
uint32_t lstimer1_ovf : 1; /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
uint32_t lstimer2_ovf : 1; /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
uint32_t lstimer3_ovf : 1; /*This is the masked interrupt status bit for the LEDC_TIMER$x_OVF_INT interrupt when LEDC_TIMER$x_OVF_INT_ENA is set to 1.*/
uint32_t duty_chng_end_ch0 : 1; /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
uint32_t duty_chng_end_ch1 : 1; /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
uint32_t duty_chng_end_ch2 : 1; /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
uint32_t duty_chng_end_ch3 : 1; /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
uint32_t duty_chng_end_ch4 : 1; /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
uint32_t duty_chng_end_ch5 : 1; /*This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt when LEDC_DUTY_CHNG_END_CH$n_INT_ENAIS set to 1.*/
uint32_t ovf_cnt_ch0 : 1; /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
uint32_t ovf_cnt_ch1 : 1; /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
uint32_t ovf_cnt_ch2 : 1; /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
uint32_t ovf_cnt_ch3 : 1; /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
uint32_t ovf_cnt_ch4 : 1; /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
uint32_t ovf_cnt_ch5 : 1; /*This is the masked interrupt status bit for the LEDC_OVF_CNT_CH$n_INT interrupt when LEDC_OVF_CNT_CH$n_INT_ENA is set to 1.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t lstimer0_ovf : 1; /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t lstimer1_ovf : 1; /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t lstimer2_ovf : 1; /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t lstimer3_ovf : 1; /*The interrupt enable bit for the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t duty_chng_end_ch0 : 1; /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch1 : 1; /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch2 : 1; /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch3 : 1; /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch4 : 1; /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch5 : 1; /*The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch0 : 1; /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch1 : 1; /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch2 : 1; /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch3 : 1; /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch4 : 1; /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch5 : 1; /*The interrupt enable bit for the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t lstimer0_ovf : 1; /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t lstimer1_ovf : 1; /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t lstimer2_ovf : 1; /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t lstimer3_ovf : 1; /*Set this bit to clear the LEDC_TIMER$x_OVF_INT interrupt.*/
uint32_t duty_chng_end_ch0 : 1; /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch1 : 1; /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch2 : 1; /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch3 : 1; /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch4 : 1; /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t duty_chng_end_ch5 : 1; /*Set this bit to clear the LEDC_DUTY_CHNG_END_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch0 : 1; /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch1 : 1; /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch2 : 1; /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch3 : 1; /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch4 : 1; /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t ovf_cnt_ch5 : 1; /*Set this bit to clear the LEDC_OVF_CNT_CH$n_INT interrupt.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_clk_sel : 2; /*This bit is used to select clock source for the 4 timers .; ; 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK*/
uint32_t reserved2 : 29; /*Reserved*/
uint32_t clk_en : 1; /*This bit is used to control clock.; ; 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
};
uint32_t val;
} conf;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date;
} ledc_dev_t;
extern ledc_dev_t LEDC;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_LEDC_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/cache_memory.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 1
#define SOC_MMU_PAGES_PER_REGION 64
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
/* Some of the WiFi RX control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
#define NRX_CHAN_EST_FORCE_PU (BIT(7))
#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
#define NRX_CHAN_EST_FORCE_PU_V 1
#define NRX_CHAN_EST_FORCE_PU_S 7
#define NRX_CHAN_EST_FORCE_PD (BIT(6))
#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
#define NRX_CHAN_EST_FORCE_PD_V 1
#define NRX_CHAN_EST_FORCE_PD_S 6
#define NRX_RX_ROT_FORCE_PU (BIT(5))
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
#define NRX_RX_ROT_FORCE_PU_V 1
#define NRX_RX_ROT_FORCE_PU_S 5
#define NRX_RX_ROT_FORCE_PD (BIT(4))
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
#define NRX_RX_ROT_FORCE_PD_V 1
#define NRX_RX_ROT_FORCE_PD_S 4
#define NRX_VIT_FORCE_PU (BIT(3))
#define NRX_VIT_FORCE_PU_M (BIT(3))
#define NRX_VIT_FORCE_PU_V 1
#define NRX_VIT_FORCE_PU_S 3
#define NRX_VIT_FORCE_PD (BIT(2))
#define NRX_VIT_FORCE_PD_M (BIT(2))
#define NRX_VIT_FORCE_PD_V 1
#define NRX_VIT_FORCE_PD_S 2
#define NRX_DEMAP_FORCE_PU (BIT(1))
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
#define NRX_DEMAP_FORCE_PU_V 1
#define NRX_DEMAP_FORCE_PU_S 1
#define NRX_DEMAP_FORCE_PD (BIT(0))
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
#define NRX_DEMAP_FORCE_PD_V 1
#define NRX_DEMAP_FORCE_PD_S 0

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE, //No timg1 on esp8684, please remove TODO: IDF-3825
PERIPH_UHCI0_MODULE,
PERIPH_RMT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_SPI2_MODULE, //SPI2
PERIPH_TWAI_MODULE,
PERIPH_RNG_MODULE,
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_BT_BASEBAND_MODULE,
PERIPH_BT_LC_MODULE,
PERIPH_RSA_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_MODULE_MAX
} periph_module_t;
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_SOURCE, /**< interrupt of RWBT, level*/
ETS_COEX_SOURCE, /**< interrupt of RWBLE, level*/
ETS_BLE_TIMER_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
ETS_BLE_SEC_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_APB_CTRL_INTR_SOURCE, /**< interrupt of APB ctrl, ?*/
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE,
ETS_CACHE_CORE0_ACS_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_JTAG_RESET = 0x18,
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file rtc.h
* @brief Low-level RTC power, clock, and sleep functions.
*
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
* RTC_CNTL peripheral handles many functions:
* - enables/disables clocks and power to various parts of the chip; this is
* done using direct register access (forcing power up or power down) or by
* allowing state machines to control power and clocks automatically
* - handles sleep and wakeup functions
* - maintains a 48-bit counter which can be used for timekeeping
*
* These functions are not thread safe, and should not be viewed as high level
* APIs. For example, while this file provides a function which can switch
* CPU frequency, this function is on its own is not sufficient to implement
* frequency switching in ESP-IDF context: some coordination with RTOS,
* peripheral drivers, and WiFi/BT stacks is also required.
*
* These functions will normally not be used in applications directly.
* ESP-IDF provides, or will provide, drivers and other facilities to use
* RTC subsystem functionality.
*
* The functions are loosely split into the following groups:
* - rtc_clk: clock switching, calibration
* - rtc_time: reading RTC counter, conversion between counter values and time
* - rtc_sleep: entry into sleep modes
* - rtc_init: initialization
*/
#define MHZ (1000000)
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_FREQ_150K 150000
#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256)
#define RTC_SLOW_CLK_FREQ_32K 32768
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18
#define RTC_CNTL_DBIAS_1V05 20
#define RTC_CNTL_DBIAS_1V10 23
#define RTC_CNTL_DBIAS_1V15 25
#define RTC_CNTL_DBIAS_1V20 28
#define RTC_CNTL_DBIAS_1V25 30
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
#define DELAY_FAST_CLK_SWITCH 3
#define DELAY_SLOW_CLK_SWITCH 300
#define DELAY_8M_ENABLE 50
/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
* 10 cycles will take approximately 300 microseconds.
*/
#define XTAL_FREQ_EST_CYCLES 10
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
/*
set sleep_init default param
*/
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
storing in efuse (based on ATE 5k ECO3 chips)
*/
#define K_RTC_MID_MUL10000 215
#define K_DIG_MID_MUL10000 213
#define V_RTC_MID_MUL10000 10800
#define V_DIG_MID_MUL10000 10860
/**
* @brief Possible main XTAL frequency values.
*
* Enum values should be equal to frequency in MHz.
*/
typedef enum {
RTC_XTAL_FREQ_32M = 32,
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
/**
* @brief CPU frequency values
*/
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
RTC_CPU_320M_80M = 5, //!< for test
RTC_CPU_320M_160M = 6, //!< for test
RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
} rtc_cpu_freq_t;
/**
* @brief CPU clock source
*/
typedef enum {
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
RTC_CPU_FREQ_SRC_APLL //!< APLL
} rtc_cpu_freq_src_t;
/**
* @brief CPU clock configuration structure
*/
typedef struct rtc_cpu_freq_config_s {
rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived
uint32_t source_freq_mhz; //!< Source clock frequency
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
uint32_t freq_mhz; //!< CPU clock frequency
} rtc_cpu_freq_config_t;
/**
* @brief RTC SLOW_CLK frequency values
*/
typedef enum {
RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
} rtc_slow_freq_t;
/**
* @brief RTC FAST_CLK frequency values
*/
typedef enum {
RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
} rtc_fast_freq_t;
/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
#define RTC_FAST_CLK_FREQ_APPROX 8500000
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/**
* @brief Clock source to be calibrated using rtc_clk_cal function
*/
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
} rtc_cal_sel_t;
/**
* Initialization parameters for rtc_clk_init
*/
typedef struct {
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
} rtc_clk_config_t;
/**
* Default initializer for rtc_clk_config_t
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = RTC_XTAL_FREQ_40M, \
.cpu_freq_mhz = 80, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
}
typedef struct {
uint32_t dac : 6;
uint32_t dres : 3;
uint32_t dgm : 3;
uint32_t dbuf: 1;
} x32k_config_t;
#define X32K_CONFIG_DEFAULT() { \
.dac = 3, \
.dres = 3, \
.dgm = 3, \
.dbuf = 1, \
}
typedef struct {
uint16_t wifi_powerup_cycles : 7;
uint16_t wifi_wait_cycles : 9;
uint16_t bt_powerup_cycles : 7;
uint16_t bt_wait_cycles : 9;
uint16_t cpu_top_powerup_cycles : 7;
uint16_t cpu_top_wait_cycles : 9;
uint16_t dg_wrap_powerup_cycles : 7;
uint16_t dg_wrap_wait_cycles : 9;
uint16_t dg_peri_powerup_cycles : 7;
uint16_t dg_peri_wait_cycles : 9;
} rtc_init_config_t;
#define RTC_INIT_CONFIG_DEFAULT() { \
.wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
.bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.bt_wait_cycles = OTHER_BLOCKS_WAIT, \
.cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
.dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
.dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
.dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
}
void rtc_clk_divider_set(uint32_t div);
void rtc_clk_8m_divider_set(uint32_t div);
/**
* Initialize clocks and set CPU frequency
*
* @param cfg clock configuration as rtc_clk_config_t
*/
void rtc_clk_init(rtc_clk_config_t cfg);
/**
* @brief Get main XTAL frequency
*
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
* rtc_clk_init function
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
/**
* @brief Update XTAL frequency
*
* Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
* after startup.
*
* @param xtal_freq New frequency value
*/
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
/**
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
*/
void rtc_clk_32k_enable_external(void);
/**
* @brief Get the state of 32k XTAL oscillator
* @return true if 32k XTAL oscillator has been enabled
*/
bool rtc_clk_32k_enabled(void);
/**
* @brief Enable 32k oscillator, configuring it for fast startup time.
* Note: to achieve higher frequency stability, rtc_clk_32k_enable function
* must be called one the 32k XTAL oscillator has started up. This function
* will initially disable the 32k XTAL oscillator, so it should not be called
* when the system is using 32k XTAL as RTC_SLOW_CLK.
*
* @param cycle Number of 32kHz cycles to bootstrap external crystal.
* If 0, no square wave will be used to bootstrap crystal oscillation.
*/
void rtc_clk_32k_bootstrap(uint32_t cycle);
/**
* @brief Enable or disable 8 MHz internal oscillator
*
* Output from 8 MHz internal oscillator is passed into a configurable
* divider, which by default divides the input clock frequency by 256.
* Output of the divider may be used as RTC_SLOW_CLK source.
* Output of the divider is referred to in register descriptions and code as
* 8md256 or simply d256. Divider values other than 256 may be configured, but
* this facility is not currently needed, so is not exposed in the code.
*
* When 8MHz/256 divided output is not needed, the divider should be disabled
* to reduce power consumption.
*
* @param clk_8m_en true to enable 8MHz generator
* @param d256_en true to enable /256 divider
*/
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
/**
* @brief Get the state of 8 MHz internal oscillator
* @return true if the oscillator is enabled
*/
bool rtc_clk_8m_enabled(void);
/**
* @brief Get the state of /256 divider which is applied to 8MHz clock
* @return true if the divided output is enabled
*/
bool rtc_clk_8md256_enabled(void);
/**
* @brief Enable or disable APLL
*
* Output frequency is given by the formula:
* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
*
* The dividend in this expression should be in the range of 240 - 600 MHz.
*
* In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
*
* @param enable true to enable, false to disable
* @param sdm0 frequency adjustment parameter, 0..255
* @param sdm1 frequency adjustment parameter, 0..255
* @param sdm2 frequency adjustment parameter, 0..63
* @param o_div frequency divider, 0..31
*/
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
/**
* @brief Select source for RTC_SLOW_CLK
* @param slow_freq clock source (one of rtc_slow_freq_t values)
*/
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
/**
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of rtc_slow_freq_t values)
*/
rtc_slow_freq_t rtc_clk_slow_freq_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
*
* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
*
* rtc_clk_cal function can be used to get more precise value by comparing
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
*
* @return RTC_SLOW_CLK frequency, in Hz
*/
uint32_t rtc_clk_slow_freq_get_hz(void);
/**
* @brief Select source for RTC_FAST_CLK
* @param fast_freq clock source (one of rtc_fast_freq_t values)
*/
void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
/**
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of rtc_fast_freq_t values)
*/
rtc_fast_freq_t rtc_clk_fast_freq_get(void);
/**
* @brief Get CPU frequency config for a given frequency
* @param freq_mhz Frequency in MHz
* @param[out] out_config Output, CPU frequency configuration structure
* @return true if frequency can be obtained, false otherwise
*/
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
/**
* @brief Switch CPU frequency
*
* This function sets CPU frequency according to the given configuration
* structure. It enables PLLs, if necessary.
*
* @note This function in not intended to be called by applications in FreeRTOS
* environment. This is because it does not adjust various timers based on the
* new CPU frequency.
*
* @param config CPU frequency configuration structure
*/
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
/**
* @brief Switch CPU frequency (optimized for speed)
*
* This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
* It works faster because it does not disable PLLs when switching from PLL to
* XTAL and does not enabled them when switching back. If PLL is not already
* enabled when this function is called to switch from XTAL to PLL frequency,
* or the PLL which is enabled is the wrong one, this function will fall back
* to calling rtc_clk_cpu_freq_set_config.
*
* Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
* so it is less safe to use it e.g. from a panic handler (when memory might
* be corrupted).
*
* @note This function in not intended to be called by applications in FreeRTOS
* environment. This is because it does not adjust various timers based on the
* new CPU frequency.
*
* @param config CPU frequency configuration structure
*/
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
/**
* @brief Get the currently used CPU frequency configuration
* @param[out] out_config Output, CPU frequency configuration structure
*/
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
/**
* @brief Switch CPU clock source to XTAL
*
* Short form for filling in rtc_cpu_freq_config_t structure and calling
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*/
void rtc_clk_cpu_freq_set_xtal(void);
/**
* @brief Store new APB frequency value into RTC_APB_FREQ_REG
*
* This function doesn't change any hardware clocks.
*
* Functions which perform frequency switching and change APB frequency call
* this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
* (one of RTC general purpose retention registers). This should not normally
* be called from application code.
*
* @param apb_freq new APB frequency, in Hz
*/
void rtc_clk_apb_freq_update(uint32_t apb_freq);
/**
* @brief Get the current stored APB frequency.
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
*/
uint32_t rtc_clk_apb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
* @brief Measure RTC slow clock's period, based on main XTAL frequency
*
* This function will time out and return 0 if the time for the given number
* of cycles to be counted exceeds the expected time twice. This may happen if
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
*
* @param cal_clk clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
/**
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
* @param cal_clk slow clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average ratio between XTAL frequency and slow clock frequency,
* Q13.19 fixed point format, or 0 if calibration has timed out.
*/
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
* @param time_in_us Time interval in microseconds
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
* fixed point format (as returned by rtc_slowck_cali).
* @return number of slow clock cycles
*/
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
/**
* @brief Convert time interval from RTC_SLOW_CLK to microseconds
* @param time_in_us Time interval in RTC_SLOW_CLK cycles
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
* fixed point format (as returned by rtc_slowck_cali).
* @return time interval in microseconds
*/
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
/**
* @brief Get current value of RTC counter
*
* RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
* cycles. Counter value is not writable by software. The value is not adjusted
* when switching to a different RTC_SLOW_CLK source.
*
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
*
* @return current value of RTC counter
*/
uint64_t rtc_time_get(void);
uint64_t rtc_light_slp_time_get(void);
uint64_t rtc_deep_slp_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief Enable the rtc digital 8M clock
*
* This function is used to enable the digital rtc 8M clock to support peripherals.
* For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
*/
void rtc_dig_clk8m_enable(void);
/**
* @brief Disable the rtc digital 8M clock
*
* This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
* @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
* @return Frequency of the clock in Hz
*/
uint32_t rtc_clk_freq_cal(uint32_t cal_val);
/**
* @brief Power down flags for rtc_sleep_pd function
*/
typedef struct {
uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep
uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep
uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep
uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep
uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep
uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
} rtc_sleep_pu_config_t;
/**
* Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
*/
#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
.dig_fpu = (val), \
.rtc_fpu = (val), \
.cpu_fpu = (val), \
.i2s_fpu = (val), \
.bb_fpu = (val), \
.nrx_fpu = (val), \
.fe_fpu = (val), \
.sram_fpu = (val), \
.rom_ram_fpu = (val), \
}
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
/**
* @brief sleep configuration for rtc_sleep_init function
*/
typedef struct {
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t bt_pd_en : 1; //!< power down BT
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1;
} rtc_sleep_config_t;
/**
* Default initializer for rtc_sleep_config_t
*
* This initializer sets all fields to "reasonable" values (e.g. suggested for
* production use) based on a combination of RTC_SLEEP_PD_x flags.
*
* @param RTC_SLEEP_PD_x flags combined using bitwise OR
*/
#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG)
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
/**
* @brief Prepare the chip to enter sleep mode
*
* This function configures various power control state machines to handle
* entry into light sleep or deep sleep mode, switches APB and CPU clock source
* (usually to XTAL), and sets bias voltages for digital and RTC power domains.
*
* This function does not actually enter sleep mode; this is done using
* rtc_sleep_start function. Software may do some other actions between
* rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
* wakeup sources.
* @param cfg sleep mode configuration
*/
void rtc_sleep_init(rtc_sleep_config_t cfg);
/**
* @brief Low level initialize for rtc state machine waiting cycles after waking up
*
* This function configures the cycles chip need to wait for internal 8MHz
* oscillator and external 40MHz crystal. As we configure fixed time for waiting
* crystal, we need to pass period to calculate cycles. Now this function only
* used in lightsleep mode.
*
* @param slowclk_period re-calibrated slow clock period
*/
void rtc_sleep_low_init(uint32_t slowclk_period);
/**
* @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
* @param t value of RTC counter at which wakeup from sleep will happen;
* only the lower 48 bits are used
*/
void rtc_sleep_set_wakeup_time(uint64_t t);
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
#define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only)
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
#define RTC_USB_TRIG_EN BIT(14)
#define RTC_BROWNOUT_DET_TRIG_EN BIT(16)
/**
* @brief Enter deep or light sleep mode
*
* This function enters the sleep mode previously configured using rtc_sleep_init
* function. Before entering sleep, software should configure wake up sources
* appropriately (set up GPIO wakeup registers, timer wakeup registers,
* and so on).
*
* If deep sleep mode was configured using rtc_sleep_init, and sleep is not
* rejected by hardware (based on reject_opt flags), this function never returns.
* When the chip wakes up from deep sleep, CPU is reset and execution starts
* from ROM bootloader.
*
* If light sleep mode was configured using rtc_sleep_init, this function
* returns on wakeup, or if sleep is rejected by hardware.
*
* @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
* combined with OR)
* @param reject_opt bit mask of sleep reject reasons:
* - RTC_CNTL_GPIO_REJECT_EN
* - RTC_CNTL_SDIO_REJECT_EN
* These flags are used to prevent entering sleep when e.g.
* an external host is communicating via SDIO slave
* @return non-zero if sleep was rejected by hardware
*/
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
/**
* @brief Enter deep sleep mode
*
* Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value
* of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake
* stub is valid to execute (if a wake address is set).
*
* No RAM is accessed while calculating the CRC and going into deep sleep, which makes
* this function safe to use even if the caller's stack is in RTC FAST memory.
*
* @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will
* have the same effect and takes less time as CRC calculation is skipped.
*
* @note This function should only be called after rtc_sleep_init() has been called to
* configure the system for deep sleep.
*
* @param wakeup_opt - same as for rtc_sleep_start
* @param reject_opt - same as for rtc_sleep_start
*
* @return non-zero if sleep was rejected by hardware
*/
uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
/**
* RTC power and clock control initialization settings
*/
typedef struct {
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
uint32_t cpu_waiti_clk_gate : 1;
uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise.
} rtc_config_t;
/**
* Default initializer of rtc_config_t.
*
* This initializer sets all fields to "reasonable" values (e.g. suggested for
* production use).
*/
#define RTC_CONFIG_DEFAULT() {\
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
.clkctl_init = 1, \
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1, \
.cali_ocode = 0\
}
/**
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
void rtc_init(rtc_config_t cfg);
/**
* Structure describing vddsdio configuration
*/
typedef struct {
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
uint32_t enable : 1; //!< Enable VDDSDIO regulator
uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator
uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator
uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator
} rtc_vddsdio_config_t;
/**
* Get current VDDSDIO configuration
* If VDDSDIO configuration is overridden by RTC, get values from RTC
* Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
* Otherwise, use default values and the level of MTDI bootstrapping pin.
* @return currently used VDDSDIO configuration
*/
rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
/**
* Set new VDDSDIO configuration using RTC registers.
* If config.force == 1, this overrides configuration done using bootstrapping
* pins and EFUSE.
*
* @param config new VDDSDIO configuration
*/
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct rtc_cntl_dev_s{
union {
struct {
uint32_t reserved0 : 2; /*Reserved*/
uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
uint32_t reserved4 : 1; /*Reserved*/
uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/
uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/
uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/
uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/
uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/
uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/
uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/
uint32_t xtl_force_pd : 1; /*crystall force power down*/
uint32_t xtl_force_pu : 1; /*crystall force power up*/
uint32_t xtl_en_wait : 4; /*wait bias_sleep and current source wakeup*/
uint32_t reserved18 : 2; /*Reserved*/
uint32_t ctr_sel : 3; /*Need add desc*/
uint32_t reserved23 : 2; /*Reserved*/
uint32_t analog_force_iso : 1; /*Need add desc*/
uint32_t reserved26 : 2; /*Reserved*/
uint32_t analog_force_noiso : 1; /*Need add desc*/
uint32_t dg_wrap_force_rst : 1; /*digital wrap force reset in deep sleep*/
uint32_t dg_wrap_force_norst : 1; /*digital core force no reset in deep sleep*/
uint32_t sw_sys_rst : 1; /*SW system reset*/
};
uint32_t val;
} options0;
uint32_t slp_timer0;
union {
struct {
uint32_t slp_val_hi : 16; /*RTC sleep timer high 16 bits*/
uint32_t main_timer_alarm_en : 1; /*timer alarm enable bit*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} slp_timer1;
union {
struct {
uint32_t reserved0 : 27; /*Reserved*/
uint32_t timer_sys_stall : 1; /*Enable to record system stall time*/
uint32_t timer_xtl_off : 1; /*Enable to record 40M XTAL OFF time*/
uint32_t timer_sys_rst : 1; /*enable to record system reset time*/
uint32_t reserved30 : 1; /*Reserved*/
uint32_t update : 1; /*Set 1: to update register with RTC timer*/
};
uint32_t val;
} time_update;
uint32_t time_low0;
union {
struct {
uint32_t rtc_timer_value0_high : 16; /*RTC timer high 16 bits*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} time_high0;
union {
struct {
uint32_t rtc_sw_cpu_int : 1; /*rtc software interrupt to main cpu*/
uint32_t rtc_slp_reject_cause_clr : 1; /*clear rtc sleep reject cause*/
uint32_t reserved2 : 20; /*Reserved*/
uint32_t apb2rtc_bridge_sel : 1; /*1: APB to RTC using bridge*/
uint32_t reserved23 : 5; /*Reserved*/
uint32_t sdio_active_ind : 1; /*SDIO active indication*/
uint32_t slp_wakeup : 1; /*leep wakeup bit*/
uint32_t slp_reject : 1; /*leep reject bit*/
uint32_t sleep_en : 1; /*sleep enable bit*/
};
uint32_t val;
} state0;
union {
struct {
uint32_t cpu_stall_en : 1; /*CPU stall enable bit*/
uint32_t cpu_stall_wait : 5; /*CPU stall wait cycles in fast_clk_rtc*/
uint32_t ck8m_wait : 8; /*CK8M wait cycles in slow_clk_rtc*/
uint32_t xtl_buf_wait : 10; /*XTAL wait cycles in slow_clk_rtc*/
uint32_t pll_buf_wait : 8; /*PLL wait cycles in slow_clk_rtc*/
};
uint32_t val;
} timer1;
union {
struct {
uint32_t reserved0 : 24; /*Reserved*/
uint32_t min_time_ck8m_off : 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
};
uint32_t val;
} timer2;
union {
struct {
uint32_t reserved0 : 16; /*Reserved*/
uint32_t dg_wrap_wait_timer : 9; /*Need add desc*/
uint32_t dg_wrap_powerup_timer : 7; /*Need add desc*/
};
uint32_t val;
} timer4;
union {
struct {
uint32_t reserved0 : 8; /*Reserved*/
uint32_t min_slp_val : 8; /*minimal sleep cycles in slow_clk_rtc*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} timer5;
union {
struct {
uint32_t reserved0 : 18; /*Reserved*/
uint32_t i2c_reset_por_force_pd : 1; /*Need add desc*/
uint32_t i2c_reset_por_force_pu : 1; /*Need add desc*/
uint32_t reserved20 : 2; /*ReservedPLLA force power down*/
uint32_t sar_i2c_pu : 1; /*PLLA force power up*/
uint32_t reserved23 : 2; /*Reserved*/
uint32_t bbpll_cal_slp_start : 1; /*start BBPLL calibration during sleep*/
uint32_t reserved26 : 1; /*Reserved*/
uint32_t txrf_i2c_pu : 1; /*1: TXRF_I2C power up*/
uint32_t rfrx_pbus_pu : 1; /*1: RFRX_PBUS power up*/
uint32_t reserved29 : 1; /*Reserved*/
uint32_t ckgen_i2c_pu : 1; /*1: CKGEN_I2C power up*/
uint32_t pll_i2c_pu : 1; /*Need add desc*/
};
uint32_t val;
} ana_conf;
union {
struct {
uint32_t reset_cause_procpu : 6; /*reset cause of PRO CPU*/
uint32_t reserved6 : 7; /*Reserved*/
uint32_t stat_vector_sel_procpu : 1; /*PRO CPU state vector sel*/
uint32_t reserved14 : 5; /*Reserved*/
uint32_t ocd_halt_on_reset_procpu : 1; /*PROCPU OcdHaltOnReset*/
uint32_t rtc_dreset_mask_procpu : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} reset_state;
union {
struct {
uint32_t reserved0 : 15; /*Reserved*/
uint32_t rtc_wakeup_ena : 17; /*wakeup enable bitmap*/
};
uint32_t val;
} wakeup_state;
union {
struct {
uint32_t slp_wakeup : 1; /*enable sleep wakeup interrupt*/
uint32_t slp_reject : 1; /*enable sleep reject interrupt*/
uint32_t reserved2 : 1; /*Reservedenable SDIO idle interrupt*/
uint32_t rtc_wdt : 1; /*enable RTC WDT interrupt*/
uint32_t reserved4 : 5; /*Reserved*/
uint32_t rtc_brown_out : 1; /*enable brown out interrupt*/
uint32_t rtc_main_timer : 1; /*enable RTC main timer interrupt*/
uint32_t reserved11 : 4; /*Reservedenable saradc2 interrupt*/
uint32_t rtc_swd : 1; /*enable super watch dog interrupt*/
uint32_t reserved16 : 4; /*Reservedenable touch timeout interrupt*/
uint32_t rtc_bbpll_cal : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t slp_wakeup : 1; /*sleep wakeup interrupt raw*/
uint32_t slp_reject : 1; /*sleep reject interrupt raw*/
uint32_t reserved2 : 1; /*ReservedSDIO idle interrupt raw*/
uint32_t rtc_wdt : 1; /*RTC WDT interrupt raw*/
uint32_t reserved4 : 5; /*Reservedtouch inactive interrupt raw*/
uint32_t rtc_brown_out : 1; /*brown out interrupt raw*/
uint32_t rtc_main_timer : 1; /*RTC main timer interrupt raw*/
uint32_t reserved11 : 4; /*Reservedsaradc2 interrupt raw*/
uint32_t rtc_swd : 1; /*super watch dog interrupt raw*/
uint32_t reserved16 : 4; /*Reservedtouch timeout interrupt raw*/
uint32_t rtc_bbpll_cal : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t slp_wakeup : 1; /*sleep wakeup interrupt state*/
uint32_t slp_reject : 1; /*sleep reject interrupt state*/
uint32_t reserved2 : 1; /*Reserved*/
uint32_t rtc_wdt : 1; /*RTC WDT interrupt state*/
uint32_t reserved4 : 5; /*Reserved*/
uint32_t rtc_brown_out : 1; /*brown out interrupt state*/
uint32_t rtc_main_timer : 1; /*RTC main timer interrupt state*/
uint32_t reserved11 : 4; /*Reserved*/
uint32_t rtc_swd : 1; /*super watch dog interrupt state*/
uint32_t reserved16 : 4; /*Reserved*/
uint32_t rtc_bbpll_cal : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t slp_wakeup : 1; /*Clear sleep wakeup interrupt state*/
uint32_t slp_reject : 1; /*Clear sleep reject interrupt state*/
uint32_t reserved2 : 1; /*Reserved*/
uint32_t rtc_wdt : 1; /*Clear RTC WDT interrupt state*/
uint32_t reserved4 : 5; /*Reserved*/
uint32_t rtc_brown_out : 1; /*Clear brown out interrupt state*/
uint32_t rtc_main_timer : 1; /*Clear RTC main timer interrupt state*/
uint32_t reserved11 : 4; /*Reserved*/
uint32_t rtc_swd : 1; /*Clear super watch dog interrupt state*/
uint32_t reserved16 : 4; /*Reserved*/
uint32_t rtc_bbpll_cal : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} int_clr;
uint32_t store[4];
union {
struct {
uint32_t reserved0 : 30; /*Reserved*/
uint32_t ctr_lv : 1; /*0: power down XTAL at high level*/
uint32_t ctr_en : 1; /*Need add desc*/
};
uint32_t val;
} ext_xtl_conf;
union {
struct {
uint32_t reserved0 : 31; /*Reserved*/
uint32_t gpio_wakeup_filter : 1; /*enable filter for gpio wakeup event*/
};
uint32_t val;
} ext_wakeup_conf;
union {
struct {
uint32_t reserved0 : 12; /*Reserved*/
uint32_t rtc_sleep_reject_ena : 18; /*sleep reject enable*/
uint32_t light_slp_reject_en : 1; /*enable reject for light sleep*/
uint32_t deep_slp_reject_en : 1; /*enable reject for deep sleep*/
};
uint32_t val;
} slp_reject_conf;
union {
struct {
uint32_t reserved0 : 29; /*Reserved*/
uint32_t cpusel_conf : 1; /*CPU sel option*/
uint32_t cpuperiod_sel : 2; /*Need add desc*/
};
uint32_t val;
} cpu_period_conf;
union {
struct {
uint32_t reserved0 : 1; /*Reserved*/
uint32_t efuse_clk_force_gating : 1; /*Need add desc*/
uint32_t efuse_clk_force_nogating : 1; /*Need add desc*/
uint32_t ck8m_div_sel_vld : 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
uint32_t ck8m_div : 2; /*CK8M_D256_OUT divider. 00: div128*/
uint32_t enb_ck8m : 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div : 1; /*1: CK8M_D256_OUT is actually CK8M*/
uint32_t dig_xtal32k_en : 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_d256_en : 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
uint32_t dig_clk8m_en : 1; /*enable CK8M for digital core (no relationship with RTC core)*/
uint32_t reserved11 : 1; /*Reserved*/
uint32_t ck8m_div_sel : 3; /*divider = reg_ck8m_div_sel + 1*/
uint32_t xtal_force_nogating : 1; /*XTAL force no gating during sleep*/
uint32_t ck8m_force_nogating : 1; /*CK8M force no gating during sleep*/
uint32_t ck8m_dfreq : 8; /*CK8M_DFREQ*/
uint32_t ck8m_force_pd : 1; /*CK8M force power down*/
uint32_t ck8m_force_pu : 1; /*CK8M force power up*/
uint32_t xtal_global_force_gating : 1; /*Need add desc*/
uint32_t xtal_global_force_nogating : 1; /*Need add desc*/
uint32_t fast_clk_rtc_sel : 1; /*fast_clk_rtc sel. 0: XTAL div 4*/
uint32_t ana_clk_rtc_sel : 2; /*Need add desc*/
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0 : 22; /*Reserved*/
uint32_t rtc_ana_clk_div_vld : 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
uint32_t rtc_ana_clk_div : 8; /*Need add desc*/
uint32_t slow_clk_next_edge : 1; /*Need add desc*/
};
uint32_t val;
} slow_clk_conf;
union {
struct {
uint32_t dg_vdd_drv_b_slp : 8; /*Need add desc*/
uint32_t dg_vdd_drv_b_slp_en : 1; /*Need add desc*/
uint32_t reserved9 : 1; /*Reserved*/
uint32_t bias_buf_idle : 1; /*Need add desc*/
uint32_t bias_buf_wake : 1; /*Need add desc*/
uint32_t bias_buf_deep_slp : 1; /*Need add desc*/
uint32_t bias_buf_monitor : 1; /*Need add desc*/
uint32_t pd_cur_deep_slp : 1; /*xpd cur when rtc in sleep_state*/
uint32_t pd_cur_monitor : 1; /*xpd cur when rtc in monitor state*/
uint32_t bias_sleep_deep_slp : 1; /*bias_sleep when rtc in sleep_state*/
uint32_t bias_sleep_monitor : 1; /*bias_sleep when rtc in monitor state*/
uint32_t dbg_atten_deep_slp : 4; /*DBG_ATTEN when rtc in sleep state*/
uint32_t dbg_atten_monitor : 4; /*DBG_ATTEN when rtc in active state*/
uint32_t dbg_atten_active : 4; /*Need add desc*/
uint32_t reserved30 : 2; /*Reserved*/
};
uint32_t val;
} bias_conf;
union {
struct {
uint32_t reserved0 : 7; /*Reserved*/
uint32_t dig_cal_en : 1; /*Need add desc*/
uint32_t reserved8 : 6; /*Reserved*/
uint32_t sck_dcap : 8; /*SCK_DCAP*/
uint32_t reserved22 : 8; /*Reserved*/
uint32_t rtculator_force_pd : 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
uint32_t rtculator_force_pu : 1; /*Need add desc*/
};
uint32_t val;
} rtc;
union {
struct {
uint32_t reserved0 : 21; /*Reserved*/
uint32_t rtc_pad_force_hold : 1; /*rtc pad force hold*/
uint32_t reserved22 : 10; /*Reserved*/
};
uint32_t val;
} pwc;
union {
struct {
uint32_t vdd_spi_pwr_drv : 2; /*Need add desc*/
uint32_t vdd_spi_pwr_force : 1; /*Need add desc*/
uint32_t vdd_spi_pd_en : 1; /*Need add desc*/
uint32_t lslp_mem_force_pd : 1; /*memories in digital core force PD in sleep*/
uint32_t lslp_mem_force_pu : 1; /*memories in digital core force no PD in sleep*/
uint32_t reserved6 : 13; /*Reserved*/
uint32_t dg_wrap_force_pd : 1; /*digital core force power down*/
uint32_t dg_wrap_force_pu : 1; /*digital core force power up*/
uint32_t reserved21 : 10; /*Reserved*/
uint32_t dg_wrap_pd_en : 1; /*Need add desc*/
};
uint32_t val;
} dig_pwc;
union {
struct {
uint32_t reserved0 : 7; /*Reserved*/
uint32_t dig_iso_force_off : 1; /*Need add desc*/
uint32_t dig_iso_force_on : 1; /*Need add desc*/
uint32_t dg_pad_autohold : 1; /*read only register to indicate digital pad auto-hold status*/
uint32_t clr_dg_pad_autohold : 1; /*wtite only register to clear digital pad auto-hold*/
uint32_t dg_pad_autohold_en : 1; /*digital pad enable auto-hold*/
uint32_t dg_pad_force_noiso : 1; /*digital pad force no ISO*/
uint32_t dg_pad_force_iso : 1; /*digital pad force ISO*/
uint32_t dg_pad_force_unhold : 1; /*digital pad force un-hold*/
uint32_t dg_pad_force_hold : 1; /*digital pad force hold*/
uint32_t reserved16 : 14; /*Reserved*/
uint32_t dg_wrap_force_iso : 1; /*digital core force ISO*/
uint32_t dg_wrap_force_noiso : 1; /*Need add desc*/
};
uint32_t val;
} dig_iso;
union {
struct {
uint32_t chip_reset_width : 8; /*chip reset siginal pulse width*/
uint32_t chip_reset_en : 1; /*wdt reset whole chip enable*/
uint32_t pause_in_slp : 1; /*pause WDT in sleep*/
uint32_t reserved10 : 1; /*Reservedenable WDT reset APP CPU*/
uint32_t procpu_reset_en : 1; /*enable WDT reset PRO CPU*/
uint32_t flashboot_mod_en : 1; /*enable WDT in flash boot*/
uint32_t sys_reset_length : 3; /*system reset counter length*/
uint32_t cpu_reset_length : 3; /*CPU reset counter length*/
uint32_t stg3 : 3; /*1: interrupt stage en*/
uint32_t stg2 : 3; /*1: interrupt stage en*/
uint32_t stg1 : 3; /*1: interrupt stage en*/
uint32_t stg0 : 3; /*1: interrupt stage en*/
uint32_t en : 1; /*Need add desc*/
};
uint32_t val;
} wdt_config0;
uint32_t wdt_config1;
uint32_t wdt_config2;
uint32_t wdt_config3;
uint32_t wdt_config4;
union {
struct {
uint32_t reserved0 : 31; /*Reserved*/
uint32_t feed : 1; /*Need add desc*/
};
uint32_t val;
} wdt_feed;
uint32_t wdt_wprotect;
union {
struct {
uint32_t swd_reset_flag : 1; /*swd reset flag*/
uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/
uint32_t reserved2 : 15; /*Reserved*/
uint32_t swd_bypass_rst : 1; /*Need add desc*/
uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/
uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/
uint32_t swd_feed : 1; /*Sw feed swd*/
uint32_t swd_disable : 1; /*disabel SWD*/
uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/
};
uint32_t val;
} swd_conf;
uint32_t swd_wprotect;
union {
struct {
uint32_t reserved0 : 26; /*Reserved*/
uint32_t procpu_c1 : 6; /*Need add desc*/
};
uint32_t val;
} sw_cpu_stall;
uint32_t store4;
uint32_t store5;
uint32_t store6;
uint32_t store7;
union {
struct {
uint32_t reserved0 : 8; /*Reserveddigital wrap iso*/
uint32_t xpd_dig : 1; /*digital wrap power down*/
uint32_t rtc_touch_state_start : 1; /*touch should start to work*/
uint32_t rtc_touch_state_switch : 1; /*touch is about to working. Switch rtc main state*/
uint32_t rtc_touch_state_slp : 1; /*touch is in sleep state*/
uint32_t rtc_touch_state_done : 1; /*touch is done*/
uint32_t rtc_cocpu_state_start : 1; /*ulp/cocpu should start to work*/
uint32_t rtc_cocpu_state_switch : 1; /*ulp/cocpu is about to working. Switch rtc main state*/
uint32_t rtc_cocpu_state_slp : 1; /*ulp/cocpu is in sleep state*/
uint32_t rtc_cocpu_state_done : 1; /*ulp/cocpu is done*/
uint32_t rtc_main_state_xtal_iso : 1; /*no use any more*/
uint32_t rtc_main_state_pll_on : 1; /*rtc main state machine is in states that pll should be running*/
uint32_t rtc_rdy_for_wakeup : 1; /*rtc is ready to receive wake up trigger from wake up source*/
uint32_t rtc_main_state_wait_end : 1; /*rtc main state machine has been waited for some cycles*/
uint32_t rtc_in_wakeup_state : 1; /*rtc main state machine is in the states of wakeup process*/
uint32_t rtc_in_low_power_state : 1; /*rtc main state machine is in the states of low power*/
uint32_t rtc_main_state_in_wait_8m : 1; /*rtc main state machine is in wait 8m state*/
uint32_t rtc_main_state_in_wait_pll : 1; /*rtc main state machine is in wait pll state*/
uint32_t rtc_main_state_in_wait_xtl : 1; /*rtc main state machine is in wait xtal state*/
uint32_t rtc_main_state_in_slp : 1; /*rtc main state machine is in sleep state*/
uint32_t rtc_main_state_in_idle : 1; /*rtc main state machine is in idle state*/
uint32_t rtc_main_state : 4; /*rtc main state machine status*/
};
uint32_t val;
} low_power_st;
uint32_t diag0;
union {
struct {
uint32_t rtc_gpio_pin0_hold : 1; /*Need add desc*/
uint32_t rtc_gpio_pin1_hold : 1; /*Need add desc*/
uint32_t rtc_gpio_pin2_hold : 1; /*Need add desc*/
uint32_t rtc_gpio_pin3_hold : 1; /*Need add desc*/
uint32_t rtc_gpio_pin4_hold : 1; /*Need add desc*/
uint32_t rtc_gpio_pin5_hold : 1; /*Need add desc*/
uint32_t reserved6 : 26; /*Reserved*/
};
uint32_t val;
} pad_hold;
uint32_t dig_pad_hold;
union {
struct {
uint32_t reserved0 : 4; /*Reserved*/
uint32_t int_wait : 10; /*brown out interrupt wait cycles*/
uint32_t close_flash_ena : 1; /*enable close flash when brown out happens*/
uint32_t pd_rf_ena : 1; /*enable power down RF when brown out happens*/
uint32_t rst_wait : 10; /*brown out reset wait cycles*/
uint32_t rst_ena : 1; /*enable brown out reset*/
uint32_t rst_sel : 1; /*1: 4-pos reset*/
uint32_t ana_rst_en : 1; /*Need add desc*/
uint32_t cnt_clr : 1; /*clear brown out counter*/
uint32_t ena : 1; /*enable brown out*/
uint32_t det : 1; /*Need add desc*/
};
uint32_t val;
} brown_out;
uint32_t time_low1;
union {
struct {
uint32_t rtc_timer_value1_high : 16; /*RTC timer high 16 bits*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} time_high1;
union {
struct {
uint32_t reserved0 : 18; /*Reserved*/
uint32_t io_mux_reset_disable : 1; /*Need add desc*/
uint32_t reserved19 : 13; /*Reserved*/
};
uint32_t val;
} usb_conf;
union {
struct {
uint32_t reject_cause : 18; /*sleep reject cause*/
uint32_t reserved18 : 14; /*Reserved*/
};
uint32_t val;
} slp_reject_cause;
union {
struct {
uint32_t force_download_boot : 1; /*Need add desc*/
uint32_t reserved1 : 31; /*Reserved*/
};
uint32_t val;
} option1;
union {
struct {
uint32_t wakeup_cause : 17; /*sleep wakeup cause*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} slp_wakeup_cause;
union {
struct {
uint32_t reserved0 : 8; /*Reserved*/
uint32_t ulp_cp_timer_slp_cycle : 24; /*sleep cycles for ULP-coprocessor timer*/
};
uint32_t val;
} ulp_cp_timer_1;
union {
struct {
uint32_t slp_wakeup_w1ts : 1; /*enable sleep wakeup interrupt*/
uint32_t slp_reject_w1ts : 1; /*enable sleep reject interrupt*/
uint32_t reserved2 : 1; /*Reserved*/
uint32_t rtc_wdt_w1ts : 1; /*enable RTC WDT interrupt*/
uint32_t reserved4 : 5; /*Reserved*/
uint32_t w1ts : 1; /*enable brown out interrupt*/
uint32_t rtc_main_timer_w1ts : 1; /*enable RTC main timer interrupt*/
uint32_t reserved11 : 4; /*Reserved*/
uint32_t rtc_swd_w1ts : 1; /*enable super watch dog interrupt*/
uint32_t reserved16 : 4; /*Reservedenbale gitch det interrupt*/
uint32_t rtc_bbpll_cal_w1ts : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} int_ena_w1ts;
union {
struct {
uint32_t slp_wakeup_w1tc : 1; /*enable sleep wakeup interrupt*/
uint32_t slp_reject_w1tc : 1; /*enable sleep reject interrupt*/
uint32_t reserved2 : 1; /*Reserved*/
uint32_t rtc_wdt_w1tc : 1; /*enable RTC WDT interrupt*/
uint32_t reserved4 : 5; /*Reserved*/
uint32_t w1tc : 1; /*enable brown out interrupt*/
uint32_t rtc_main_timer_w1tc : 1; /*enable RTC main timer interrupt*/
uint32_t reserved11 : 4; /*Reserved*/
uint32_t rtc_swd_w1tc : 1; /*enable super watch dog interrupt*/
uint32_t reserved16 : 4; /*Reservedenbale gitch det interrupt*/
uint32_t rtc_bbpll_cal_w1tc : 1; /*Need add desc*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} int_ena_w1tc;
union {
struct {
uint32_t reserved0 : 18; /*Reserved*/
uint32_t retention_clk_sel : 1; /*Need add desc*/
uint32_t retention_done_wait : 3; /*Need add desc*/
uint32_t retention_clkoff_wait : 4; /*Need add desc*/
uint32_t retention_en : 1; /*Need add desc*/
uint32_t retention_wait : 5; /*wait cycles for rention operation*/
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t rtc_fib_sel : 3; /*select use analog fib signal*/
uint32_t reserved3 : 29; /*Reserved*/
};
uint32_t val;
} fib_sel;
union {
struct {
uint32_t rtc_gpio_wakeup_status : 6; /*Need add desc*/
uint32_t rtc_gpio_wakeup_status_clr : 1; /*Need add desc*/
uint32_t rtc_gpio_pin_clk_gate : 1; /*Need add desc*/
uint32_t rtc_gpio_pin5_int_type : 3; /*Need add desc*/
uint32_t rtc_gpio_pin4_int_type : 3; /*Need add desc*/
uint32_t rtc_gpio_pin3_int_type : 3; /*Need add desc*/
uint32_t rtc_gpio_pin2_int_type : 3; /*Need add desc*/
uint32_t rtc_gpio_pin1_int_type : 3; /*Need add desc*/
uint32_t rtc_gpio_pin0_int_type : 3; /*Need add desc*/
uint32_t rtc_gpio_pin5_wakeup_enable : 1; /*Need add desc*/
uint32_t rtc_gpio_pin4_wakeup_enable : 1; /*Need add desc*/
uint32_t rtc_gpio_pin3_wakeup_enable : 1; /*Need add desc*/
uint32_t rtc_gpio_pin2_wakeup_enable : 1; /*Need add desc*/
uint32_t rtc_gpio_pin1_wakeup_enable : 1; /*Need add desc*/
uint32_t rtc_gpio_pin0_wakeup_enable : 1; /*Need add desc*/
};
uint32_t val;
} gpio_wakeup;
union {
struct {
uint32_t reserved0 : 1; /*Reserved*/
uint32_t rtc_debug_12m_no_gating : 1; /*Need add desc*/
uint32_t rtc_debug_bit_sel : 5; /*Need add desc*/
uint32_t rtc_debug_sel0 : 5; /*Need add desc*/
uint32_t rtc_debug_sel1 : 5; /*Need add desc*/
uint32_t rtc_debug_sel2 : 5; /*Need add desc*/
uint32_t rtc_debug_sel3 : 5; /*Need add desc*/
uint32_t rtc_debug_sel4 : 5; /*Need add desc*/
};
uint32_t val;
} dbg_sel;
union {
struct {
uint32_t reserved0 : 2; /*Reserved*/
uint32_t rtc_gpio_pin5_mux_sel : 1; /*Need add desc*/
uint32_t rtc_gpio_pin4_mux_sel : 1; /*Need add desc*/
uint32_t rtc_gpio_pin3_mux_sel : 1; /*Need add desc*/
uint32_t rtc_gpio_pin2_mux_sel : 1; /*Need add desc*/
uint32_t rtc_gpio_pin1_mux_sel : 1; /*Need add desc*/
uint32_t rtc_gpio_pin0_mux_sel : 1; /*Need add desc*/
uint32_t rtc_gpio_pin5_fun_sel : 4; /*Need add desc*/
uint32_t rtc_gpio_pin4_fun_sel : 4; /*Need add desc*/
uint32_t rtc_gpio_pin3_fun_sel : 4; /*Need add desc*/
uint32_t rtc_gpio_pin2_fun_sel : 4; /*Need add desc*/
uint32_t rtc_gpio_pin1_fun_sel : 4; /*Need add desc*/
uint32_t rtc_gpio_pin0_fun_sel : 4; /*Need add desc*/
};
uint32_t val;
} dbg_map;
union {
struct {
uint32_t reserved0 : 27; /*Reserved*/
uint32_t sar2_pwdet_cct : 3; /*Need add desc*/
uint32_t force_xpd_sar : 2; /*Need add desc*/
};
uint32_t val;
} sensor_ctrl;
union {
struct {
uint32_t reserved0 : 27; /*Reserved*/
uint32_t sar_debug_sel : 5; /*Need add desc*/
};
uint32_t val;
} dbg_sar_sel;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
uint32_t date : 28; /*Need add desc*/
uint32_t reserved28 : 4; /*Reserved*/
};
uint32_t val;
} date;
} rtc_cntl_dev_t;
extern rtc_cntl_dev_t RTCCNTL;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_CNTL_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_I2C_REG_H_
#define _SOC_RTC_I2C_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
/*description: time period that scl = 0*/
#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_LOW_PERIOD_S 0
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: rtc i2c reg clk gating*/
#define RTC_I2C_CLK_EN (BIT(31))
#define RTC_I2C_CLK_EN_M (BIT(31))
#define RTC_I2C_CLK_EN_V 0x1
#define RTC_I2C_CLK_EN_S 31
/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: rtc i2c sw reset*/
#define RTC_I2C_RESET (BIT(30))
#define RTC_I2C_RESET_M (BIT(30))
#define RTC_I2C_RESET_V 0x1
#define RTC_I2C_RESET_S 30
/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29))
#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29))
#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1
#define RTC_I2C_CTRL_CLK_GATE_EN_S 29
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: receive lsb first*/
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
#define RTC_I2C_RX_LSB_FIRST_M (BIT(5))
#define RTC_I2C_RX_LSB_FIRST_V 0x1
#define RTC_I2C_RX_LSB_FIRST_S 5
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: transit lsb first*/
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
#define RTC_I2C_TX_LSB_FIRST_M (BIT(4))
#define RTC_I2C_TX_LSB_FIRST_V 0x1
#define RTC_I2C_TX_LSB_FIRST_S 4
/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: force start*/
#define RTC_I2C_TRANS_START (BIT(3))
#define RTC_I2C_TRANS_START_M (BIT(3))
#define RTC_I2C_TRANS_START_V 0x1
#define RTC_I2C_TRANS_START_S 3
/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: 1=master 0=slave*/
#define RTC_I2C_MS_MODE (BIT(2))
#define RTC_I2C_MS_MODE_M (BIT(2))
#define RTC_I2C_MS_MODE_V 0x1
#define RTC_I2C_MS_MODE_S 2
/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: 1=push pull 0=open drain*/
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1))
#define RTC_I2C_SCL_FORCE_OUT_V 0x1
#define RTC_I2C_SCL_FORCE_OUT_S 1
/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: 1=push pull 0=open drain*/
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0))
#define RTC_I2C_SDA_FORCE_OUT_V 0x1
#define RTC_I2C_SDA_FORCE_OUT_S 0
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: scl last status*/
#define RTC_I2C_SCL_STATE_LAST 0x00000007
#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
#define RTC_I2C_SCL_STATE_LAST_V 0x7
#define RTC_I2C_SCL_STATE_LAST_S 28
/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: i2c last main status*/
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007
#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
/*description: shifter content*/
#define RTC_I2C_SHIFT 0x000000FF
#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
#define RTC_I2C_SHIFT_V 0xFF
#define RTC_I2C_SHIFT_S 16
/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
/*description: which operation is working*/
#define RTC_I2C_OP_CNT 0x00000003
#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
#define RTC_I2C_OP_CNT_V 0x3
#define RTC_I2C_OP_CNT_S 6
/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: One byte transit done*/
#define RTC_I2C_BYTE_TRANS (BIT(5))
#define RTC_I2C_BYTE_TRANS_M (BIT(5))
#define RTC_I2C_BYTE_TRANS_V 0x1
#define RTC_I2C_BYTE_TRANS_S 5
/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: slave reg sub address*/
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4))
#define RTC_I2C_SLAVE_ADDRESSED_V 0x1
#define RTC_I2C_SLAVE_ADDRESSED_S 4
/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: bus is busy*/
#define RTC_I2C_BUS_BUSY (BIT(3))
#define RTC_I2C_BUS_BUSY_M (BIT(3))
#define RTC_I2C_BUS_BUSY_V 0x1
#define RTC_I2C_BUS_BUSY_S 3
/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: arbitration is lost*/
#define RTC_I2C_ARB_LOST (BIT(2))
#define RTC_I2C_ARB_LOST_M (BIT(2))
#define RTC_I2C_ARB_LOST_V 0x1
#define RTC_I2C_ARB_LOST_S 2
/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: slave read or write*/
#define RTC_I2C_SLAVE_RW (BIT(1))
#define RTC_I2C_SLAVE_RW_M (BIT(1))
#define RTC_I2C_SLAVE_RW_V 0x1
#define RTC_I2C_SLAVE_RW_S 1
/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: ack response*/
#define RTC_I2C_ACK_REC (BIT(0))
#define RTC_I2C_ACK_REC_M (BIT(0))
#define RTC_I2C_ACK_REC_V 0x1
#define RTC_I2C_ACK_REC_S 0
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
/*description: time out threshold*/
#define RTC_I2C_TIMEOUT 0x000FFFFF
#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
#define RTC_I2C_TIMEOUT_V 0xFFFFF
#define RTC_I2C_TIMEOUT_S 0
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: i2c 10bit mode enable*/
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31))
#define RTC_I2C_ADDR_10BIT_EN_V 0x1
#define RTC_I2C_ADDR_10BIT_EN_S 31
/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
/*description: slave address*/
#define RTC_I2C_SLAVE_ADDR 0x00007FFF
#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
#define RTC_I2C_SLAVE_ADDR_S 0
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
/*description: time period that scl = 1*/
#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_HIGH_PERIOD_S 0
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
/*description: time period for SDA to toggle after SCL goes low*/
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF
#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF
#define RTC_I2C_SDA_DUTY_NUM_S 0
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
/*description: time period for SCL to toggle after I2C start is triggered*/
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_START_PERIOD_S 0
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
/*description: time period for SCL to stop after I2C end is triggered*/
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_STOP_PERIOD_S 0
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: clear detect start interrupt*/
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_CLR_V 0x1
#define RTC_I2C_DETECT_START_INT_CLR_S 8
/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: clear transit load data complete interrupt*/
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_CLR_V 0x1
#define RTC_I2C_TX_DATA_INT_CLR_S 7
/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: clear receive data interrupt*/
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_CLR_V 0x1
#define RTC_I2C_RX_DATA_INT_CLR_S 6
/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: clear ack error interrupt*/
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: clear time out interrupt*/
#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4))
#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1
#define RTC_I2C_TIMEOUT_INT_CLR_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: clear transit complete interrupt*/
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: clear master transit complete interrupt*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: clear arbitration lost interrupt*/
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: clear slave transit complete interrupt*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028)
/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: detect start interrupt raw*/
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_RAW_V 0x1
#define RTC_I2C_DETECT_START_INT_RAW_S 8
/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: transit data interrupt raw*/
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_RAW_V 0x1
#define RTC_I2C_TX_DATA_INT_RAW_S 7
/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: receive data interrupt raw*/
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_RAW_V 0x1
#define RTC_I2C_RX_DATA_INT_RAW_S 6
/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ack error interrupt raw*/
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: time out interrupt raw*/
#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4))
#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1
#define RTC_I2C_TIMEOUT_INT_RAW_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: transit complete interrupt raw*/
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: master transit complete interrupt raw*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: arbitration lost interrupt raw*/
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: slave transit complete interrupt raw*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c)
/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: detect start interrupt state*/
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_ST_V 0x1
#define RTC_I2C_DETECT_START_INT_ST_S 8
/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: transit data interrupt state*/
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_ST_V 0x1
#define RTC_I2C_TX_DATA_INT_ST_S 7
/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: receive data interrupt state*/
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_ST_V 0x1
#define RTC_I2C_RX_DATA_INT_ST_S 6
/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ack error interrupt state*/
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ST_V 0x1
#define RTC_I2C_ACK_ERR_INT_ST_S 5
/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: time out interrupt state*/
#define RTC_I2C_TIMEOUT_INT_ST (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ST_V 0x1
#define RTC_I2C_TIMEOUT_INT_ST_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: transit complete interrupt state*/
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: master transit complete interrupt state*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: arbitration lost interrupt state*/
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: slave transit complete interrupt state*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030)
/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: enable detect start interrupt*/
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_ENA_V 0x1
#define RTC_I2C_DETECT_START_INT_ENA_S 8
/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: enable transit data interrupt*/
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_ENA_V 0x1
#define RTC_I2C_TX_DATA_INT_ENA_S 7
/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: enable receive data interrupt*/
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_ENA_V 0x1
#define RTC_I2C_RX_DATA_INT_ENA_S 6
/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: enable eack error interrupt*/
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: enable time out interrupt*/
#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1
#define RTC_I2C_TIMEOUT_INT_ENA_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: enable transit complete interrupt*/
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: enable master transit complete interrupt*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable arbitration lost interrupt*/
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable slave transit complete interrupt*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034)
/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: i2c done*/
#define RTC_I2C_DONE (BIT(31))
#define RTC_I2C_DONE_M (BIT(31))
#define RTC_I2C_DONE_V 0x1
#define RTC_I2C_DONE_S 31
/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: data sent by slave*/
#define RTC_I2C_SLAVE_TX_DATA 0x000000FF
#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
#define RTC_I2C_SLAVE_TX_DATA_V 0xFF
#define RTC_I2C_SLAVE_TX_DATA_S 8
/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: data received*/
#define RTC_I2C_RDATA 0x000000FF
#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
#define RTC_I2C_RDATA_V 0xFF
#define RTC_I2C_RDATA_S 0
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038)
/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command0_done*/
#define RTC_I2C_COMMAND0_DONE (BIT(31))
#define RTC_I2C_COMMAND0_DONE_M (BIT(31))
#define RTC_I2C_COMMAND0_DONE_V 0x1
#define RTC_I2C_COMMAND0_DONE_S 31
/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
/*description: command0*/
#define RTC_I2C_COMMAND0 0x00003FFF
#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
#define RTC_I2C_COMMAND0_V 0x3FFF
#define RTC_I2C_COMMAND0_S 0
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c)
/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command1_done*/
#define RTC_I2C_COMMAND1_DONE (BIT(31))
#define RTC_I2C_COMMAND1_DONE_M (BIT(31))
#define RTC_I2C_COMMAND1_DONE_V 0x1
#define RTC_I2C_COMMAND1_DONE_S 31
/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command1*/
#define RTC_I2C_COMMAND1 0x00003FFF
#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
#define RTC_I2C_COMMAND1_V 0x3FFF
#define RTC_I2C_COMMAND1_S 0
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040)
/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command2_done*/
#define RTC_I2C_COMMAND2_DONE (BIT(31))
#define RTC_I2C_COMMAND2_DONE_M (BIT(31))
#define RTC_I2C_COMMAND2_DONE_V 0x1
#define RTC_I2C_COMMAND2_DONE_S 31
/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
/*description: command2*/
#define RTC_I2C_COMMAND2 0x00003FFF
#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
#define RTC_I2C_COMMAND2_V 0x3FFF
#define RTC_I2C_COMMAND2_S 0
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044)
/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command3_done*/
#define RTC_I2C_COMMAND3_DONE (BIT(31))
#define RTC_I2C_COMMAND3_DONE_M (BIT(31))
#define RTC_I2C_COMMAND3_DONE_V 0x1
#define RTC_I2C_COMMAND3_DONE_S 31
/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
/*description: command3*/
#define RTC_I2C_COMMAND3 0x00003FFF
#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
#define RTC_I2C_COMMAND3_V 0x3FFF
#define RTC_I2C_COMMAND3_S 0
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048)
/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command4_done*/
#define RTC_I2C_COMMAND4_DONE (BIT(31))
#define RTC_I2C_COMMAND4_DONE_M (BIT(31))
#define RTC_I2C_COMMAND4_DONE_V 0x1
#define RTC_I2C_COMMAND4_DONE_S 31
/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
/*description: command4*/
#define RTC_I2C_COMMAND4 0x00003FFF
#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
#define RTC_I2C_COMMAND4_V 0x3FFF
#define RTC_I2C_COMMAND4_S 0
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c)
/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command5_done*/
#define RTC_I2C_COMMAND5_DONE (BIT(31))
#define RTC_I2C_COMMAND5_DONE_M (BIT(31))
#define RTC_I2C_COMMAND5_DONE_V 0x1
#define RTC_I2C_COMMAND5_DONE_S 31
/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
/*description: command5*/
#define RTC_I2C_COMMAND5 0x00003FFF
#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
#define RTC_I2C_COMMAND5_V 0x3FFF
#define RTC_I2C_COMMAND5_S 0
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050)
/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command6_done*/
#define RTC_I2C_COMMAND6_DONE (BIT(31))
#define RTC_I2C_COMMAND6_DONE_M (BIT(31))
#define RTC_I2C_COMMAND6_DONE_V 0x1
#define RTC_I2C_COMMAND6_DONE_S 31
/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command6*/
#define RTC_I2C_COMMAND6 0x00003FFF
#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
#define RTC_I2C_COMMAND6_V 0x3FFF
#define RTC_I2C_COMMAND6_S 0
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054)
/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command7_done*/
#define RTC_I2C_COMMAND7_DONE (BIT(31))
#define RTC_I2C_COMMAND7_DONE_M (BIT(31))
#define RTC_I2C_COMMAND7_DONE_V 0x1
#define RTC_I2C_COMMAND7_DONE_S 31
/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
/*description: command7*/
#define RTC_I2C_COMMAND7 0x00003FFF
#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
#define RTC_I2C_COMMAND7_V 0x3FFF
#define RTC_I2C_COMMAND7_S 0
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058)
/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command8_done*/
#define RTC_I2C_COMMAND8_DONE (BIT(31))
#define RTC_I2C_COMMAND8_DONE_M (BIT(31))
#define RTC_I2C_COMMAND8_DONE_V 0x1
#define RTC_I2C_COMMAND8_DONE_S 31
/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command8*/
#define RTC_I2C_COMMAND8 0x00003FFF
#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
#define RTC_I2C_COMMAND8_V 0x3FFF
#define RTC_I2C_COMMAND8_S 0
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c)
/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command9_done*/
#define RTC_I2C_COMMAND9_DONE (BIT(31))
#define RTC_I2C_COMMAND9_DONE_M (BIT(31))
#define RTC_I2C_COMMAND9_DONE_V 0x1
#define RTC_I2C_COMMAND9_DONE_S 31
/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
/*description: command9*/
#define RTC_I2C_COMMAND9 0x00003FFF
#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
#define RTC_I2C_COMMAND9_V 0x3FFF
#define RTC_I2C_COMMAND9_S 0
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060)
/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command10_done*/
#define RTC_I2C_COMMAND10_DONE (BIT(31))
#define RTC_I2C_COMMAND10_DONE_M (BIT(31))
#define RTC_I2C_COMMAND10_DONE_V 0x1
#define RTC_I2C_COMMAND10_DONE_S 31
/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
/*description: command10*/
#define RTC_I2C_COMMAND10 0x00003FFF
#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
#define RTC_I2C_COMMAND10_V 0x3FFF
#define RTC_I2C_COMMAND10_S 0
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064)
/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command11_done*/
#define RTC_I2C_COMMAND11_DONE (BIT(31))
#define RTC_I2C_COMMAND11_DONE_M (BIT(31))
#define RTC_I2C_COMMAND11_DONE_V 0x1
#define RTC_I2C_COMMAND11_DONE_S 31
/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
/*description: command11*/
#define RTC_I2C_COMMAND11 0x00003FFF
#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
#define RTC_I2C_COMMAND11_V 0x3FFF
#define RTC_I2C_COMMAND11_S 0
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068)
/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command12_done*/
#define RTC_I2C_COMMAND12_DONE (BIT(31))
#define RTC_I2C_COMMAND12_DONE_M (BIT(31))
#define RTC_I2C_COMMAND12_DONE_V 0x1
#define RTC_I2C_COMMAND12_DONE_S 31
/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
/*description: command12*/
#define RTC_I2C_COMMAND12 0x00003FFF
#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
#define RTC_I2C_COMMAND12_V 0x3FFF
#define RTC_I2C_COMMAND12_S 0
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c)
/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command13_done*/
#define RTC_I2C_COMMAND13_DONE (BIT(31))
#define RTC_I2C_COMMAND13_DONE_M (BIT(31))
#define RTC_I2C_COMMAND13_DONE_V 0x1
#define RTC_I2C_COMMAND13_DONE_S 31
/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command13*/
#define RTC_I2C_COMMAND13 0x00003FFF
#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
#define RTC_I2C_COMMAND13_V 0x3FFF
#define RTC_I2C_COMMAND13_S 0
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070)
/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command14_done*/
#define RTC_I2C_COMMAND14_DONE (BIT(31))
#define RTC_I2C_COMMAND14_DONE_M (BIT(31))
#define RTC_I2C_COMMAND14_DONE_V 0x1
#define RTC_I2C_COMMAND14_DONE_S 31
/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: command14*/
#define RTC_I2C_COMMAND14 0x00003FFF
#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
#define RTC_I2C_COMMAND14_V 0x3FFF
#define RTC_I2C_COMMAND14_S 0
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074)
/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command15_done*/
#define RTC_I2C_COMMAND15_DONE (BIT(31))
#define RTC_I2C_COMMAND15_DONE_M (BIT(31))
#define RTC_I2C_COMMAND15_DONE_V 0x1
#define RTC_I2C_COMMAND15_DONE_S 31
/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: command15*/
#define RTC_I2C_COMMAND15 0x00003FFF
#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
#define RTC_I2C_COMMAND15_V 0x3FFF
#define RTC_I2C_COMMAND15_S 0
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
/*description: */
#define RTC_I2C_DATE 0x0FFFFFFF
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
#define RTC_I2C_DATE_V 0xFFFFFFF
#define RTC_I2C_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_I2C_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_I2C_STRUCT_H_
#define _SOC_RTC_I2C_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct rtc_i2c_dev_s{
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_low;
union {
struct {
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
uint32_t ms_mode: 1; /*1=master 0=slave*/
uint32_t trans_start: 1; /*force start*/
uint32_t tx_lsb_first: 1; /*transit lsb first*/
uint32_t rx_lsb_first: 1; /*receive lsb first*/
uint32_t reserved6: 23;
uint32_t i2c_ctrl_clk_gate_en: 1;
uint32_t i2c_reset: 1; /*rtc i2c sw reset*/
uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t ack_rec: 1; /*ack response*/
uint32_t slave_rw: 1; /*slave read or write*/
uint32_t arb_lost: 1; /*arbitration is lost*/
uint32_t bus_busy: 1; /*bus is busy*/
uint32_t slave_addressed: 1; /*slave reg sub address*/
uint32_t byte_trans: 1; /*One byte transit done*/
uint32_t op_cnt: 2; /*which operation is working*/
uint32_t reserved8: 8;
uint32_t shift: 8; /*shifter content*/
uint32_t scl_main_state_last: 3; /*i2c last main status*/
uint32_t reserved27: 1;
uint32_t scl_state_last: 3; /*scl last status*/
uint32_t reserved31: 1;
};
uint32_t val;
} status;
union {
struct {
uint32_t time_out: 20; /*time out threshold*/
uint32_t reserved20:12;
};
uint32_t val;
} timeout;
union {
struct {
uint32_t addr: 15; /*slave address*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*i2c 10bit mode enable*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t period: 20; /*time period that scl = 1*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_high;
union {
struct {
uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/
uint32_t reserved20: 12;
};
uint32_t val;
} sda_duty;
union {
struct {
uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_start_period;
union {
struct {
uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_stop_period;
union {
struct {
uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/
uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/
uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/
uint32_t trans_complete: 1; /*clear transit complete interrupt*/
uint32_t time_out: 1; /*clear time out interrupt*/
uint32_t ack_err: 1; /*clear ack error interrupt*/
uint32_t rx_data: 1; /*clear receive data interrupt*/
uint32_t tx_data: 1; /*clear transit load data complete interrupt*/
uint32_t detect_start: 1; /*clear detect start interrupt*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/
uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/
uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/
uint32_t trans_complete: 1; /*transit complete interrupt raw*/
uint32_t time_out: 1; /*time out interrupt raw*/
uint32_t ack_err: 1; /*ack error interrupt raw*/
uint32_t rx_data: 1; /*receive data interrupt raw*/
uint32_t tx_data: 1; /*transit data interrupt raw*/
uint32_t detect_start: 1; /*detect start interrupt raw*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/
uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/
uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/
uint32_t trans_complete: 1; /*transit complete interrupt state*/
uint32_t time_out: 1; /*time out interrupt state*/
uint32_t ack_err: 1; /*ack error interrupt state*/
uint32_t rx_data: 1; /*receive data interrupt state*/
uint32_t tx_data: 1; /*transit data interrupt state*/
uint32_t detect_start: 1; /*detect start interrupt state*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/
uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/
uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/
uint32_t trans_complete: 1; /*enable transit complete interrupt*/
uint32_t time_out: 1; /*enable time out interrupt*/
uint32_t ack_err: 1; /*enable eack error interrupt*/
uint32_t rx_data: 1; /*enable receive data interrupt*/
uint32_t tx_data: 1; /*enable transit data interrupt*/
uint32_t detect_start: 1; /*enable detect start interrupt*/
uint32_t reserved9: 23;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t i2c_rdata: 8; /*data received*/
uint32_t slave_tx_data: 8; /*data sent by slave*/
uint32_t reserved16: 15;
uint32_t i2c_done: 1; /*i2c done*/
};
uint32_t val;
} fifo_data;
union {
struct {
uint32_t command0: 14; /*command0*/
uint32_t reserved14: 17;
uint32_t done: 1; /*command0_done*/
};
uint32_t val;
} command[16];
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
union {
struct {
uint32_t i2c_date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
} rtc_i2c_dev_t;
extern rtc_i2c_dev_t RTC_I2C;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_RTC_I2C_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SENSITIVE_REG_H_
#define _SOC_SENSITIVE_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0)
/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_ROM_TABLE_LOCK (BIT(0))
#define SENSITIVE_ROM_TABLE_LOCK_M (BIT(0))
#define SENSITIVE_ROM_TABLE_LOCK_V 0x1
#define SENSITIVE_ROM_TABLE_LOCK_S 0
#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4)
/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_ROM_TABLE 0xFFFFFFFF
#define SENSITIVE_ROM_TABLE_M ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
#define SENSITIVE_ROM_TABLE_V 0xFFFFFFFF
#define SENSITIVE_ROM_TABLE_S 0
#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8)
/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0))
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0))
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1
#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0
#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xC)
/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0))
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0))
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1
#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0
#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10)
/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0))
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0))
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1
#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0
#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14)
/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: 3'b111 ; */
/*description: Need add description.*/
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM 0x00000007
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V 0x7
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S 1
/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE (BIT(0))
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M (BIT(0))
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V 0x1
#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S 0
#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x18)
/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP (BIT(3))
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M (BIT(3))
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V 0x1
#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S 3
/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM 0x00000007
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V 0x7
#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S 0
#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x1C)
/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0))
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0))
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1
#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0
#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x20)
/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3))
#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3))
#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1
#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3
/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2))
#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2))
#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1
#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2
/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1))
#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1))
#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1
#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1
/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0))
#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0))
#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1
#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0
#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x24)
/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0))
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0))
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1
#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0
#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x28)
/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1))
#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1))
#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1
#define SENSITIVE_PRO_MMU_WR_ACS_S 1
/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0))
#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0))
#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1
#define SENSITIVE_PRO_MMU_RD_ACS_S 0
#define SENSITIVE_PIF_ACCESS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x2C)
/* SENSITIVE_PIF_ACCESS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK (BIT(0))
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_M (BIT(0))
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_V 0x1
#define SENSITIVE_PIF_ACCESS_MONITOR_LOCK_S 0
#define SENSITIVE_PIF_ACCESS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x30)
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN (BIT(1))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_V 0x1
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN_S 1
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR_S 0
#define SENSITIVE_PIF_ACCESS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x34)
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR_S 0
#define SENSITIVE_PIF_ACCESS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x38)
/* SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: Need add description.*/
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF
#define SENSITIVE_PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0
#define SENSITIVE_XTS_AES_KEY_UPDATE_REG (DR_REG_SENSITIVE_BASE + 0x3C)
/* SENSITIVE_XTS_AES_KEY_UPDATE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to update xts_aes key.*/
#define SENSITIVE_XTS_AES_KEY_UPDATE (BIT(0))
#define SENSITIVE_XTS_AES_KEY_UPDATE_M (BIT(0))
#define SENSITIVE_XTS_AES_KEY_UPDATE_V 0x1
#define SENSITIVE_XTS_AES_KEY_UPDATE_S 0
#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x40)
/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Need add description.*/
#define SENSITIVE_CLK_EN (BIT(0))
#define SENSITIVE_CLK_EN_M (BIT(0))
#define SENSITIVE_CLK_EN_V 0x1
#define SENSITIVE_CLK_EN_S 0
#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC)
/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106301 ; */
/*description: Need add description.*/
#define SENSITIVE_DATE 0x0FFFFFFF
#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
#define SENSITIVE_DATE_V 0xFFFFFFF
#define SENSITIVE_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SENSITIVE_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#include "esp_bit_defs.h"
#endif
#include "sdkconfig.h"
#define PRO_CPU_NUM (0)
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_GDMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_IO_MUX_BASE 0x60009000
#define DR_REG_RTC_I2C_BASE 0x6000e000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_I2C_EXT_BASE 0x60013000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_EFUSE_BASE 0x60008800
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_WDEVLE_BASE 0x60045000
#define DR_REG_ETM_BIT_BASE 0x6004B000
#define DR_REG_BLE_TIMER_BASE 0x6004B800
#define DR_REG_BLE_SEC_BASE 0x6004C000
#define DR_REG_COEX_BIT_BASE 0x6004C400
#define DR_REG_I2C_MST_BASE 0x6004E800
#define DR_REG_RTC_BLE_TIMER_BASE( i ) ( \
( (i) == 0 ) ? ( 0x6004E000 ) : \
( (i) == 1 ) ? ( 0x6004E100 ) : \
( (i) == 2 ) ? ( 0x6004E200 ) : \
0 \
)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))
#else
#define BIT(nr) (1 << (nr))
#endif
#ifndef __ASSEMBLER__
//write value to register
#define REG_WRITE(_r, _v) ({ \
(*(volatile uint32_t *)(_r)) = (_v); \
})
//read value from register
#define REG_READ(_r) ({ \
(*(volatile uint32_t *)(_r)); \
})
//get bit or get bits from register
#define REG_GET_BIT(_r, _b) ({ \
(*(volatile uint32_t*)(_r) & (_b)); \
})
//set bit or set bits to register
#define REG_SET_BIT(_r, _b) ({ \
(*(volatile uint32_t*)(_r) |= (_b)); \
})
//clear bit or clear bits of register
#define REG_CLR_BIT(_r, _b) ({ \
(*(volatile uint32_t*)(_r) &= ~(_b)); \
})
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) ({ \
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
})
//get field from register, uses field _S & _V to determine mask
#define REG_GET_FIELD(_r, _f) ({ \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
//set field of a register from variable, uses field _S & _V to determine mask
#define REG_SET_FIELD(_r, _f, _v) ({ \
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
})
//get field value from a variable, used when _f is not left shifted by _f##_S
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//read value from register
#define READ_PERI_REG(addr) ({ \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
//write value to register
#define WRITE_PERI_REG(addr, val) ({ \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
})
//clear bits of register controlled by mask
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
})
//set bits of register controlled by mask
#define SET_PERI_REG_MASK(reg, mask) ({ \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
})
//get bits of register controlled by mask
#define GET_PERI_REG_MASK(reg, mask) ({ \
(READ_PERI_REG(reg) & (mask)); \
})
//get bits of register controlled by highest bit and lowest bit
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
//set bits of register controlled by mask and shift
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
})
//get field of register
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
#endif /* !__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM ( 40*1000000)
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 40 // CPU is 40MHz
#define GPIO_MATRIX_DELAY_NS 0
//}}
/* Overall memory map */
#define SOC_DROM_LOW 0x3C000000
#define SOC_DROM_HIGH 0x3C800000
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH 0x42400000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40060000
#define SOC_DROM_MASK_LOW 0x3FF00000
#define SOC_DROM_MASK_HIGH 0x3FF20000
#define SOC_IRAM_LOW 0x4037C000
#define SOC_IRAM_HIGH 0x403C0000
#define SOC_DRAM_LOW 0x3FCA0000
#define SOC_DRAM_HIGH 0x3FCE0000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40380000
#define SOC_DIRAM_IRAM_HIGH 0x403C0000
#define SOC_DIRAM_DRAM_LOW 0x3FCA0000
#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x3FC88000
#define SOC_DMA_HIGH 0x3FD00000
// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x3FCA0000
#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
#define SOC_MEM_INTERNAL_LOW1 0x4037C000
#define SOC_MEM_INTERNAL_HIGH1 0x403C0000
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
// Region of address space that holds peripherals
#define SOC_PERIPHERAL_LOW 0x60000000
#define SOC_PERIPHERAL_HIGH 0x60100000
// Debug region, not used by software
#define SOC_DEBUG_LOW 0x20000000
#define SOC_DEBUG_HIGH 0x28000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fcebf10
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
#define ETS_T1_WDT_INUM 24 // Remove TODO: IDF-4246
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM 26
#define ETS_DPORT_INUM 28
//CPU0 Max valid interrupt number
#define ETS_MAX_INUM 31
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
#define ETS_SPI2_INUM 1
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
#define ETS_GPIO_INUM 4
//Other interrupt number should be managed by the user
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 0
//Interrupt medium level, used for INT WDT for example
#define SOC_INTERRUPT_LEVEL_MEDIUM 4

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
#pragma once
#define SOC_CPU_CORES_NUM 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define SOC_RTC_FAST_MEM_SUPPORTED 0
#define SOC_RTC_SLOW_MEM_SUPPORTED 0
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 0
#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_AES_GDMA (1)
/*-------------------------- ADC CAPS -------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_MAX_BITWIDTH (12)
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_DIGI_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP8684 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (21)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP8684, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP8684
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP8684 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO19 on ESP8684 is invalid.
#define SOC_GPIO_VALID_GPIO_MASK (((1U<<SOC_GPIO_PIN_COUNT) - 1) & (~(BIT19)))
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// TODO IDF-3918
#define SOC_I2C_NUM (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// TODO IDF-3896
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
/*-------------------------- MPU CAPS ----------------------------------------*/
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
/*-------------------------- RTC CAPS --------------------------------------*/
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP8684. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (1)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP8684 */
/*-------------------------- TWAI CAPS ---------------------------------------*/
// TODO IDF-3897
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP8684 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_WIFI_PD (1)
#define SOC_PM_SUPPORT_BT_PD (1)

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
* peripheral and include them here to avoid developing conflicts in those header files.
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"

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components/soc/esp8684/include/soc/spi_mem_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_MEM_STRUCT_H_
#define _SOC_SPI_MEM_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct spi_mem_dev_s{
union {
struct {
uint32_t mst_st : 4; /*The current status of SPI1 master FSM.*/
uint32_t slv_st : 4; /*The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
uint32_t reserved8 : 9; /*reserved*/
uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
};
uint32_t val;
} cmd;
uint32_t addr;
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
uint32_t fdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t reserved4 : 3; /*reserved*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t reserved9 : 1; /*reserved*/
uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12 : 1; /*reserved*/
uint32_t fastrd_mode : 1; /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
uint32_t reserved16 : 2; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */
uint32_t wrsr_2b : 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
uint32_t reserved2 : 18; /*reserved*/
uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time : 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t reserved10 : 15; /*reserved*/
uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
uint32_t sync_reset : 1; /*The FSM will be reset.*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. */
uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */
uint32_t clk_equ_sysclk : 1; /*Set this bit in 1-division mode.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. */
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
uint32_t reserved8 : 1; /*reserved*/
uint32_t ck_out_edge : 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t reserved16 : 8; /*reserved*/
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved6 : 20; /*reserved*/
uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len : 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} miso_dlen;
union {
struct {
uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t reserved24 : 8; /*reserved*/
};
uint32_t val;
} rd_status;
uint32_t reserved_30;
union {
struct {
uint32_t cs0_dis : 1; /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
uint32_t reserved0 : 1; /*reserved*/
uint32_t mst_st_trans_end : 1; /*The bit is used to indicate the spi0_mst_st controlled transmitting is done.*/
uint32_t mst_st_trans_end_en : 1; /*The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.*/
uint32_t slv_st_trans_end : 1; /*The bit is used to indicate the spi0_slv_st controlled transmitting is done.*/
uint32_t slv_st_trans_end_en : 1; /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
uint32_t reserved7 : 2; /*reserved*/
uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle */
uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set.*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} misc;
uint32_t tx_crc;
union {
struct {
uint32_t req_en : 1; /*For SPI0, Cache access enable, 1: enable, 0:disable.*/
uint32_t usr_addr_4byte : 1; /*For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.*/
uint32_t flash_usr_cmd : 1; /*For SPI0, cache read flash for user define command, 1: enable, 0:disable.*/
uint32_t fdin_dual : 1; /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdout_dual : 1; /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t faddr_dual : 1; /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad : 1; /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} cache_fctrl;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
union {
struct {
uint32_t spi0_slv_st : 4; /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
uint32_t spi0_mst_st : 3; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
uint32_t cspi_lock_delay_time : 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} fsm;
uint32_t data_buf[16];
union {
struct {
uint32_t reserved0 : 1; /*reserved*/
uint32_t waiti_dummy : 1; /*The dummy phase enable when wait flash idle (RDSR)*/
uint32_t waiti_cmd : 8; /*The command to wait flash idle(RDSR).*/
uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} flash_waiti_ctrl;
union {
struct {
uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_per_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
uint32_t flash_pes_en : 1; /*Set this bit to enable Auto-suspending function.*/
uint32_t pesr_end_msk : 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
uint32_t frd_sus_2b : 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/
uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
};
uint32_t val;
} flash_sus_ctrl;
union {
struct {
uint32_t flash_per_command : 8; /*Program/Erase resume command.*/
uint32_t flash_pes_command : 8; /*Program/Erase suspend command.*/
uint32_t wait_pesr_command : 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
};
uint32_t val;
} flash_sus_cmd;
union {
struct {
uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/
uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
uint32_t flash_res_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
uint32_t flash_dp_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
uint32_t spi0_lock_en : 1; /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} sus_status;
union {
struct {
uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/
uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} timing_cali;
union {
struct {
uint32_t din0_mode : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/
uint32_t din1_mode : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/
uint32_t din2_mode : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/
uint32_t din3_mode : 2; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num : 1; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din1_num : 1; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din2_num : 1; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t din3_num : 1; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
uint32_t reserved4 : 28; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
uint32_t reserved4 : 28; /*reserved*/
};
uint32_t val;
} dout_mode;
uint32_t reserved_b8;
uint32_t reserved_bc;
union {
struct {
uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_t mst_st_end_en : 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t per_end : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end : 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t per_end : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t per_end : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
uint32_t mst_st_end : 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} int_st;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
union {
struct {
uint32_t clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
uint32_t reserved1 : 31; /*reserved*/
};
uint32_t val;
} clock_gate;
union {
struct {
uint32_t spi01_clk_sel : 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. */
uint32_t reserved2 : 30; /*reserved*/
};
uint32_t val;
} core_clk_sel;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
union {
struct {
uint32_t date : 28; /*SPI register version.*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_MEM_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 12
#define SPI_IOMUX_PIN_NUM_CS 14
#define SPI_IOMUX_PIN_NUM_MOSI 16
#define SPI_IOMUX_PIN_NUM_CLK 15
#define SPI_IOMUX_PIN_NUM_MISO 17
#define SPI_IOMUX_PIN_NUM_WP 13
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2
#define SPI2_IOMUX_PIN_NUM_HD 4
#define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 10
#endif

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct spi_dev_s{
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
uint32_t reserved18 : 5; /*reserved*/
uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} cmd;
uint32_t addr;
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
uint32_t dummy_out : 1; /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
uint32_t reserved4 : 1; /*reserved*/
uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_oct : 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved11 : 3; /*reserved*/
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved17 : 1; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t reserved22 : 1; /*reserved*/
uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
uint32_t reserved22 : 9; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
};
uint32_t val;
} clock;
union {
struct {
uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved1 : 2; /*reserved*/
uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
uint32_t opi_mode : 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
uint32_t reserved16 : 1; /*reserved*/
uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved18 : 6; /*reserved*/
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
uint32_t reserved8 : 8; /*reserved*/
uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/
uint32_t reserved16 : 11; /*reserved*/
uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} ms_dlen;
union {
struct {
uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/
uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
uint32_t reserved13 : 3; /*reserved*/
uint32_t clk_data_dtr_en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. */
uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
uint32_t addr_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
uint32_t reserved20 : 3; /*reserved*/
uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/
uint32_t dqs_idle_edge : 1; /*The default value of spi_dqs. Can be configured in CONF state.*/
uint32_t reserved25 : 4; /*reserved*/
uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/
uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
uint32_t quad_din_pin_swap : 1; /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.*/
};
uint32_t val;
} misc;
union {
struct {
uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din4_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din5_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/
uint32_t reserved17 : 15; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din4_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din5_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout4_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout5_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t d_dqs_mode : 1; /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} dout_mode;
union {
struct {
uint32_t dma_outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
uint32_t dma_infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
uint32_t reserved2 : 16; /*reserved*/
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t reserved22 : 5; /*reserved*/
uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/
uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/
uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_clr;
union {
struct {
uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */
uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */
uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */
uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/
uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t infifo_full_err_int_set : 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi_int_set : 1; /*The software set bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7_int_set : 1; /*The software set bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8_int_set : 1; /*The software set bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9_int_set : 1; /*The software set bit for SPI slave CMD9 interrupt.*/
uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done_int_set : 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done_int_set : 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done_int_set : 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err_int_set : 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err_int_set : 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/
uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_set;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t data_buf[16];
uint32_t reserved_d8;
uint32_t reserved_dc;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */
uint32_t reserved4 : 4; /*reserved*/
uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
uint32_t reserved12 : 10; /*reserved*/
uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/
uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */
uint32_t last_command : 8; /*In the slave mode it is the value of command.*/
uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/
};
uint32_t val;
} slave1;
union {
struct {
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/
uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} clk_gate;
uint32_t reserved_ec;
union {
struct {
uint32_t date : 28; /*SPI register version.*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2;
extern spi_dev_t GPSPI3;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: reg_rst_tick_cnt.*/
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SYSCON_RST_TICK_CNT_M (BIT(12))
#define SYSCON_RST_TICK_CNT_V 0x1
#define SYSCON_RST_TICK_CNT_S 12
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: reg_clk_en.*/
#define SYSCON_CLK_EN (BIT(11))
#define SYSCON_CLK_EN_M (BIT(11))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 11
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: reg_clk_320m_en.*/
#define SYSCON_CLK_320M_EN (BIT(10))
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: reg_pre_div_cnt.*/
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: reg_tick_enable.*/
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: reg_ck8m_tick_num.*/
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
#define SYSCON_CK8M_TICK_NUM_V 0xFF
#define SYSCON_CK8M_TICK_NUM_S 8
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: reg_xtal_tick_num.*/
#define SYSCON_XTAL_TICK_NUM 0x000000FF
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8)
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: reg_clk_xtal_oen.*/
#define SYSCON_CLK_XTAL_OEN (BIT(10))
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
#define SYSCON_CLK_XTAL_OEN_V 0x1
#define SYSCON_CLK_XTAL_OEN_S 10
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: reg_clk40x_bb_oen.*/
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: reg_clk_dac_cpu_oen.*/
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
#define SYSCON_CLK_DAC_CPU_OEN_S 8
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: reg_clk_adc_inf_oen.*/
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
#define SYSCON_CLK_ADC_INF_OEN_S 7
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: reg_clk_320m_oen.*/
#define SYSCON_CLK_320M_OEN (BIT(6))
#define SYSCON_CLK_320M_OEN_M (BIT(6))
#define SYSCON_CLK_320M_OEN_V 0x1
#define SYSCON_CLK_320M_OEN_S 6
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: reg_clk160_oen.*/
#define SYSCON_CLK160_OEN (BIT(5))
#define SYSCON_CLK160_OEN_M (BIT(5))
#define SYSCON_CLK160_OEN_V 0x1
#define SYSCON_CLK160_OEN_S 5
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: reg_clk80_oen.*/
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCON_CLK80_OEN_V 0x1
#define SYSCON_CLK80_OEN_S 4
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: reg_clk_bb_oen.*/
#define SYSCON_CLK_BB_OEN (BIT(3))
#define SYSCON_CLK_BB_OEN_M (BIT(3))
#define SYSCON_CLK_BB_OEN_V 0x1
#define SYSCON_CLK_BB_OEN_S 3
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: reg_clk44_oen.*/
#define SYSCON_CLK44_OEN (BIT(2))
#define SYSCON_CLK44_OEN_M (BIT(2))
#define SYSCON_CLK44_OEN_V 0x1
#define SYSCON_CLK44_OEN_S 2
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: reg_clk22_oen.*/
#define SYSCON_CLK22_OEN (BIT(1))
#define SYSCON_CLK22_OEN_M (BIT(1))
#define SYSCON_CLK22_OEN_V 0x1
#define SYSCON_CLK22_OEN_S 1
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: reg_clk20_oen.*/
#define SYSCON_CLK20_OEN (BIT(0))
#define SYSCON_CLK20_OEN_M (BIT(0))
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_bb_cfg.*/
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_S 0
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_bb_cfg_2.*/
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_S 0
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14)
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: reg_wifi_clk_en.*/
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_wifi_rst.*/
#define SYSCON_WIFI_RST 0xFFFFFFFF
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
#define SYSCON_WIFI_RST_S 0
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits, 6 */
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */
#define SYSTEM_WIFI_CLK_BT_EN 0x0
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Digital team to check */
//bluetooth baseband bit11
#define SYSTEM_BT_BASEBAND_EN BIT(11)
//bluetooth LC bit16 and bit17
#define SYSTEM_BT_LC_EN (BIT(16)|BIT(17))
/* Remaining single bit clock masks */
#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4)
#define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5)
#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSTEM_BB_RST BIT(0)
#define SYSTEM_FE_RST BIT(1)
#define SYSTEM_MAC_RST BIT(2)
#define SYSTEM_BT_RST BIT(3)
#define SYSTEM_BTMAC_RST BIT(4)
#define SYSTEM_SDIO_RST BIT(5)
#define SYSTEM_EMAC_RST BIT(7)
#define SYSTEM_MACPWR_RST BIT(8)
#define SYSTEM_RW_BTMAC_RST BIT(9)
#define SYSTEM_RW_BTLP_RST BIT(10)
#define BLE_REG_REST_BIT BIT(11)
#define BLE_PWR_REG_REST_BIT BIT(12)
#define BLE_BB_REG_REST_BIT BIT(13)
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: reg_peri_io_swap.*/
#define SYSCON_PERI_IO_SWAP 0x000000FF
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: reg_ext_mem_pms_lock.*/
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0))
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace0_attr.*/
#define SYSCON_FLASH_ACE0_ATTR 0x00000003
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
#define SYSCON_FLASH_ACE0_ATTR_V 0x3
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace1_attr.*/
#define SYSCON_FLASH_ACE1_ATTR 0x00000003
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
#define SYSCON_FLASH_ACE1_ATTR_V 0x3
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace2_attr.*/
#define SYSCON_FLASH_ACE2_ATTR 0x00000003
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
#define SYSCON_FLASH_ACE2_ATTR_V 0x3
#define SYSCON_FLASH_ACE2_ATTR_S 0
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
/*description: reg_flash_ace3_attr.*/
#define SYSCON_FLASH_ACE3_ATTR 0x00000003
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
#define SYSCON_FLASH_ACE3_ATTR_V 0x3
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_flash_ace0_addr_s.*/
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C)
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
/*description: reg_flash_ace1_addr_s.*/
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
/*description: reg_flash_ace2_addr_s.*/
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
/*description: reg_flash_ace3_addr_s.*/
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace0_size.*/
#define SYSCON_FLASH_ACE0_SIZE 0x00001FFF
#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
#define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF
#define SYSCON_FLASH_ACE0_SIZE_S 0
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C)
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace1_size.*/
#define SYSCON_FLASH_ACE1_SIZE 0x00001FFF
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
#define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace2_size.*/
#define SYSCON_FLASH_ACE2_SIZE 0x00001FFF
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
#define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
/*description: reg_flash_ace3_size.*/
#define SYSCON_FLASH_ACE3_SIZE 0x00001FFF
#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
#define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF
#define SYSCON_FLASH_ACE3_SIZE_S 0
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: reg_spi_mem_reject_cde.*/
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: reg_spi_mem_reject_clr.*/
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: reg_spi_mem_reject_int.*/
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
#define SYSCON_SPI_MEM_REJECT_INT_S 0
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C)
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: reg_spi_mem_reject_addr.*/
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: reg_sdio_win_access_en.*/
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: reg_redcy_andor.*/
#define SYSCON_REDCY_ANDOR (BIT(31))
#define SYSCON_REDCY_ANDOR_M (BIT(31))
#define SYSCON_REDCY_ANDOR_V 0x1
#define SYSCON_REDCY_ANDOR_S 31
/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: reg_redcy_sig0.*/
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_S 0
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: reg_redcy_nandor.*/
#define SYSCON_REDCY_NANDOR (BIT(31))
#define SYSCON_REDCY_NANDOR_M (BIT(31))
#define SYSCON_REDCY_NANDOR_V 0x1
#define SYSCON_REDCY_NANDOR_S 31
/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: reg_redcy_sig1.*/
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: reg_freq_mem_force_pd.*/
#define SYSCON_FREQ_MEM_FORCE_PD (BIT(7))
#define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7))
#define SYSCON_FREQ_MEM_FORCE_PD_V 0x1
#define SYSCON_FREQ_MEM_FORCE_PD_S 7
/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: reg_freq_mem_force_pu.*/
#define SYSCON_FREQ_MEM_FORCE_PU (BIT(6))
#define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6))
#define SYSCON_FREQ_MEM_FORCE_PU_V 0x1
#define SYSCON_FREQ_MEM_FORCE_PU_S 6
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: reg_dc_mem_force_pd.*/
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5))
#define SYSCON_DC_MEM_FORCE_PD_V 0x1
#define SYSCON_DC_MEM_FORCE_PD_S 5
/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: reg_dc_mem_force_pu.*/
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
#define SYSCON_DC_MEM_FORCE_PU_S 4
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: reg_pbus_mem_force_pd.*/
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3))
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: reg_pbus_mem_force_pu.*/
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2))
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reg_agc_mem_force_pd.*/
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1))
#define SYSCON_AGC_MEM_FORCE_PD_V 0x1
#define SYSCON_AGC_MEM_FORCE_PD_S 1
/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: reg_agc_mem_force_pu.*/
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0)
/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: reg_nobypass_cpu_iso_rst.*/
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: reg_retention_link_addr.*/
#define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
#define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_LINK_ADDR_S 0
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA4)
/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
hen only when have access the sram have clock.*/
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3
/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
en only when have access the rom have clock.*/
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007
#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xA8)
/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
/*description: Set 1 to let sram power down.*/
#define SYSCON_SRAM_POWER_DOWN 0x0000000F
#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
#define SYSCON_SRAM_POWER_DOWN_V 0xF
#define SYSCON_SRAM_POWER_DOWN_S 3
/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set 1 to let rom power down.*/
#define SYSCON_ROM_POWER_DOWN 0x00000007
#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
#define SYSCON_ROM_POWER_DOWN_V 0x7
#define SYSCON_ROM_POWER_DOWN_S 0
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xAC)
/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
/*description: Set 1 to let sram power up.*/
#define SYSCON_SRAM_POWER_UP 0x0000000F
#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
#define SYSCON_SRAM_POWER_UP_V 0xF
#define SYSCON_SRAM_POWER_UP_S 3
/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set 1 to let rom power up.*/
#define SYSCON_ROM_POWER_UP 0x00000007
#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
#define SYSCON_ROM_POWER_UP_V 0x7
#define SYSCON_ROM_POWER_UP_S 0
#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xB0)
/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: reg_rnd_data.*/
#define SYSCON_RND_DATA 0xFFFFFFFF
#define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
#define SYSCON_RND_DATA_V 0xFFFFFFFF
#define SYSCON_RND_DATA_S 0
#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xB4)
/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: reg_peri_backup_ena.*/
#define SYSCON_PERI_BACKUP_ENA (BIT(31))
#define SYSCON_PERI_BACKUP_ENA_M (BIT(31))
#define SYSCON_PERI_BACKUP_ENA_V 0x1
#define SYSCON_PERI_BACKUP_ENA_S 31
/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: reg_peri_backup_to_mem.*/
#define SYSCON_PERI_BACKUP_TO_MEM (BIT(30))
#define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30))
#define SYSCON_PERI_BACKUP_TO_MEM_V 0x1
#define SYSCON_PERI_BACKUP_TO_MEM_S 30
/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: reg_peri_backup_start.*/
#define SYSCON_PERI_BACKUP_START (BIT(29))
#define SYSCON_PERI_BACKUP_START_M (BIT(29))
#define SYSCON_PERI_BACKUP_START_V 0x1
#define SYSCON_PERI_BACKUP_START_S 29
/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
/*description: reg_peri_backup_size.*/
#define SYSCON_PERI_BACKUP_SIZE 0x000003FF
#define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
#define SYSCON_PERI_BACKUP_SIZE_V 0x3FF
#define SYSCON_PERI_BACKUP_SIZE_S 19
/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
/*description: reg_peri_backup_tout_thres.*/
#define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF
#define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
#define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF
#define SYSCON_PERI_BACKUP_TOUT_THRES_S 9
/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
/*description: reg_peri_backup_burst_limit.*/
#define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F
#define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F
#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4
/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
/*description: reg_peri_backup_flow_err.*/
#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003
#define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3
#define SYSCON_PERI_BACKUP_FLOW_ERR_S 1
#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xB8)
/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: reg_backup_apb_start_addr.*/
#define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
#define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define SYSCON_BACKUP_APB_START_ADDR_S 0
#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xBC)
/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: reg_backup_mem_start_addr.*/
#define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
#define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define SYSCON_BACKUP_MEM_START_ADDR_S 0
#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xC0)
/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_raw.*/
#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1
/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_raw.*/
#define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0
#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xC4)
/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_st.*/
#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1
#define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1
/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_st.*/
#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0
#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xC8)
/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_ena.*/
#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1
/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_ena.*/
#define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0
#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xD0)
/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
/*description: reg_peri_backup_err_int_clr.*/
#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1
/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
/*description: reg_peri_backup_done_int_clr.*/
#define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
/*description: reg_dateVersion control.*/
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
#define SYSCON_DATE_V 0xFFFFFFFF
#define SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSCON_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct syscon_dev_s{
union {
struct {
uint32_t pre_div : 10; /*reg_pre_div_cnt*/
uint32_t clk_320m_en : 1; /*reg_clk_320m_en*/
uint32_t clk_en : 1; /*reg_clk_en*/
uint32_t rst_tick : 1; /*reg_rst_tick_cnt*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t xtal_tick : 8; /*reg_xtal_tick_num*/
uint32_t ck8m_tick : 8; /*reg_ck8m_tick_num*/
uint32_t tick_enable : 1; /*reg_tick_enable*/
uint32_t reserved17 : 15; /*Reserved.*/
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t clk20_oen : 1; /*reg_clk20_oen*/
uint32_t clk22_oen : 1; /*reg_clk22_oen*/
uint32_t clk44_oen : 1; /*reg_clk44_oen*/
uint32_t clk_bb_oen : 1; /*reg_clk_bb_oen*/
uint32_t clk80_oen : 1; /*reg_clk80_oen*/
uint32_t clk160_oen : 1; /*reg_clk160_oen*/
uint32_t clk_320m_oen : 1; /*reg_clk_320m_oen*/
uint32_t clk_adc_inf_oen : 1; /*reg_clk_adc_inf_oen*/
uint32_t clk_dac_cpu_oen : 1; /*reg_clk_dac_cpu_oen*/
uint32_t clk40x_bb_oen : 1; /*reg_clk40x_bb_oen*/
uint32_t clk_xtal_oen : 1; /*reg_clk_xtal_oen*/
uint32_t reserved11 : 21; /*Reserved.*/
};
uint32_t val;
} clk_out_en;
uint32_t wifi_bb_cfg;
uint32_t wifi_bb_cfg_2;
uint32_t wifi_clk_en;
uint32_t wifi_rst_en;
union {
struct {
uint32_t peri_io_swap : 8; /*reg_peri_io_swap*/
uint32_t reserved8 : 24; /*Reserved.*/
};
uint32_t val;
} host_inf_sel;
union {
struct {
uint32_t ext_mem_pms_lock : 1; /*reg_ext_mem_pms_lock*/
uint32_t reserved1 : 31; /*Reserved.*/
};
uint32_t val;
} ext_mem_pms_lock;
uint32_t reserved_24;
union {
struct {
uint32_t flash_ace0_attr : 2; /*reg_flash_ace0_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr : 2; /*reg_flash_ace1_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr : 2; /*reg_flash_ace2_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr : 2; /*reg_flash_ace3_attr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr;
uint32_t flash_ace1_addr;
uint32_t flash_ace2_addr;
uint32_t flash_ace3_addr;
union {
struct {
uint32_t flash_ace0_size : 13; /*reg_flash_ace0_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace0_size;
union {
struct {
uint32_t flash_ace1_size : 13; /*reg_flash_ace1_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace1_size;
union {
struct {
uint32_t flash_ace2_size : 13; /*reg_flash_ace2_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace2_size;
union {
struct {
uint32_t flash_ace3_size : 13; /*reg_flash_ace3_size*/
uint32_t reserved13 : 19; /*Reserved.*/
};
uint32_t val;
} flash_ace3_size;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
union {
struct {
uint32_t spi_mem_reject_int : 1; /*reg_spi_mem_reject_int*/
uint32_t spi_mem_reject_clr : 1; /*reg_spi_mem_reject_clr*/
uint32_t spi_mem_reject_cde : 5; /*reg_spi_mem_reject_cde*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr;
union {
struct {
uint32_t sdio_win_access_en : 1; /*reg_sdio_win_access_en*/
uint32_t reserved1 : 31; /*Reserved.*/
};
uint32_t val;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0 : 31; /*reg_redcy_sig0*/
uint32_t redcy_andor : 1; /*reg_redcy_andor*/
};
uint32_t val;
} redcy_sig0;
union {
struct {
uint32_t redcy_sig1 : 31; /*reg_redcy_sig1*/
uint32_t redcy_nandor : 1; /*reg_redcy_nandor*/
};
uint32_t val;
} redcy_sig1;
union {
struct {
uint32_t agc_mem_force_pu : 1; /*reg_agc_mem_force_pu*/
uint32_t agc_mem_force_pd : 1; /*reg_agc_mem_force_pd*/
uint32_t pbus_mem_force_pu : 1; /*reg_pbus_mem_force_pu*/
uint32_t pbus_mem_force_pd : 1; /*reg_pbus_mem_force_pd*/
uint32_t dc_mem_force_pu : 1; /*reg_dc_mem_force_pu*/
uint32_t dc_mem_force_pd : 1; /*reg_dc_mem_force_pd*/
uint32_t freq_mem_force_pu : 1; /*reg_freq_mem_force_pu*/
uint32_t freq_mem_force_pd : 1; /*reg_freq_mem_force_pd*/
uint32_t reserved8 : 24; /*Reserved.*/
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t retention_link_addr : 27; /*reg_retention_link_addr*/
uint32_t nobypass_cpu_iso_rst : 1; /*reg_nobypass_cpu_iso_rst*/
uint32_t reserved28 : 4; /*Reserved.*/
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t rom_clkgate_force_on : 3; /*Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock*/
uint32_t sram_clkgate_force_on : 4; /*Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down : 3; /*Set 1 to let rom power down*/
uint32_t sram_power_down : 4; /*Set 1 to let sram power down*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up : 3; /*Set 1 to let rom power up*/
uint32_t sram_power_up : 4; /*Set 1 to let sram power up*/
uint32_t reserved7 : 25; /*Reserved.*/
};
uint32_t val;
} mem_power_up;
uint32_t rnd_data;
union {
struct {
uint32_t reserved0 : 1; /*Reserved.*/
uint32_t peri_backup_flow_err : 2; /*reg_peri_backup_flow_err*/
uint32_t reserved3 : 1; /*Reserved.*/
uint32_t peri_backup_burst_limit : 5; /*reg_peri_backup_burst_limit*/
uint32_t peri_backup_tout_thres : 10; /*reg_peri_backup_tout_thres*/
uint32_t peri_backup_size : 10; /*reg_peri_backup_size*/
uint32_t peri_backup_start : 1; /*reg_peri_backup_start*/
uint32_t peri_backup_to_mem : 1; /*reg_peri_backup_to_mem*/
uint32_t peri_backup_ena : 1; /*reg_peri_backup_ena*/
};
uint32_t val;
} peri_backup_config;
uint32_t peri_backup_addr;
uint32_t peri_backup_mem_addr;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_raw*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_raw*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_raw;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_st*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_st*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_st;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_ena*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_ena*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_ena;
uint32_t reserved_cc;
union {
struct {
uint32_t peri_backup_done : 1; /*reg_peri_backup_done_int_clr*/
uint32_t peri_backup_err : 1; /*reg_peri_backup_err_int_clr*/
uint32_t reserved2 : 30; /*Reserved.*/
};
uint32_t val;
} peri_backup_int_clr;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date;
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSCON_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSTEM_REG_H_
#define _SOC_SYSTEM_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0)
/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set 1 to open dedicated_gpio module clk.*/
#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))
#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7))
#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1
#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7
/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set 1 to open assist_debug module clock.*/
#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))
#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6))
#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1
#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6
#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4)
/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: Set 1 to let dedicated_gpio module reset.*/
#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7))
#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7))
#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1
#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7
/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: Set 1 to let assist_debug module reset.*/
#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6))
#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6))
#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1
#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6
#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8)
/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
/*description: This field used to set delay cycle when cpu enter waiti mode, after delay waiti_
clk will close.*/
#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F
#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF
#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4
/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: Set 1 to force cpu_waiti_clk enable..*/
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3))
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3
/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: This field used to sel pll frequent..*/
#define SYSTEM_PLL_FREQ_SEL (BIT(2))
#define SYSTEM_PLL_FREQ_SEL_M (BIT(2))
#define SYSTEM_PLL_FREQ_SEL_V 0x1
#define SYSTEM_PLL_FREQ_SEL_S 2
/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: This field used to sel cpu clock frequent..*/
#define SYSTEM_CPUPERIOD_SEL 0x00000003
#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
#define SYSTEM_CPUPERIOD_SEL_V 0x3
#define SYSTEM_CPUPERIOD_SEL_S 0
#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xC)
/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Set 1 to mask memory power down..*/
#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0))
#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0))
#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1
#define SYSTEM_LSLP_MEM_PD_MASK_S 0
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x10)
/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: Set 1 to enable ADC2_ARB clock.*/
#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30))
#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30))
#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1
#define SYSTEM_ADC2_ARB_CLK_EN_S 30
/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
/*description: Set 1 to enable SYSTEMTIMER clock.*/
#define SYSTEM_SYSTIMER_CLK_EN (BIT(29))
#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29))
#define SYSTEM_SYSTIMER_CLK_EN_V 0x1
#define SYSTEM_SYSTIMER_CLK_EN_S 29
/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: Set 1 to enable APB_SARADC clock.*/
#define SYSTEM_APB_SARADC_CLK_EN (BIT(28))
#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28))
#define SYSTEM_APB_SARADC_CLK_EN_V 0x1
#define SYSTEM_APB_SARADC_CLK_EN_S 28
/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
/*description: Set 1 to enable UART_MEM clock.*/
#define SYSTEM_UART_MEM_CLK_EN (BIT(24))
#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24))
#define SYSTEM_UART_MEM_CLK_EN_V 0x1
#define SYSTEM_UART_MEM_CLK_EN_S 24
/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: Set 1 to enable TIMERGROUP clock.*/
#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13))
#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13))
#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1
#define SYSTEM_TIMERGROUP_CLK_EN_S 13
/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set 1 to enable LEDC clock.*/
#define SYSTEM_LEDC_CLK_EN (BIT(11))
#define SYSTEM_LEDC_CLK_EN_M (BIT(11))
#define SYSTEM_LEDC_CLK_EN_V 0x1
#define SYSTEM_LEDC_CLK_EN_S 11
/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set 1 to enable I2C_EXT0 clock.*/
#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7))
#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7))
#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1
#define SYSTEM_I2C_EXT0_CLK_EN_S 7
/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: Set 1 to enable SPI2 clock.*/
#define SYSTEM_SPI2_CLK_EN (BIT(6))
#define SYSTEM_SPI2_CLK_EN_M (BIT(6))
#define SYSTEM_SPI2_CLK_EN_V 0x1
#define SYSTEM_SPI2_CLK_EN_S 6
/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: Set 1 to enable UART1 clock.*/
#define SYSTEM_UART1_CLK_EN (BIT(5))
#define SYSTEM_UART1_CLK_EN_M (BIT(5))
#define SYSTEM_UART1_CLK_EN_V 0x1
#define SYSTEM_UART1_CLK_EN_S 5
/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Set 1 to enable UART clock.*/
#define SYSTEM_UART_CLK_EN (BIT(2))
#define SYSTEM_UART_CLK_EN_M (BIT(2))
#define SYSTEM_UART_CLK_EN_V 0x1
#define SYSTEM_UART_CLK_EN_S 2
/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: Set 1 to enable SPI01 clock.*/
#define SYSTEM_SPI01_CLK_EN (BIT(1))
#define SYSTEM_SPI01_CLK_EN_M (BIT(1))
#define SYSTEM_SPI01_CLK_EN_V 0x1
#define SYSTEM_SPI01_CLK_EN_S 1
#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x14)
/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set 1 to enable TSENS clock.*/
#define SYSTEM_TSENS_CLK_EN (BIT(10))
#define SYSTEM_TSENS_CLK_EN_M (BIT(10))
#define SYSTEM_TSENS_CLK_EN_V 0x1
#define SYSTEM_TSENS_CLK_EN_S 10
/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set 1 to enable DMA clock.*/
#define SYSTEM_DMA_CLK_EN (BIT(6))
#define SYSTEM_DMA_CLK_EN_M (BIT(6))
#define SYSTEM_DMA_CLK_EN_V 0x1
#define SYSTEM_DMA_CLK_EN_S 6
/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set 1 to enable SHA clock.*/
#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2))
#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2))
#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2
/* SYSTEM_CRYPTO_ECC_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to enable ECC clock.*/
#define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(1))
#define SYSTEM_CRYPTO_ECC_CLK_EN_M (BIT(1))
#define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_ECC_CLK_EN_S 1
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x18)
/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set 1 to let ADC2_ARB reset.*/
#define SYSTEM_ADC2_ARB_RST (BIT(30))
#define SYSTEM_ADC2_ARB_RST_M (BIT(30))
#define SYSTEM_ADC2_ARB_RST_V 0x1
#define SYSTEM_ADC2_ARB_RST_S 30
/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set 1 to let SYSTIMER reset.*/
#define SYSTEM_SYSTIMER_RST (BIT(29))
#define SYSTEM_SYSTIMER_RST_M (BIT(29))
#define SYSTEM_SYSTIMER_RST_V 0x1
#define SYSTEM_SYSTIMER_RST_S 29
/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Set 1 to let APB_SARADC reset.*/
#define SYSTEM_APB_SARADC_RST (BIT(28))
#define SYSTEM_APB_SARADC_RST_M (BIT(28))
#define SYSTEM_APB_SARADC_RST_V 0x1
#define SYSTEM_APB_SARADC_RST_S 28
/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: Set 1 to let UART_MEM reset.*/
#define SYSTEM_UART_MEM_RST (BIT(24))
#define SYSTEM_UART_MEM_RST_M (BIT(24))
#define SYSTEM_UART_MEM_RST_V 0x1
#define SYSTEM_UART_MEM_RST_S 24
/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Set 1 to let TIMERGROUP reset.*/
#define SYSTEM_TIMERGROUP_RST (BIT(13))
#define SYSTEM_TIMERGROUP_RST_M (BIT(13))
#define SYSTEM_TIMERGROUP_RST_V 0x1
#define SYSTEM_TIMERGROUP_RST_S 13
/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set 1 to let LEDC reset.*/
#define SYSTEM_LEDC_RST (BIT(11))
#define SYSTEM_LEDC_RST_M (BIT(11))
#define SYSTEM_LEDC_RST_V 0x1
#define SYSTEM_LEDC_RST_S 11
/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set 1 to let I2C_EXT0 reset.*/
#define SYSTEM_I2C_EXT0_RST (BIT(7))
#define SYSTEM_I2C_EXT0_RST_M (BIT(7))
#define SYSTEM_I2C_EXT0_RST_V 0x1
#define SYSTEM_I2C_EXT0_RST_S 7
/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set 1 to let SPI2 reset.*/
#define SYSTEM_SPI2_RST (BIT(6))
#define SYSTEM_SPI2_RST_M (BIT(6))
#define SYSTEM_SPI2_RST_V 0x1
#define SYSTEM_SPI2_RST_S 6
/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set 1 to let UART1 reset.*/
#define SYSTEM_UART1_RST (BIT(5))
#define SYSTEM_UART1_RST_M (BIT(5))
#define SYSTEM_UART1_RST_V 0x1
#define SYSTEM_UART1_RST_S 5
/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set 1 to let UART reset.*/
#define SYSTEM_UART_RST (BIT(2))
#define SYSTEM_UART_RST_M (BIT(2))
#define SYSTEM_UART_RST_V 0x1
#define SYSTEM_UART_RST_S 2
/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to let SPI01 reset.*/
#define SYSTEM_SPI01_RST (BIT(1))
#define SYSTEM_SPI01_RST_M (BIT(1))
#define SYSTEM_SPI01_RST_V 0x1
#define SYSTEM_SPI01_RST_S 1
#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C)
/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set 1 to let TSENS reset.*/
#define SYSTEM_TSENS_RST (BIT(10))
#define SYSTEM_TSENS_RST_M (BIT(10))
#define SYSTEM_TSENS_RST_V 0x1
#define SYSTEM_TSENS_RST_S 10
/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: Set 1 to let DMA reset.*/
#define SYSTEM_DMA_RST (BIT(6))
#define SYSTEM_DMA_RST_M (BIT(6))
#define SYSTEM_DMA_RST_V 0x1
#define SYSTEM_DMA_RST_S 6
/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Set 1 to let CRYPTO_SHA reset.*/
#define SYSTEM_CRYPTO_SHA_RST (BIT(2))
#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2))
#define SYSTEM_CRYPTO_SHA_RST_V 0x1
#define SYSTEM_CRYPTO_SHA_RST_S 2
/* SYSTEM_CRYPTO_ECC_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: Set 1 to let CRYPTO_ECC reset.*/
#define SYSTEM_CRYPTO_ECC_RST (BIT(1))
#define SYSTEM_CRYPTO_ECC_RST_M (BIT(1))
#define SYSTEM_CRYPTO_ECC_RST_V 0x1
#define SYSTEM_CRYPTO_ECC_RST_S 1
#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x20)
/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
/*description: This field is lower power clock frequent division factor.*/
#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_NUM_S 0
#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x24)
/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: Set 1 to enable RTC low power clock.*/
#define SYSTEM_LPCLK_RTC_EN (BIT(28))
#define SYSTEM_LPCLK_RTC_EN_M (BIT(28))
#define SYSTEM_LPCLK_RTC_EN_V 0x1
#define SYSTEM_LPCLK_RTC_EN_S 28
/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: Set 1 to select xtal32k clock as low power clock.*/
#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27))
#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27))
#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1
#define SYSTEM_LPCLK_SEL_XTAL32K_S 27
/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: Set 1 to select xtal clock as rtc low power clock.*/
#define SYSTEM_LPCLK_SEL_XTAL (BIT(26))
#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26))
#define SYSTEM_LPCLK_SEL_XTAL_V 0x1
#define SYSTEM_LPCLK_SEL_XTAL_S 26
/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: Set 1 to select 8m clock as rtc low power clock.*/
#define SYSTEM_LPCLK_SEL_8M (BIT(25))
#define SYSTEM_LPCLK_SEL_8M_M (BIT(25))
#define SYSTEM_LPCLK_SEL_8M_V 0x1
#define SYSTEM_LPCLK_SEL_8M_S 25
/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: Set 1 to select rtc-slow clock as rtc low power clock.*/
#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24))
#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24))
#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1
#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24
/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
/*description: This field is lower power clock frequent division factor a.*/
#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_A_S 12
/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
/*description: This field is lower power clock frequent division factor b.*/
#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_B_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x28)
/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to generate cpu interrupt 0.*/
#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x2C)
/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to generate cpu interrupt 1.*/
#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x30)
/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to generate cpu interrupt 2.*/
#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x34)
/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to generate cpu interrupt 3.*/
#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38)
/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set 1 to force power down RSA memory. This bit has the highest priority..*/
#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2))
#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2))
#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1
#define SYSTEM_RSA_MEM_FORCE_PD_S 2
/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to force power up RSA memory. This bit has the second highest priority..*/
#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1))
#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1))
#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1
#define SYSTEM_RSA_MEM_FORCE_PU_S 1
/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Si
gnature occupies the RSA. This bit is invalid..*/
#define SYSTEM_RSA_MEM_PD (BIT(0))
#define SYSTEM_RSA_MEM_PD_M (BIT(0))
#define SYSTEM_RSA_MEM_PD_V 0x1
#define SYSTEM_RSA_MEM_PD_S 0
#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x3C)
/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to let EDMA reset.*/
#define SYSTEM_EDMA_RESET (BIT(1))
#define SYSTEM_EDMA_RESET_M (BIT(1))
#define SYSTEM_EDMA_RESET_V 0x1
#define SYSTEM_EDMA_RESET_S 1
/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Set 1 to enable EDMA clock..*/
#define SYSTEM_EDMA_CLK_ON (BIT(0))
#define SYSTEM_EDMA_CLK_ON_M (BIT(0))
#define SYSTEM_EDMA_CLK_ON_V 0x1
#define SYSTEM_EDMA_CLK_ON_S 0
#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x40)
/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set 1 to let dcache reset.*/
#define SYSTEM_DCACHE_RESET (BIT(3))
#define SYSTEM_DCACHE_RESET_M (BIT(3))
#define SYSTEM_DCACHE_RESET_V 0x1
#define SYSTEM_DCACHE_RESET_S 3
/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: Set 1 to enable dcache clock.*/
#define SYSTEM_DCACHE_CLK_ON (BIT(2))
#define SYSTEM_DCACHE_CLK_ON_M (BIT(2))
#define SYSTEM_DCACHE_CLK_ON_V 0x1
#define SYSTEM_DCACHE_CLK_ON_S 2
/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to let icache reset.*/
#define SYSTEM_ICACHE_RESET (BIT(1))
#define SYSTEM_ICACHE_RESET_M (BIT(1))
#define SYSTEM_ICACHE_RESET_V 0x1
#define SYSTEM_ICACHE_RESET_S 1
/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: Set 1 to enable icache clock.*/
#define SYSTEM_ICACHE_CLK_ON (BIT(0))
#define SYSTEM_ICACHE_CLK_ON_M (BIT(0))
#define SYSTEM_ICACHE_CLK_ON_V 0x1
#define SYSTEM_ICACHE_CLK_ON_S 0
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x44)
/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set 1 to enable download manual encrypt.*/
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3))
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set 1 to enable download G0CB decrypt.*/
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2))
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1
#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to enable download DB encrypt..*/
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1))
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1
#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to enable the SPI manual encrypt..*/
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0))
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x48)
/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: This bit stores the status of RTC memory CRC.1 means finished..*/
#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31))
#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31))
#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1
#define SYSTEM_RTC_MEM_CRC_FINISH_S 31
/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
/*description: This field is used to set length of RTC memory for CRC based on start address..*/
#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF
#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF
#define SYSTEM_RTC_MEM_CRC_LEN_S 20
/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
/*description: This field is used to set address of RTC memory for CRC..*/
#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF
#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF
#define SYSTEM_RTC_MEM_CRC_ADDR_S 9
/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set 1 to start the CRC of RTC memory.*/
#define SYSTEM_RTC_MEM_CRC_START (BIT(8))
#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8))
#define SYSTEM_RTC_MEM_CRC_START_V 0x1
#define SYSTEM_RTC_MEM_CRC_START_S 8
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x4C)
/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: This field stores the CRC result of RTC memory..*/
#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF
#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF
#define SYSTEM_RTC_MEM_CRC_RES_S 0
#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x50)
/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: reg_redundant_eco_result.*/
#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1))
#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1))
#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1
#define SYSTEM_REDUNDANT_ECO_RESULT_S 1
/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: reg_redundant_eco_drive.*/
#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0))
#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0))
#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1
#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x54)
/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: reg_clk_en.*/
#define SYSTEM_CLK_EN (BIT(0))
#define SYSTEM_CLK_EN_M (BIT(0))
#define SYSTEM_CLK_EN_V 0x1
#define SYSTEM_CLK_EN_S 0
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x58)
/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
/*description: reg_clk_div_en.*/
#define SYSTEM_CLK_DIV_EN (BIT(19))
#define SYSTEM_CLK_DIV_EN_M (BIT(19))
#define SYSTEM_CLK_DIV_EN_V 0x1
#define SYSTEM_CLK_DIV_EN_S 19
/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
/*description: This field is used to read xtal frequency in MHz..*/
#define SYSTEM_CLK_XTAL_FREQ 0x0000007F
#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
#define SYSTEM_CLK_XTAL_FREQ_V 0x7F
#define SYSTEM_CLK_XTAL_FREQ_S 12
/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
/*description: This field is used to select soc clock..*/
#define SYSTEM_SOC_CLK_SEL 0x00000003
#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
#define SYSTEM_SOC_CLK_SEL_V 0x3
#define SYSTEM_SOC_CLK_SEL_S 10
/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: This field is used to set the count of prescaler of XTAL_CLK..*/
#define SYSTEM_PRE_DIV_CNT 0x000003FF
#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
#define SYSTEM_PRE_DIV_CNT_V 0x3FF
#define SYSTEM_PRE_DIV_CNT_S 0
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x5C)
/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
/*description: reg_mem_vt_sel.*/
#define SYSTEM_MEM_VT_SEL 0x00000003
#define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
#define SYSTEM_MEM_VT_SEL_V 0x3
#define SYSTEM_MEM_VT_SEL_S 22
/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
/*description: reg_mem_timing_err_cnt.*/
#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF
#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF
#define SYSTEM_MEM_TIMING_ERR_CNT_S 6
/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: reg_mem_pvt_monitor_en.*/
#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5))
#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5))
#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1
#define SYSTEM_MEM_PVT_MONITOR_EN_S 5
/* SYSTEM_MEM_ERR_CNT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: reg_mem_err_cnt_clr.*/
#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4))
#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4))
#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1
#define SYSTEM_MEM_ERR_CNT_CLR_S 4
/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
/*description: reg_mem_path_len.*/
#define SYSTEM_MEM_PATH_LEN 0x0000000F
#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
#define SYSTEM_MEM_PATH_LEN_V 0xF
#define SYSTEM_MEM_PATH_LEN_S 0
#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x60)
/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: reg_comb_pvt_monitor_en_lvt.*/
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(7))
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(7))
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 7
/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: reg_comb_err_cnt_clr_lvt.*/
#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(6))
#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(6))
#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1
#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 6
/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: reg_comb_path_len_lvt.*/
#define SYSTEM_COMB_PATH_LEN_LVT 0x0000003F
#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
#define SYSTEM_COMB_PATH_LEN_LVT_V 0x3F
#define SYSTEM_COMB_PATH_LEN_LVT_S 0
#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x64)
/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: reg_comb_pvt_monitor_en_nvt.*/
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(7))
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(7))
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 7
/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: reg_comb_err_cnt_clr_nvt.*/
#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(6))
#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(6))
#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1
#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 6
/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: reg_comb_path_len_nvt.*/
#define SYSTEM_COMB_PATH_LEN_NVT 0x0000003F
#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
#define SYSTEM_COMB_PATH_LEN_NVT_V 0x3F
#define SYSTEM_COMB_PATH_LEN_NVT_S 0
#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68)
/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: reg_comb_pvt_monitor_en_hvt.*/
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(7))
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(7))
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 7
/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: reg_comb_err_cnt_clr_hvt.*/
#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(6))
#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(6))
#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1
#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 6
/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: reg_comb_path_len_hvt.*/
#define SYSTEM_COMB_PATH_LEN_HVT 0x0000003F
#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
#define SYSTEM_COMB_PATH_LEN_HVT_V 0x3F
#define SYSTEM_COMB_PATH_LEN_HVT_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x6C)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_lvt_site0.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x70)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_nvt_site0.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_hvt_site0.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x78)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_lvt_site1.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x7C)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_nvt_site1.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_hvt_site1.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x84)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_lvt_site2.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x88)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_nvt_site2.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8C)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_hvt_site2.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x90)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_lvt_site3.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x94)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_nvt_site3.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: reg_comb_timing_err_cnt_hvt_site3.*/
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0
#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC)
/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
/*description: reg_system_reg_date.*/
#define SYSTEM_DATE 0x0FFFFFFF
#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
#define SYSTEM_DATE_V 0xFFFFFFF
#define SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSTEM_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_SYSTIMER_REG_H_
#define _SOC_SYSTIMER_REG_H_
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/* SYSTIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating.*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (BIT(31))
#define SYSTIMER_CLK_EN_V 0x1
#define SYSTIMER_CLK_EN_S 31
/* SYSTIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: timer unit0 work enable.*/
#define SYSTIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_UNIT0_WORK_EN_M (BIT(30))
#define SYSTIMER_UNIT0_WORK_EN_V 0x1
#define SYSTIMER_UNIT0_WORK_EN_S 30
/* SYSTIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer unit1 work enable.*/
#define SYSTIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_UNIT1_WORK_EN_M (BIT(29))
#define SYSTIMER_UNIT1_WORK_EN_V 0x1
#define SYSTIMER_UNIT1_WORK_EN_S 29
/* SYSTIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core0 stalled.*/
#define SYSTIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_UNIT0_CORE0_STALL_EN_M (BIT(28))
#define SYSTIMER_UNIT0_CORE0_STALL_EN_V 0x1
#define SYSTIMER_UNIT0_CORE0_STALL_EN_S 28
/* SYSTIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core1 stalled.*/
#define SYSTIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_UNIT0_CORE1_STALL_EN_M (BIT(27))
#define SYSTIMER_UNIT0_CORE1_STALL_EN_V 0x1
#define SYSTIMER_UNIT0_CORE1_STALL_EN_S 27
/* SYSTIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core0 stalled.*/
#define SYSTIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_UNIT1_CORE0_STALL_EN_M (BIT(26))
#define SYSTIMER_UNIT1_CORE0_STALL_EN_V 0x1
#define SYSTIMER_UNIT1_CORE0_STALL_EN_S 26
/* SYSTIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core1 stalled.*/
#define SYSTIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_UNIT1_CORE1_STALL_EN_M (BIT(25))
#define SYSTIMER_UNIT1_CORE1_STALL_EN_V 0x1
#define SYSTIMER_UNIT1_CORE1_STALL_EN_S 25
/* SYSTIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: target0 work enable.*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_V 0x1
#define SYSTIMER_TARGET0_WORK_EN_S 24
/* SYSTIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: target1 work enable.*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_V 0x1
#define SYSTIMER_TARGET1_WORK_EN_S 23
/* SYSTIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: target2 work enable.*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_V 0x1
#define SYSTIMER_TARGET2_WORK_EN_S 22
/* SYSTIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: systimer clock force on.*/
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYSTIMER_SYSTIMER_CLK_FO_M (BIT(0))
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x1
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/* SYSTIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer_unit0.*/
#define SYSTIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_UNIT0_UPDATE_M (BIT(30))
#define SYSTIMER_UNIT0_UPDATE_V 0x1
#define SYSTIMER_UNIT0_UPDATE_S 30
/* SYSTIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer value is sync and valid.*/
#define SYSTIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_UNIT0_VALUE_VALID_M (BIT(29))
#define SYSTIMER_UNIT0_VALUE_VALID_V 0x1
#define SYSTIMER_UNIT0_VALUE_VALID_S 29
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/* SYSTIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer unit1.*/
#define SYSTIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_UNIT1_UPDATE_M (BIT(30))
#define SYSTIMER_UNIT1_UPDATE_V 0x1
#define SYSTIMER_UNIT1_UPDATE_S 30
/* SYSTIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer value is sync and valid.*/
#define SYSTIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_UNIT1_VALUE_VALID_M (BIT(29))
#define SYSTIMER_UNIT1_VALUE_VALID_V 0x1
#define SYSTIMER_UNIT1_VALUE_VALID_S 29
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xC)
/* SYSTIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit0 load high 20 bits.*/
#define SYSTIMER_UNIT0_LOAD_HI 0x000FFFFF
#define SYSTIMER_UNIT0_LOAD_HI_M ((SYSTIMER_UNIT0_LOAD_HI_V)<<(SYSTIMER_UNIT0_LOAD_HI_S))
#define SYSTIMER_UNIT0_LOAD_HI_V 0xFFFFF
#define SYSTIMER_UNIT0_LOAD_HI_S 0
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/* SYSTIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit0 load low 32 bits.*/
#define SYSTIMER_UNIT0_LOAD_LO 0xFFFFFFFF
#define SYSTIMER_UNIT0_LOAD_LO_M ((SYSTIMER_UNIT0_LOAD_LO_V)<<(SYSTIMER_UNIT0_LOAD_LO_S))
#define SYSTIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
#define SYSTIMER_UNIT0_LOAD_LO_S 0
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/* SYSTIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit1 load high 20 bits.*/
#define SYSTIMER_UNIT1_LOAD_HI 0x000FFFFF
#define SYSTIMER_UNIT1_LOAD_HI_M ((SYSTIMER_UNIT1_LOAD_HI_V)<<(SYSTIMER_UNIT1_LOAD_HI_S))
#define SYSTIMER_UNIT1_LOAD_HI_V 0xFFFFF
#define SYSTIMER_UNIT1_LOAD_HI_S 0
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/* SYSTIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit1 load low 32 bits.*/
#define SYSTIMER_UNIT1_LOAD_LO 0xFFFFFFFF
#define SYSTIMER_UNIT1_LOAD_LO_M ((SYSTIMER_UNIT1_LOAD_LO_V)<<(SYSTIMER_UNIT1_LOAD_LO_S))
#define SYSTIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
#define SYSTIMER_UNIT1_LOAD_LO_S 0
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1C)
/* SYSTIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget0 high 20 bits.*/
#define SYSTIMER_TARGET0_HI 0x000FFFFF
#define SYSTIMER_TARGET0_HI_M ((SYSTIMER_TARGET0_HI_V)<<(SYSTIMER_TARGET0_HI_S))
#define SYSTIMER_TARGET0_HI_V 0xFFFFF
#define SYSTIMER_TARGET0_HI_S 0
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/* SYSTIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget0 low 32 bits.*/
#define SYSTIMER_TARGET0_LO 0xFFFFFFFF
#define SYSTIMER_TARGET0_LO_M ((SYSTIMER_TARGET0_LO_V)<<(SYSTIMER_TARGET0_LO_S))
#define SYSTIMER_TARGET0_LO_V 0xFFFFFFFF
#define SYSTIMER_TARGET0_LO_S 0
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/* SYSTIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget1 high 20 bits.*/
#define SYSTIMER_TARGET1_HI 0x000FFFFF
#define SYSTIMER_TARGET1_HI_M ((SYSTIMER_TARGET1_HI_V)<<(SYSTIMER_TARGET1_HI_S))
#define SYSTIMER_TARGET1_HI_V 0xFFFFF
#define SYSTIMER_TARGET1_HI_S 0
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/* SYSTIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget1 low 32 bits.*/
#define SYSTIMER_TARGET1_LO 0xFFFFFFFF
#define SYSTIMER_TARGET1_LO_M ((SYSTIMER_TARGET1_LO_V)<<(SYSTIMER_TARGET1_LO_S))
#define SYSTIMER_TARGET1_LO_V 0xFFFFFFFF
#define SYSTIMER_TARGET1_LO_S 0
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2C)
/* SYSTIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget2 high 20 bits.*/
#define SYSTIMER_TARGET2_HI 0x000FFFFF
#define SYSTIMER_TARGET2_HI_M ((SYSTIMER_TARGET2_HI_V)<<(SYSTIMER_TARGET2_HI_S))
#define SYSTIMER_TARGET2_HI_V 0xFFFFF
#define SYSTIMER_TARGET2_HI_S 0
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/* SYSTIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget2 low 32 bits.*/
#define SYSTIMER_TARGET2_LO 0xFFFFFFFF
#define SYSTIMER_TARGET2_LO_M ((SYSTIMER_TARGET2_LO_V)<<(SYSTIMER_TARGET2_LO_S))
#define SYSTIMER_TARGET2_LO_V 0xFFFFFFFF
#define SYSTIMER_TARGET2_LO_S 0
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare.*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x1
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
/* SYSTIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target0 to period mode.*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x1
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/* SYSTIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target0 period.*/
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET0_PERIOD_M ((SYSTIMER_TARGET0_PERIOD_V)<<(SYSTIMER_TARGET0_PERIOD_S))
#define SYSTIMER_TARGET0_PERIOD_V 0x3FFFFFF
#define SYSTIMER_TARGET0_PERIOD_S 0
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare.*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x1
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
/* SYSTIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target1 to period mode.*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x1
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/* SYSTIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target1 period.*/
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET1_PERIOD_M ((SYSTIMER_TARGET1_PERIOD_V)<<(SYSTIMER_TARGET1_PERIOD_S))
#define SYSTIMER_TARGET1_PERIOD_V 0x3FFFFFF
#define SYSTIMER_TARGET1_PERIOD_S 0
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3C)
/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare.*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x1
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
/* SYSTIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target2 to period mode.*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x1
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/* SYSTIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target2 period.*/
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET2_PERIOD_M ((SYSTIMER_TARGET2_PERIOD_V)<<(SYSTIMER_TARGET2_PERIOD_S))
#define SYSTIMER_TARGET2_PERIOD_V 0x3FFFFFF
#define SYSTIMER_TARGET2_PERIOD_S 0
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/* SYSTIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 20bits.*/
#define SYSTIMER_UNIT0_VALUE_HI 0x000FFFFF
#define SYSTIMER_UNIT0_VALUE_HI_M ((SYSTIMER_UNIT0_VALUE_HI_V)<<(SYSTIMER_UNIT0_VALUE_HI_S))
#define SYSTIMER_UNIT0_VALUE_HI_V 0xFFFFF
#define SYSTIMER_UNIT0_VALUE_HI_S 0
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/* SYSTIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bits.*/
#define SYSTIMER_UNIT0_VALUE_LO 0xFFFFFFFF
#define SYSTIMER_UNIT0_VALUE_LO_M ((SYSTIMER_UNIT0_VALUE_LO_V)<<(SYSTIMER_UNIT0_VALUE_LO_S))
#define SYSTIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
#define SYSTIMER_UNIT0_VALUE_LO_S 0
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/* SYSTIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 20bits.*/
#define SYSTIMER_UNIT1_VALUE_HI 0x000FFFFF
#define SYSTIMER_UNIT1_VALUE_HI_M ((SYSTIMER_UNIT1_VALUE_HI_V)<<(SYSTIMER_UNIT1_VALUE_HI_S))
#define SYSTIMER_UNIT1_VALUE_HI_V 0xFFFFF
#define SYSTIMER_UNIT1_VALUE_HI_S 0
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4C)
/* SYSTIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bits.*/
#define SYSTIMER_UNIT1_VALUE_LO 0xFFFFFFFF
#define SYSTIMER_UNIT1_VALUE_LO_M ((SYSTIMER_UNIT1_VALUE_LO_V)<<(SYSTIMER_UNIT1_VALUE_LO_S))
#define SYSTIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
#define SYSTIMER_UNIT1_VALUE_LO_S 0
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/* SYSTIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp0 sync enable signal.*/
#define SYSTIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_COMP0_LOAD_M (BIT(0))
#define SYSTIMER_COMP0_LOAD_V 0x1
#define SYSTIMER_COMP0_LOAD_S 0
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/* SYSTIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp1 sync enable signal.*/
#define SYSTIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_COMP1_LOAD_M (BIT(0))
#define SYSTIMER_COMP1_LOAD_V 0x1
#define SYSTIMER_COMP1_LOAD_S 0
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/* SYSTIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp2 sync enable signal.*/
#define SYSTIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_COMP2_LOAD_M (BIT(0))
#define SYSTIMER_COMP2_LOAD_V 0x1
#define SYSTIMER_COMP2_LOAD_S 0
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5C)
/* SYSTIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit0 sync enable signal.*/
#define SYSTIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_UNIT0_LOAD_M (BIT(0))
#define SYSTIMER_UNIT0_LOAD_V 0x1
#define SYSTIMER_UNIT0_LOAD_S 0
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/* SYSTIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit1 sync enable signal.*/
#define SYSTIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_UNIT1_LOAD_M (BIT(0))
#define SYSTIMER_UNIT1_LOAD_V 0x1
#define SYSTIMER_UNIT1_LOAD_S 0
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/* SYSTIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 enable.*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_V 0x1
#define SYSTIMER_TARGET2_INT_ENA_S 2
/* SYSTIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 enable.*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_V 0x1
#define SYSTIMER_TARGET1_INT_ENA_S 1
/* SYSTIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 enable.*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_V 0x1
#define SYSTIMER_TARGET0_INT_ENA_S 0
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 raw.*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_V 0x1
#define SYSTIMER_TARGET2_INT_RAW_S 2
/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 raw.*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_V 0x1
#define SYSTIMER_TARGET1_INT_RAW_S 1
/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 raw.*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_V 0x1
#define SYSTIMER_TARGET0_INT_RAW_S 0
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6C)
/* SYSTIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 clear.*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_V 0x1
#define SYSTIMER_TARGET2_INT_CLR_S 2
/* SYSTIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 clear.*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_V 0x1
#define SYSTIMER_TARGET1_INT_CLR_S 1
/* SYSTIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 clear.*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_V 0x1
#define SYSTIMER_TARGET0_INT_CLR_S 0
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/* SYSTIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 status.*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_V 0x1
#define SYSTIMER_TARGET2_INT_ST_S 2
/* SYSTIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 status.*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_V 0x1
#define SYSTIMER_TARGET1_INT_ST_S 1
/* SYSTIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 status.*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_V 0x1
#define SYSTIMER_TARGET0_INT_ST_S 0
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xFC)
/* SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */
/*description: systimer register version.*/
#define SYSTIMER_DATE 0xFFFFFFFF
#define SYSTIMER_DATE_M ((SYSTIMER_DATE_V)<<(SYSTIMER_DATE_S))
#define SYSTIMER_DATE_V 0xFFFFFFFF
#define SYSTIMER_DATE_S 0
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Configuration Register */
/** Type of conf register
* SYSTIMER_CONF.
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
* systimer clock force on
*/
uint32_t systimer_clk_fo: 1;
uint32_t reserved_1: 21;
/** target2_work_en : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
uint32_t target2_work_en: 1;
/** target1_work_en : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
uint32_t target1_work_en: 1;
/** target0_work_en : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
uint32_t target0_work_en: 1;
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
uint32_t timer_unit1_core1_stall_en: 1;
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
uint32_t timer_unit1_core0_stall_en: 1;
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
uint32_t timer_unit0_core1_stall_en: 1;
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
uint32_t timer_unit0_core0_stall_en: 1;
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
uint32_t timer_unit1_work_en: 1;
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
uint32_t timer_unit0_work_en: 1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
uint32_t clk_en: 1;
};
uint32_t val;
} systimer_conf_reg_t;
/** Type of unit_op register
* SYSTIMER_UNIT_OP.
*/
typedef union {
struct {
uint32_t reserved_0: 29;
/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* reg_timer_unit0_value_valid
*/
uint32_t timer_unit_value_valid: 1;
/** timer_unit_update : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
uint32_t timer_unit_update: 1;
uint32_t reserved_32: 1;
};
uint32_t val;
} systimer_unit_op_reg_t;
/** Type of unit_load register
* SYSTIMER_UNIT_LOAD
*/
typedef struct {
union {
struct {
/** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit load high 32 bit
*/
uint32_t timer_unit_load_hi: 20;
uint32_t reserved_20: 12;
};
uint32_t val;
} hi;
union {
struct {
/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit load low 32 bit
*/
uint32_t timer_unit_load_lo: 32;
};
uint32_t val;
} lo;
} systimer_unit_load_val_reg_t;
/** Type of target register
* SYSTIMER_TARGET.
*/
typedef struct {
union {
struct {
/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
* timer target high 32 bit
*/
uint32_t timer_target_hi: 20;
uint32_t reserved_20: 12;
};
uint32_t val;
} hi;
union {
struct {
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
* timer target low 32 bit
*/
uint32_t timer_target_lo: 32;
};
uint32_t val;
} lo;
} systimer_target_val_reg_t;
/** Type of target_conf register
* SYSTIMER_TARGET_CONF.
*/
typedef union {
struct {
/** target_period : R/W; bitpos: [25:0]; default: 0;
* target period
*/
uint32_t target_period: 26;
uint32_t reserved_26: 4;
/** target_period_mode : R/W; bitpos: [30]; default: 0;
* Set target to period mode
*/
uint32_t target_period_mode: 1;
/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target_timer_unit_sel: 1;
};
uint32_t val;
} systimer_target_conf_reg_t;
/** Type of unit_value_hi register
* SYSTIMER_UNIT_VALUE_HI.
*/
typedef struct {
union {
struct {
/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bit
*/
uint32_t timer_unit_value_hi: 20;
uint32_t reserved_20: 12;
};
uint32_t val;
} hi;
union {
struct {
/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bit
*/
uint32_t timer_unit_value_lo: 32;
};
uint32_t val;
} lo;
} systimer_unit_value_reg_t;
/** Type of comp_load register
* SYSTIMER_COMP_LOAD.
*/
typedef union {
struct {
/** timer_comp_load : WT; bitpos: [0]; default: 0;
* timer comp load value
*/
uint32_t timer_comp_load: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} systimer_comp_load_reg_t;
/** Type of unit_load register
* SYSTIMER_UNIT_LOAD.
*/
typedef union {
struct {
/** timer_unit_load : WT; bitpos: [0]; default: 0;
* timer unit load value
*/
uint32_t timer_unit_load: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} systimer_unit_load_reg_t;
/** Interrupt Register */
/** Type of int_ena register
* SYSTIMER_INT_ENA.
*/
typedef union {
struct {
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
uint32_t target0_int_ena: 1;
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
uint32_t target1_int_ena: 1;
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
uint32_t target2_int_ena: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
/** Type of int_raw register
* SYSTIMER_INT_RAW.
*/
typedef union {
struct {
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
uint32_t target0_int_raw: 1;
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
uint32_t target1_int_raw: 1;
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
uint32_t target2_int_raw: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
/** Type of int_clr register
* SYSTIMER_INT_CLR.
*/
typedef union {
struct {
/** target0_int_clr : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
uint32_t target0_int_clr: 1;
/** target1_int_clr : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
uint32_t target1_int_clr: 1;
/** target2_int_clr : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
uint32_t target2_int_clr: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;
/** Type of int_st register
* SYSTIMER_INT_ST.
*/
typedef union {
struct {
/** target0_int_st : RO; bitpos: [0]; default: 0;
* reg_target0_int_st
*/
uint32_t target0_int_st: 1;
/** target1_int_st : RO; bitpos: [1]; default: 0;
* reg_target1_int_st
*/
uint32_t target1_int_st: 1;
/** target2_int_st : RO; bitpos: [2]; default: 0;
* reg_target2_int_st
*/
uint32_t target2_int_st: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} systimer_int_st_reg_t;
/** Version Register */
/** Type of date register
* SYSTIMER_DATE.
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 33579377;
* reg_date
*/
uint32_t date: 32;
};
uint32_t val;
} systimer_date_reg_t;
typedef struct {
volatile systimer_conf_reg_t conf;
volatile systimer_unit_op_reg_t unit_op[2];
volatile systimer_unit_load_val_reg_t unit_load_val[2];
volatile systimer_target_val_reg_t target_val[3];
volatile systimer_target_conf_reg_t target_conf[3];
volatile systimer_unit_value_reg_t unit_val[2];
volatile systimer_comp_load_reg_t comp_load[3];
volatile systimer_unit_load_reg_t unit_load[2];
volatile systimer_int_ena_reg_t int_ena;
volatile systimer_int_raw_reg_t int_raw;
volatile systimer_int_clr_reg_t int_clr;
volatile systimer_int_st_reg_t int_st;
uint32_t reserved_074;
uint32_t reserved_078;
uint32_t reserved_07c;
uint32_t reserved_080;
uint32_t reserved_084;
uint32_t reserved_088;
uint32_t reserved_08c;
uint32_t reserved_090;
uint32_t reserved_094;
uint32_t reserved_098;
uint32_t reserved_09c;
uint32_t reserved_0a0;
uint32_t reserved_0a4;
uint32_t reserved_0a8;
uint32_t reserved_0ac;
uint32_t reserved_0b0;
uint32_t reserved_0b4;
uint32_t reserved_0b8;
uint32_t reserved_0bc;
uint32_t reserved_0c0;
uint32_t reserved_0c4;
uint32_t reserved_0c8;
uint32_t reserved_0cc;
uint32_t reserved_0d0;
uint32_t reserved_0d4;
uint32_t reserved_0d8;
uint32_t reserved_0dc;
uint32_t reserved_0e0;
uint32_t reserved_0e4;
uint32_t reserved_0e8;
uint32_t reserved_0ec;
uint32_t reserved_0f0;
uint32_t reserved_0f4;
uint32_t reserved_0f8;
volatile systimer_date_reg_t date;
} systimer_dev_t;
extern systimer_dev_t SYSTIMER;
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
/* Possible values for TIMG_WDT_STGx */
#define TIMG_WDT_STG_SEL_OFF 0
#define TIMG_WDT_STG_SEL_INT 1
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
#define TIMG_T0_USE_XTAL_V 0x00000001U
#define TIMG_T0_USE_XTAL_S 9
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
/** TIMG_T0HI_REG register
* Timer $x current value, high 22 bits
*/
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
/** TIMG_T0ALARMLO_REG register
* Timer $x alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
/** TIMG_T0ALARMHI_REG register
* Timer $x alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
/** TIMG_T0LOADLO_REG register
* Timer $x reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
/** TIMG_T0LOADHI_REG register
* Timer $x reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
#define TIMG_WDT_USE_XTAL_V 0x00000001U
#define TIMG_WDT_USE_XTAL_S 21
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 1
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 1
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 1
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 1
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: tx Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
/** tx_en : R/W; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer $x current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer $x alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer $x alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer $x reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer $x reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
uint32_t wdt_use_xtal:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Reserved
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Reserved
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** tx_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t tx_int_ena:1;
/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** tx_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t tx_int_raw:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** tx_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t tx_int_st:1;
/** wdt_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** tx_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t tx_int_clr:1;
/** wdt_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
uint32_t wdt_clk_is_active:1;
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
uint32_t timer_clk_is_active:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t config;
volatile timg_txlo_reg_t lo;
volatile timg_txhi_reg_t hi;
volatile timg_txupdate_reg_t update;
volatile timg_txalarmlo_reg_t alarmlo;
volatile timg_txalarmhi_reg_t alarmhi;
volatile timg_txloadlo_reg_t loadlo;
volatile timg_txloadhi_reg_t loadhi;
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct timg_dev_t {
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
#endif

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/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 19
#define U0TXD_GPIO_NUM 20
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)

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/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte : 32; /*UART $n accesses FIFO via this register.*/
};
uint32_t val;
} ahb_fifo;
union {
struct {
uint32_t rxfifo_full : 1; /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
uint32_t txfifo_empty : 1; /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
uint32_t parity_err : 1; /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
uint32_t frm_err : 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
uint32_t rxfifo_ovf : 1; /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
uint32_t dsr_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
uint32_t cts_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
uint32_t brk_det : 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
uint32_t rxfifo_tout : 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
uint32_t sw_xoff : 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
uint32_t glitch_det : 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
uint32_t tx_brk_done : 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.*/
uint32_t tx_brk_idle_done : 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.*/
uint32_t tx_done : 1; /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
uint32_t rs485_parity_err : 1; /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
uint32_t rs485_frm_err : 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
uint32_t rs485_clash : 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
uint32_t at_cmd_char_det : 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
uint32_t wakeup : 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full : 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
uint32_t txfifo_empty : 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
uint32_t parity_err : 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err : 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf : 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg : 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg : 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
uint32_t brk_det : 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
uint32_t rxfifo_tout : 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
uint32_t sw_xon : 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
uint32_t sw_xoff : 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det : 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done : 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done : 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint32_t tx_done : 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
uint32_t rs485_parity_err : 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
uint32_t rs485_frm_err : 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
uint32_t rs485_clash : 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
uint32_t at_cmd_char_det : 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t wakeup : 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full : 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t txfifo_empty : 1; /*This is the enable bit for txfifo_empty_int_st register.*/
uint32_t parity_err : 1; /*This is the enable bit for parity_err_int_st register.*/
uint32_t frm_err : 1; /*This is the enable bit for frm_err_int_st register.*/
uint32_t rxfifo_ovf : 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
uint32_t dsr_chg : 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg : 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det : 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout : 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon : 1; /*This is the enable bit for sw_xon_int_st register.*/
uint32_t sw_xoff : 1; /*This is the enable bit for sw_xoff_int_st register.*/
uint32_t glitch_det : 1; /*This is the enable bit for glitch_det_int_st register.*/
uint32_t tx_brk_done : 1; /*This is the enable bit for tx_brk_done_int_st register.*/
uint32_t tx_brk_idle_done : 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
uint32_t tx_done : 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash : 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det : 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
uint32_t wakeup : 1; /*This is the enable bit for uart_wakeup_int_st register.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full : 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
uint32_t txfifo_empty : 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err : 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err : 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
uint32_t rxfifo_ovf : 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg : 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg : 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det : 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
uint32_t rxfifo_tout : 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
uint32_t sw_xon : 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t sw_xoff : 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
uint32_t glitch_det : 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done : 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
uint32_t tx_brk_idle_done : 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done : 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err : 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err : 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
uint32_t rs485_clash : 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
uint32_t at_cmd_char_det : 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
uint32_t wakeup : 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int : 12; /*The integral part of the frequency divider factor.*/
uint32_t reserved12 : 8;
uint32_t div_frag : 4; /*The decimal part of the frequency divider factor.*/
uint32_t reserved24 : 8; /*Reserved*/
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t glitch_filt : 8; /*when input pulse width is lower than this value, the pulse is ignored.*/
uint32_t glitch_filt_en : 1; /*Set this bit to enable Rx signal filter.*/
uint32_t reserved9 : 23;
};
uint32_t val;
} rx_filt;
union {
struct {
uint32_t rxfifo_cnt : 10; /*Stores the byte number of valid data in Rx-FIFO.*/
uint32_t reserved10 : 3;
uint32_t dsrn : 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t ctsn : 1; /*This register represent the level value of the internal uart cts signal.*/
uint32_t rxd : 1; /*This register represent the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt : 10; /*Stores the byte number of data in Tx-FIFO.*/
uint32_t reserved26 : 3; /*Reserved*/
uint32_t dtrn : 1; /*This bit represents the level of the internal uart dtr signal.*/
uint32_t rtsn : 1; /*This bit represents the level of the internal uart rts signal.*/
uint32_t txd : 1; /*This bit represents the level of the internal uart txd signal.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity : 1; /*This register is used to configure the parity check mode.*/
uint32_t parity_en : 1; /*Set this bit to enable uart parity check.*/
uint32_t bit_num : 2; /*This register is used to set the length of data.*/
uint32_t stop_bit_num : 2; /*This register is used to set the length of stop bit.*/
uint32_t sw_rts : 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr : 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/
uint32_t txd_brk : 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/
uint32_t irda_dplx : 1; /*Set this bit to enable IrDA loopback mode.*/
uint32_t irda_tx_en : 1; /*This is the start enable bit for IrDA transmitter.*/
uint32_t irda_wctl : 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
uint32_t irda_tx_inv : 1; /*Set this bit to invert the level of IrDA transmitter.*/
uint32_t irda_rx_inv : 1; /*Set this bit to invert the level of IrDA receiver.*/
uint32_t loopback : 1; /*Set this bit to enable uart loopback test mode.*/
uint32_t tx_flow_en : 1; /*Set this bit to enable flow control function for transmitter.*/
uint32_t irda_en : 1; /*Set this bit to enable IrDA protocol.*/
uint32_t rxfifo_rst : 1; /*Set this bit to reset the uart receive-FIFO.*/
uint32_t txfifo_rst : 1; /*Set this bit to reset the uart transmit-FIFO.*/
uint32_t rxd_inv : 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv : 1; /*Set this bit to inverse the level value of uart cts signal.*/
uint32_t dsr_inv : 1; /*Set this bit to inverse the level value of uart dsr signal.*/
uint32_t txd_inv : 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv : 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv : 1; /*Set this bit to inverse the level value of uart dtr signal.*/
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
uint32_t err_wr_mask : 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/
uint32_t autobaud_en : 1; /*This is the enable bit for detecting baudrate.*/
uint32_t mem_clk_en : 1; /*UART memory clock gate enable signal.*/
uint32_t reserved29 : 3;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd : 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
uint32_t txfifo_empty_thrhd : 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
uint32_t dis_rx_dat_ovf : 1; /*Disable UART Rx data overflow detect. */
uint32_t rx_tout_flow_dis : 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/
uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/
uint32_t reserved22 : 10;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt : 12; /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt : 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt : 10; /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en : 1; /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
uint32_t xonoff_del : 1; /*Set this bit to remove flow control char from the received data.*/
uint32_t force_xon : 1; /*Set this bit to enable the transmitter to go on sending data.*/
uint32_t force_xoff : 1; /*Set this bit to stop the transmitter from sending data.*/
uint32_t send_xon : 1; /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
uint32_t send_xoff : 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
uint32_t reserved6 : 26; /*Reserved*/
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold : 10; /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xoff_threshold : 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/
uint32_t xoff_char : 8; /*This register stores the Xoff flow control char.*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} swfc_conf0;
union {
struct {
uint32_t xon_threshold : 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/
uint32_t xon_char : 8; /*This register stores the Xon flow control char.*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} swfc_conf1;
union {
struct {
uint32_t tx_brk_num : 8; /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} txbrk_conf;
union {
struct {
uint32_t rx_idle_thrhd : 10; /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
uint32_t tx_idle_num : 10; /*This register is used to configure the duration time between transfers.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en : 1; /*Set this bit to choose the rs485 mode.*/
uint32_t dl0_en : 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en : 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en : 1; /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. */
uint32_t rx_busy_tx_en : 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
uint32_t rx_dly_num : 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num : 4; /*This register is used to delay the transmitter's internal data signal.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num : 16; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num : 16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout : 16; /*This register is used to configure the duration time between the at_cmd chars.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data : 8; /*This register is used to configure the content of at_cmd char.*/
uint32_t char_num : 8; /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t reserved0 : 1;
uint32_t rx_size : 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
uint32_t tx_size : 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
uint32_t rx_flow_thrhd : 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/
uint32_t rx_tout_thrhd : 10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
uint32_t force_pd : 1; /*Set this bit to force power down UART memory.*/
uint32_t force_pu : 1; /*Set this bit to force power up UART memory.*/
uint32_t reserved28 : 4;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t apb_tx_waddr : 10; /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
uint32_t reserved10 : 1; /*Reserved*/
uint32_t tx_raddr : 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t apb_rx_raddr : 10; /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
uint32_t reserved10 : 1; /*Reserved*/
uint32_t rx_waddr : 10; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t st_urx_out : 4; /*This is the status register of receiver.*/
uint32_t st_utx_out : 4; /*This is the status register of transmitter.*/
uint32_t reserved8 : 24; /*Reserved*/
};
uint32_t val;
} fsm_status;
union {
struct {
uint32_t min_cnt : 12; /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt : 12; /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} negpulse;
union {
struct {
uint32_t sclk_div_b : 6; /*The denominator of the frequency divider factor.*/
uint32_t sclk_div_a : 6; /*The numerator of the frequency divider factor.*/
uint32_t sclk_div_num : 8; /*The integral part of the frequency divider factor.*/
uint32_t sclk_sel : 2; /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/
uint32_t sclk_en : 1; /*Set this bit to enable UART Tx/Rx clock.*/
uint32_t rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/
uint32_t tx_sclk_en : 1; /*Set this bit to enable UART Tx clock.*/
uint32_t rx_sclk_en : 1; /*Set this bit to enable UART Rx clock.*/
uint32_t tx_rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Tx.*/
uint32_t rx_rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Rx.*/
uint32_t reserved28 : 4;
};
uint32_t val;
} clk_conf;
uint32_t date;
union {
struct {
uint32_t id : 30; /*This register is used to configure the uart_id.*/
uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
uint32_t update : 1; /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
};
uint32_t val;
} id;
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_UART_STRUCT_H_ */

12
components/soc/esp8684/include/soc/wdev_reg.h Normal file
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@ -0,0 +1,12 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
/* Hardware random number generator register */
#define WDEV_RND_REG 0x600260b0

53
components/soc/esp8684/interrupts.c Normal file
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@ -0,0 +1,53 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
const char *const esp_isr_names[] = {
[0] = "WIFI_MAC",
[1] = "WIFI_MAC_NMI",
[2] = "WIFI_PWR",
[3] = "WIFI_BB",
[4] = "BT_MAC",
[5] = "BT_BB",
[6] = "BT_BB_NMI",
[7] = "LP_TIMER",
[8] = "COEX",
[9] = "BLE_TIMER",
[10] = "BLE_SEC",
[11] = "I2C_MST",
[12] = "APB_CTRL",
[13] = "GPIO_INTR_PRO",
[14] = "GPIO_INTR_PRO_NMI",
[15] = "SPI_INTR_1",
[16] = "SPI_INTR_2",
[17] = "UART",
[18] = "UART1",
[19] = "LEDC",
[20] = "EFUSE",
[21] = "RTC_CORE",
[22] = "I2C_EXT0",
[23] = "TG0_T0_LEVEL",
[24] = "TG0_WDT_LEVEL",
[25] = "CACHE_IA",
[26] = "SYSTIMER_TARGET0_EDGE",
[27] = "SYSTIMER_TARGET1_EDGE",
[28] = "SYSTIMER_TARGET2_EDGE",
[29] = "SPI_MEM_REJECT_CACHE",
[30] = "ICACHE_PRELOAD0",
[31] = "ICACHE_SYNC0",
[32] = "APB_ADC",
[33] = "DMA_CH0",
[34] = "SHA",
[35] = "ECC",
[36] = "ETS_FROM_CPU_INTR0",
[37] = "ETS_FROM_CPU_INTR1",
[38] = "ETS_FROM_CPU_INTR2",
[39] = "ETS_FROM_CPU_INTR3",
[40] = "ETS_ASSIST_DEBUG",
[41] = "ETS_CORE0_PIF_PMS_SIZE",
[42] = "ETS_CACHE_CORE0_ACS",
};

28
components/soc/esp8684/ld/esp8684.peripherals.ld Normal file
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@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( UART1 = 0x60010000 );
PROVIDE ( SPIMEM1 = 0x60002000 );
PROVIDE ( SPIMEM0 = 0x60003000 );
PROVIDE ( GPIO = 0x60004000 );
PROVIDE ( SIGMADELTA = 0x60004f00 );
PROVIDE ( RTCCNTL = 0x60008000 );
PROVIDE ( RTCIO = 0x60008400 );
PROVIDE ( HINF = 0x6000B000 );
PROVIDE ( I2C0 = 0x60013000 );
PROVIDE ( HOST = 0x60015000 );
PROVIDE ( RMT = 0x60016000 );
PROVIDE ( RMTMEM = 0x60016400 );
PROVIDE ( PCNT = 0x60017000 );
PROVIDE ( SLC = 0x60018000 );
PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( GPSPI2 = 0x60024000 );
PROVIDE ( GPSPI3 = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( GDMA = 0x6003F000 );

17
components/soc/esp8684/ledc_periph.c Normal file
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@ -0,0 +1,17 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ledc_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every LEDC peripheral: GPIO signals
*/
const ledc_signal_conn_t ledc_periph_signal[1] = {
{
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
}
};

35
components/soc/esp8684/rmt_periph.c Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rmt_periph.h"
#include "soc/gpio_sig_map.h"
const rmt_signal_conn_t rmt_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_RMT_MODULE,
.irq = ETS_RMT_INTR_SOURCE,
.channels = {
[0] = {
.tx_sig = RMT_SIG_OUT0_IDX,
.rx_sig = -1
},
[1] = {
.tx_sig = RMT_SIG_OUT1_IDX,
.rx_sig = -1
},
[2] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_IN0_IDX
},
[3] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_IN1_IDX
},
}
}
}
};

63
components/soc/esp8684/spi_periph.c Normal file
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@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/spi_periph.h"
#include "stddef.h"
/*
Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{
.spiclk_out = SPICLK_OUT_MUX_IDX,
.spiclk_in = 0,/* SPI clock is not an input signal*/
.spid_out = SPID_OUT_IDX,
.spiq_out = SPIQ_OUT_IDX,
.spiwp_out = SPIWP_OUT_IDX,
.spihd_out = SPIHD_OUT_IDX,
.spid_in = SPID_IN_IDX,
.spiq_in = SPIQ_IN_IDX,
.spiwp_in = SPIWP_IN_IDX,
.spihd_in = SPIHD_IN_IDX,
.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
.spics_in = 0,/* SPI cs is not an input signal*/
.spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI1_INTR_SOURCE,
.irq_dma = -1,
.module = PERIPH_SPI_MODULE,
.hw = (spi_dev_t *) &SPIMEM1,
.func = SPI_FUNC_NUM,
}, {
.spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX,
.spid_out = FSPID_OUT_IDX,
.spiq_out = FSPIQ_OUT_IDX,
.spiwp_out = FSPIWP_OUT_IDX,
.spihd_out = FSPIHD_OUT_IDX,
.spid_in = FSPID_IN_IDX,
.spiq_in = FSPIQ_IN_IDX,
.spiwp_in = FSPIWP_IN_IDX,
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
.irq = ETS_SPI2_INTR_SOURCE,
.irq_dma = -1,
.module = PERIPH_SPI2_MODULE,
.hw = &GPSPI2,
.func = SPI2_FUNC_NUM,
}
};

18
components/soc/esp8684/timer_periph.c Normal file
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@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/timer_periph.h"
const timer_group_signal_conn_t timer_group_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_TIMG0_MODULE,
.timer_irq_id = {
[0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
}
},
}
};

80
components/soc/esp8684/uart_periph.c Normal file
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@ -0,0 +1,80 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
.irq = ETS_UART0_INTR_SOURCE,
.module = PERIPH_UART0_MODULE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
.module = PERIPH_UART1_MODULE,
},
};

20
components/soc/include/soc/lldesc.h
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@ -1,16 +1,8 @@
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
@ -26,6 +18,8 @@
#include "esp32c3/rom/lldesc.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/lldesc.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/lldesc.h"
#endif
//the size field has 12 bits, but 0 not for 4096.

32
components/soc/include/soc/soc_memory_types.h
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@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdlib.h>
@ -54,7 +46,10 @@ inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
|| (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
#endif
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
#if SOC_RTC_FAST_MEM_SUPPORTED
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH)
#endif
;
}
inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
@ -81,7 +76,11 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
bool r;
r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
#if SOC_RTC_SLOW_MEM_SUPPORTED
r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
#endif
#if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
* for single core configuration (where it gets added to system heap) following
@ -124,6 +123,7 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
}
#if SOC_RTC_FAST_MEM_SUPPORTED
inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) {
return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH);
}
@ -131,10 +131,14 @@ inline static bool IRAM_ATTR esp_ptr_in_rtc_iram_fast(const void *p) {
inline static bool IRAM_ATTR esp_ptr_in_rtc_dram_fast(const void *p) {
return ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
}
#endif
#if !CONFIG_IDF_TARGET_ESP8684
// IDF-3901
inline static bool IRAM_ATTR esp_ptr_in_rtc_slow(const void *p) {
return ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
}
#endif
/* Convert a D/IRAM DRAM pointer to equivalent word address in IRAM