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timer_group: update reg headers for c3&s2&h2 and fix direct 8/16bit reg access

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This commit is contained in:
SalimTerryLi 2021-08-11 20:49:49 +08:00
parent 9b3b89017f
commit 443845fd54
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GPG Key ID: F05CCEF2191AF770
12 changed files with 4018 additions and 2193 deletions
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69
components/hal/esp32c3/include/hal/mwdt_ll.h
View File

@ -42,6 +42,13 @@ _Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add
_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
#define FORCE_MODIFY_WHOLE_REG(i, j, k) \
{ \
typeof(i) temp_reg = (i); \
temp_reg.j = (k); \
(i) = temp_reg; \
}
/**
* @brief Enable the MWDT
*
@ -49,7 +56,7 @@ _Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add
*/
FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
{
hw->wdt_config0.en = 1;
hw->wdtconfig0.wdt_en = 1;
}
/**
@ -62,7 +69,7 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdt_config0.en = 0;
hw->wdtconfig0.wdt_en = 0;
}
/**
@ -73,7 +80,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdt_config0.en) ? true : false;
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
@ -88,26 +95,26 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u
{
switch (stage) {
case WDT_STAGE0:
hw->wdt_config0.stg0 = behavior;
hw->wdt_config2 = timeout;
hw->wdtconfig0.wdt_stg0 = behavior;
hw->wdtconfig2.wdt_stg0_hold = timeout;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = behavior;
hw->wdt_config3 = timeout;
hw->wdtconfig0.wdt_stg1 = behavior;
hw->wdtconfig3.wdt_stg1_hold = timeout;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = behavior;
hw->wdt_config4 = timeout;
hw->wdtconfig0.wdt_stg2 = behavior;
hw->wdtconfig4.wdt_stg2_hold = timeout;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = behavior;
hw->wdt_config5 = timeout;
hw->wdtconfig0.wdt_stg3 = behavior;
hw->wdtconfig5.wdt_stg3_hold = timeout;
break;
default:
break;
}
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -120,22 +127,22 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
break;
}
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -146,9 +153,9 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->wdt_config0.cpu_reset_length = length;
hw->wdtconfig0.wdt_cpu_reset_length = length;
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -159,9 +166,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->wdt_config0.sys_reset_length = length;
hw->wdtconfig0.wdt_sys_reset_length = length;
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -176,9 +183,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0;
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -189,9 +196,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
hw->wdt_config1.clk_prescale = prescaler;
// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// We take care of the "read-modify-write" procedure by ourselves.
FORCE_MODIFY_WHOLE_REG(hw->wdtconfig1, wdt_clk_prescale, prescaler);
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -203,7 +212,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
*/
FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
{
hw->wdt_feed = 1;
hw->wdtfeed.wdt_feed = 1;
}
/**
@ -215,7 +224,7 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
{
hw->wdt_wprotect = 0;
hw->wdtwprotect.wdt_wkey = 0;
}
/**
@ -225,7 +234,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
hw->wdt_wprotect = TIMG_WDT_WKEY_VALUE;
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
@ -235,7 +244,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
hw->int_clr.wdt = 1;
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
@ -246,7 +255,7 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
{
hw->int_ena.wdt = (enable) ? 1 : 0;
hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
}
#ifdef __cplusplus

62
components/hal/esp32c3/include/hal/timer_ll.h
View File

@ -52,11 +52,11 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
if (divider >= 65536) {
divider = 0;
}
int timer_en = hw->hw_timer[timer_num].config.enable;
hw->hw_timer[timer_num].config.enable = 0;
hw->hw_timer[timer_num].config.divcnt_rst = 1;
hw->hw_timer[timer_num].config.divider = divider;
hw->hw_timer[timer_num].config.enable = timer_en;
int timer_en = hw->hw_timer[timer_num].config.tx_en;
hw->hw_timer[timer_num].config.tx_en = 0;
hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
hw->hw_timer[timer_num].config.tx_divider = divider;
hw->hw_timer[timer_num].config.tx_en = timer_en;
}
/**
@ -70,7 +70,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
*/
static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
{
uint32_t d = hw->hw_timer[timer_num].config.divider;
uint32_t d = hw->hw_timer[timer_num].config.tx_divider;
if (d == 0) {
d = 65536;
} else if (d == 1) {
@ -90,9 +90,9 @@ static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, u
*/
static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val)
{
hw->hw_timer[timer_num].load_high.load_hi = (uint32_t) (load_val >> 32);
hw->hw_timer[timer_num].load_low = (uint32_t) load_val;
hw->hw_timer[timer_num].reload = 1;
hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32);
hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val;
hw->hw_timer[timer_num].load.tx_load = 1;
}
/**
@ -106,9 +106,9 @@ static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_
*/
FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val)
{
hw->hw_timer[timer_num].update.update = 1;
while (hw->hw_timer[timer_num].update.update) {}
*timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high.hi << 32) | (hw->hw_timer[timer_num].cnt_low);
hw->hw_timer[timer_num].update.tx_update = 1;
while (hw->hw_timer[timer_num].update.tx_update) {}
*timer_val = ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
}
/**
@ -122,7 +122,7 @@ FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t ti
*/
static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en)
{
hw->hw_timer[timer_num].config.increase = increase_en;
hw->hw_timer[timer_num].config.tx_increase = increase_en;
}
/**
@ -137,7 +137,7 @@ static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.increase;
return hw->hw_timer[timer_num].config.tx_increase;
}
/**
@ -151,7 +151,7 @@ static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t tim
*/
FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en)
{
hw->hw_timer[timer_num].config.enable = counter_en;
hw->hw_timer[timer_num].config.tx_en = counter_en;
}
/**
@ -166,7 +166,7 @@ FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t t
*/
static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.enable;
return hw->hw_timer[timer_num].config.tx_en;
}
/**
@ -180,7 +180,7 @@ static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer
*/
static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en)
{
hw->hw_timer[timer_num].config.autoreload = auto_reload_en;
hw->hw_timer[timer_num].config.tx_autoreload = auto_reload_en;
}
/**
@ -195,7 +195,7 @@ static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.autoreload;
return hw->hw_timer[timer_num].config.tx_autoreload;
}
/**
@ -209,8 +209,8 @@ FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t time
*/
FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value)
{
hw->hw_timer[timer_num].alarm_high.alarm_hi = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value;
hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value;
}
/**
@ -224,7 +224,7 @@ FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t time
*/
static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value)
{
*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high.alarm_hi << 32) | (hw->hw_timer[timer_num].alarm_low);
*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarmhi.tx_alarm_hi << 32) | (hw->hw_timer[timer_num].alarmlo.tx_alarm_lo);
}
/**
@ -238,7 +238,7 @@ static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en)
{
hw->hw_timer[timer_num].config.alarm_en = alarm_en;
hw->hw_timer[timer_num].config.tx_alarm_en = alarm_en;
}
/**
@ -253,7 +253,7 @@ FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.alarm_en;
return hw->hw_timer[timer_num].config.tx_alarm_en;
}
/**
@ -266,7 +266,7 @@ static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_n
*/
FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_ena.val |= BIT(timer_num);
hw->int_ena_timers.val |= BIT(timer_num);
}
/**
@ -279,7 +279,7 @@ FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_ena.val &= (~BIT(timer_num));
hw->int_ena_timers.val &= (~BIT(timer_num));
}
/**
@ -292,7 +292,7 @@ FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_n
*/
FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_clr.val |= BIT(timer_num);
hw->int_clr_timers.val |= BIT(timer_num);
}
/**
@ -305,7 +305,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
*/
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
{
*intr_status = hw->int_st.val & 0x01;
*intr_status = hw->int_st_timers.val & 0x01;
}
/**
@ -319,7 +319,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
{
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
*intr_raw_status = hw->int_raw.val & 0x01;
*intr_raw_status = hw->int_raw_timers.val & 0x01;
}
/**
@ -391,7 +391,7 @@ static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t time
*/
static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw)
{
return (uint32_t) & (hw->int_st.val);
return (uint32_t) & (hw->int_st_timers.val);
}
static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num)
@ -409,7 +409,7 @@ static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t ti
*/
static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num, bool use_xtal_en)
{
hw->hw_timer[timer_num].config.use_xtal = use_xtal_en;
hw->hw_timer[timer_num].config.tx_use_xtal = use_xtal_en;
}
/**
@ -423,7 +423,7 @@ static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num,
*/
static inline bool timer_ll_get_use_xtal(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.use_xtal;
return hw->hw_timer[timer_num].config.tx_use_xtal;
}
#ifdef __cplusplus

69
components/hal/esp32h2/include/hal/mwdt_ll.h
View File

@ -42,6 +42,13 @@ _Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add
_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
#define FORCE_MODIFY_WHOLE_REG(i, j, k) \
{ \
typeof(i) temp_reg = (i); \
temp_reg.j = (k); \
(i) = temp_reg; \
}
/**
* @brief Enable the MWDT
*
@ -49,7 +56,7 @@ _Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add
*/
FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
{
hw->wdt_config0.en = 1;
hw->wdtconfig0.wdt_en = 1;
}
/**
@ -62,7 +69,7 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdt_config0.en = 0;
hw->wdtconfig0.wdt_en = 0;
}
/**
@ -73,7 +80,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdt_config0.en) ? true : false;
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
@ -88,26 +95,26 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u
{
switch (stage) {
case WDT_STAGE0:
hw->wdt_config0.stg0 = behavior;
hw->wdt_config2 = timeout;
hw->wdtconfig0.wdt_stg0 = behavior;
hw->wdtconfig2.wdt_stg0_hold = timeout;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = behavior;
hw->wdt_config3 = timeout;
hw->wdtconfig0.wdt_stg1 = behavior;
hw->wdtconfig3.wdt_stg1_hold = timeout;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = behavior;
hw->wdt_config4 = timeout;
hw->wdtconfig0.wdt_stg2 = behavior;
hw->wdtconfig4.wdt_stg2_hold = timeout;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = behavior;
hw->wdt_config5 = timeout;
hw->wdtconfig0.wdt_stg3 = behavior;
hw->wdtconfig5.wdt_stg3_hold = timeout;
break;
default:
break;
}
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -120,22 +127,22 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
break;
}
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -146,9 +153,9 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->wdt_config0.cpu_reset_length = length;
hw->wdtconfig0.wdt_cpu_reset_length = length;
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -159,9 +166,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->wdt_config0.sys_reset_length = length;
hw->wdtconfig0.wdt_sys_reset_length = length;
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -176,9 +183,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0;
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -189,9 +196,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
hw->wdt_config1.clk_prescale = prescaler;
// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// We take care of the "read-modify-write" procedure by ourselves.
FORCE_MODIFY_WHOLE_REG(hw->wdtconfig1, wdt_clk_prescale, prescaler);
//Config registers are updated asynchronously
hw->wdt_config0.conf_update_en = 1;
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@ -203,7 +212,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
*/
FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
{
hw->wdt_feed = 1;
hw->wdtfeed.wdt_feed = 1;
}
/**
@ -215,7 +224,7 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
{
hw->wdt_wprotect = 0;
hw->wdtwprotect.wdt_wkey = 0;
}
/**
@ -225,7 +234,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
hw->wdt_wprotect = TIMG_WDT_WKEY_VALUE;
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
@ -235,7 +244,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
hw->int_clr.wdt = 1;
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
@ -246,7 +255,7 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
{
hw->int_ena.wdt = (enable) ? 1 : 0;
hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
}
#ifdef __cplusplus

62
components/hal/esp32h2/include/hal/timer_ll.h
View File

@ -52,11 +52,11 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
if (divider >= 65536) {
divider = 0;
}
int timer_en = hw->hw_timer[timer_num].config.enable;
hw->hw_timer[timer_num].config.enable = 0;
hw->hw_timer[timer_num].config.divcnt_rst = 1;
hw->hw_timer[timer_num].config.divider = divider;
hw->hw_timer[timer_num].config.enable = timer_en;
int timer_en = hw->hw_timer[timer_num].config.tx_en;
hw->hw_timer[timer_num].config.tx_en = 0;
hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
hw->hw_timer[timer_num].config.tx_divider = divider;
hw->hw_timer[timer_num].config.tx_en = timer_en;
}
/**
@ -70,7 +70,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
*/
static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
{
uint32_t d = hw->hw_timer[timer_num].config.divider;
uint32_t d = hw->hw_timer[timer_num].config.tx_divider;
if (d == 0) {
d = 65536;
} else if (d == 1) {
@ -90,9 +90,9 @@ static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, u
*/
static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val)
{
hw->hw_timer[timer_num].load_high.load_hi = (uint32_t) (load_val >> 32);
hw->hw_timer[timer_num].load_low = (uint32_t) load_val;
hw->hw_timer[timer_num].reload = 1;
hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32);
hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val;
hw->hw_timer[timer_num].load.tx_load = 1;
}
/**
@ -106,9 +106,9 @@ static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_
*/
FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val)
{
hw->hw_timer[timer_num].update.update = 1;
while (hw->hw_timer[timer_num].update.update) {}
*timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high.hi << 32) | (hw->hw_timer[timer_num].cnt_low);
hw->hw_timer[timer_num].update.tx_update = 1;
while (hw->hw_timer[timer_num].update.tx_update) {}
*timer_val = ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
}
/**
@ -122,7 +122,7 @@ FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t ti
*/
static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en)
{
hw->hw_timer[timer_num].config.increase = increase_en;
hw->hw_timer[timer_num].config.tx_increase = increase_en;
}
/**
@ -137,7 +137,7 @@ static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.increase;
return hw->hw_timer[timer_num].config.tx_increase;
}
/**
@ -151,7 +151,7 @@ static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t tim
*/
FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en)
{
hw->hw_timer[timer_num].config.enable = counter_en;
hw->hw_timer[timer_num].config.tx_en = counter_en;
}
/**
@ -166,7 +166,7 @@ FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t t
*/
static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.enable;
return hw->hw_timer[timer_num].config.tx_en;
}
/**
@ -180,7 +180,7 @@ static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer
*/
static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en)
{
hw->hw_timer[timer_num].config.autoreload = auto_reload_en;
hw->hw_timer[timer_num].config.tx_autoreload = auto_reload_en;
}
/**
@ -195,7 +195,7 @@ static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.autoreload;
return hw->hw_timer[timer_num].config.tx_autoreload;
}
/**
@ -209,8 +209,8 @@ FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t time
*/
FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value)
{
hw->hw_timer[timer_num].alarm_high.alarm_hi = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value;
hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value;
}
/**
@ -224,7 +224,7 @@ FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t time
*/
static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value)
{
*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high.alarm_hi << 32) | (hw->hw_timer[timer_num].alarm_low);
*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarmhi.tx_alarm_hi << 32) | (hw->hw_timer[timer_num].alarmlo.tx_alarm_lo);
}
/**
@ -238,7 +238,7 @@ static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en)
{
hw->hw_timer[timer_num].config.alarm_en = alarm_en;
hw->hw_timer[timer_num].config.tx_alarm_en = alarm_en;
}
/**
@ -253,7 +253,7 @@ FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.alarm_en;
return hw->hw_timer[timer_num].config.tx_alarm_en;
}
/**
@ -266,7 +266,7 @@ static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_n
*/
FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_ena.val |= BIT(timer_num);
hw->int_ena_timers.val |= BIT(timer_num);
}
/**
@ -279,7 +279,7 @@ FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_ena.val &= (~BIT(timer_num));
hw->int_ena_timers.val &= (~BIT(timer_num));
}
/**
@ -292,7 +292,7 @@ FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_n
*/
FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_clr.val |= BIT(timer_num);
hw->int_clr_timers.val |= BIT(timer_num);
}
/**
@ -305,7 +305,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
*/
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
{
*intr_status = hw->int_st.val & 0x01;
*intr_status = hw->int_st_timers.val & 0x01;
}
/**
@ -319,7 +319,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
{
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
*intr_raw_status = hw->int_raw.val & 0x01;
*intr_raw_status = hw->int_raw_timers.val & 0x01;
}
/**
@ -391,7 +391,7 @@ static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t time
*/
static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw)
{
return (uint32_t) & (hw->int_st.val);
return (uint32_t) & (hw->int_st_timers.val);
}
static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num)
@ -409,7 +409,7 @@ static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t ti
*/
static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num, bool use_xtal_en)
{
hw->hw_timer[timer_num].config.use_xtal = use_xtal_en;
hw->hw_timer[timer_num].config.tx_use_xtal = use_xtal_en;
}
/**
@ -423,7 +423,7 @@ static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num,
*/
static inline bool timer_ll_get_use_xtal(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.use_xtal;
return hw->hw_timer[timer_num].config.tx_use_xtal;
}
#ifdef __cplusplus

61
components/hal/esp32s2/include/hal/mwdt_ll.h
View File

@ -42,6 +42,13 @@ _Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add
_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
#define FORCE_MODIFY_WHOLE_REG(i, j, k) \
{ \
typeof(i) temp_reg = (i); \
temp_reg.j = (k); \
(i) = temp_reg; \
}
/**
* @brief Enable the MWDT
*
@ -49,7 +56,7 @@ _Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add
*/
FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
{
hw->wdt_config0.en = 1;
hw->wdtconfig0.wdt_en = 1;
}
/**
@ -62,7 +69,7 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
hw->wdt_config0.en = 0;
hw->wdtconfig0.wdt_en = 0;
}
/**
@ -73,7 +80,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
return (hw->wdt_config0.en) ? true : false;
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
@ -88,20 +95,20 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u
{
switch (stage) {
case WDT_STAGE0:
hw->wdt_config0.stg0 = behavior;
hw->wdt_config2 = timeout;
hw->wdtconfig0.wdt_stg0 = behavior;
hw->wdtconfig2.wdt_stg0_hold = timeout;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = behavior;
hw->wdt_config3 = timeout;
hw->wdtconfig0.wdt_stg1 = behavior;
hw->wdtconfig3.wdt_stg1_hold = timeout;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = behavior;
hw->wdt_config4 = timeout;
hw->wdtconfig0.wdt_stg2 = behavior;
hw->wdtconfig4.wdt_stg2_hold = timeout;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = behavior;
hw->wdt_config5 = timeout;
hw->wdtconfig0.wdt_stg3 = behavior;
hw->wdtconfig5.wdt_stg3_hold = timeout;
break;
default:
break;
@ -118,16 +125,16 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
switch (stage) {
case WDT_STAGE0:
hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF;
hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
break;
@ -142,7 +149,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_edge_intr(timg_dev_t *hw, bool enable)
{
hw->wdt_config0.edge_int_en = (enable) ? 1 : 0;
hw->wdtconfig0.wdt_edge_int_en = (enable) ? 1 : 0;
}
/**
@ -153,7 +160,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_edge_intr(timg_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_level_intr(timg_dev_t *hw, bool enable)
{
hw->wdt_config0.level_int_en = (enable) ? 1 : 0;
hw->wdtconfig0.wdt_level_int_en = (enable) ? 1 : 0;
}
/**
@ -164,7 +171,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_level_intr(timg_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->wdt_config0.cpu_reset_length = length;
hw->wdtconfig0.wdt_cpu_reset_length = length;
}
/**
@ -175,7 +182,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
hw->wdt_config0.sys_reset_length = length;
hw->wdtconfig0.wdt_sys_reset_length = length;
}
/**
@ -190,7 +197,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
{
hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0;
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
/**
@ -201,7 +208,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
hw->wdt_config1.clk_prescale = prescaler;
// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// We take care of the "read-modify-write" procedure by ourselves.
FORCE_MODIFY_WHOLE_REG(hw->wdtconfig1, wdt_clk_prescaler, prescaler);
}
/**
@ -213,7 +222,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
*/
FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
{
hw->wdt_feed = 1;
hw->wdtfeed.wdt_feed = 1;
}
/**
@ -225,7 +234,7 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
{
hw->wdt_wprotect = 0;
hw->wdtwprotect.wdt_wkey = 0;
}
/**
@ -235,7 +244,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
hw->wdt_wprotect = TIMG_WDT_WKEY_VALUE;
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
@ -245,7 +254,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t* hw)
{
hw->int_clr.wdt = 1;
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
@ -256,7 +265,7 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t* hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t* hw, bool enable)
{
hw->int_ena.wdt = (enable) ? 1 : 0;
hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
}
#ifdef __cplusplus

72
components/hal/esp32s2/include/hal/timer_ll.h
View File

@ -48,10 +48,10 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
if (divider >= 65536) {
divider = 0;
}
int timer_en = hw->hw_timer[timer_num].config.enable;
hw->hw_timer[timer_num].config.enable = 0;
hw->hw_timer[timer_num].config.divider = divider;
hw->hw_timer[timer_num].config.enable = timer_en;
int timer_en = hw->hw_timer[timer_num].config.tx_en;
hw->hw_timer[timer_num].config.tx_en = 0;
hw->hw_timer[timer_num].config.tx_divider = divider;
hw->hw_timer[timer_num].config.tx_en = timer_en;
}
/**
@ -65,7 +65,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
*/
static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
{
uint32_t d = hw->hw_timer[timer_num].config.divider;
uint32_t d = hw->hw_timer[timer_num].config.tx_divider;
if (d == 0) {
d = 65536;
} else if (d == 1) {
@ -85,9 +85,9 @@ static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, u
*/
static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val)
{
hw->hw_timer[timer_num].load_high = (uint32_t) (load_val >> 32);
hw->hw_timer[timer_num].load_low = (uint32_t) load_val;
hw->hw_timer[timer_num].reload = 1;
hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32);
hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val;
hw->hw_timer[timer_num].load.tx_load = 1;
}
/**
@ -101,9 +101,9 @@ static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_
*/
FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val)
{
hw->hw_timer[timer_num].update.update = 1;
while (hw->hw_timer[timer_num].update.update) {}
*timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high << 32) | (hw->hw_timer[timer_num].cnt_low);
hw->hw_timer[timer_num].update.tx_update = 1;
while (hw->hw_timer[timer_num].update.tx_update) {}
*timer_val = ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
}
/**
@ -117,7 +117,7 @@ FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t ti
*/
static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en)
{
hw->hw_timer[timer_num].config.increase = increase_en;
hw->hw_timer[timer_num].config.tx_increase = increase_en;
}
/**
@ -132,7 +132,7 @@ static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.increase;
return hw->hw_timer[timer_num].config.tx_increase;
}
/**
@ -146,7 +146,7 @@ static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t tim
*/
FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en)
{
hw->hw_timer[timer_num].config.enable = counter_en;
hw->hw_timer[timer_num].config.tx_en = counter_en;
}
/**
@ -161,7 +161,7 @@ FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t t
*/
static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.enable;
return hw->hw_timer[timer_num].config.tx_en;
}
/**
@ -175,7 +175,7 @@ static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer
*/
static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en)
{
hw->hw_timer[timer_num].config.autoreload = auto_reload_en;
hw->hw_timer[timer_num].config.tx_autoreload = auto_reload_en;
}
/**
@ -190,7 +190,7 @@ static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.autoreload;
return hw->hw_timer[timer_num].config.tx_autoreload;
}
/**
@ -204,8 +204,8 @@ FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t time
*/
FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value)
{
hw->hw_timer[timer_num].alarm_high = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value;
hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32);
hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value;
}
/**
@ -219,7 +219,7 @@ FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t time
*/
static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value)
{
*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high << 32) | (hw->hw_timer[timer_num].alarm_low);
*alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarmhi.tx_alarm_hi << 32) | (hw->hw_timer[timer_num].alarmlo.tx_alarm_lo);
}
/**
@ -233,7 +233,7 @@ static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en)
{
hw->hw_timer[timer_num].config.alarm_en = alarm_en;
hw->hw_timer[timer_num].config.tx_alarm_en = alarm_en;
}
/**
@ -248,7 +248,7 @@ FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.alarm_en;
return hw->hw_timer[timer_num].config.tx_alarm_en;
}
/**
@ -261,8 +261,8 @@ static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_n
*/
FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_ena.val |= BIT(timer_num);
hw->hw_timer[timer_num].config.level_int_en = 1;
hw->int_ena_timers.val |= BIT(timer_num);
hw->hw_timer[timer_num].config.tx_level_int_en = 1;
}
/**
@ -275,8 +275,8 @@ FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_nu
*/
FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_ena.val &= (~BIT(timer_num));
hw->hw_timer[timer_num].config.level_int_en = 0;
hw->int_ena_timers.val &= (~BIT(timer_num));
hw->hw_timer[timer_num].config.tx_level_int_en = 0;
}
/**
@ -289,7 +289,7 @@ FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_n
*/
FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num)
{
hw->int_clr.val |= BIT(timer_num);
hw->int_clr_timers.val |= BIT(timer_num);
}
/**
@ -302,7 +302,7 @@ FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t ti
*/
FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
{
*intr_status = hw->int_st.val & 0x03;
*intr_status = hw->int_st_timers.val & 0x03;
}
/**
@ -316,7 +316,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_s
FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
{
timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
*intr_raw_status = hw->int_raw.val & 0x03;
*intr_raw_status = hw->int_raw_timers.val & 0x03;
}
/**
@ -330,7 +330,7 @@ FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uin
*/
static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool level_int_en)
{
hw->hw_timer[timer_num].config.level_int_en = level_int_en;
hw->hw_timer[timer_num].config.tx_level_int_en = level_int_en;
}
/**
@ -345,7 +345,7 @@ static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t tim
*/
static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.level_int_en;
return hw->hw_timer[timer_num].config.tx_level_int_en;
}
/**
@ -359,7 +359,7 @@ static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t tim
*/
static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en)
{
hw->hw_timer[timer_num].config.edge_int_en = edge_int_en;
hw->hw_timer[timer_num].config.tx_edge_int_en = edge_int_en;
}
/**
@ -374,7 +374,7 @@ static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t time
*/
static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.edge_int_en;
return hw->hw_timer[timer_num].config.tx_edge_int_en;
}
/**
@ -386,7 +386,7 @@ static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t time
*/
static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw)
{
return (uint32_t) & (hw->int_st.val);
return (uint32_t) & (hw->int_st_timers.val);
}
static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num)
@ -404,7 +404,7 @@ static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t ti
*/
static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num, bool use_xtal_en)
{
hw->hw_timer[timer_num].config.use_xtal = use_xtal_en;
hw->hw_timer[timer_num].config.tx_use_xtal = use_xtal_en;
}
/**
@ -418,7 +418,7 @@ static inline void timer_ll_set_use_xtal(timg_dev_t *hw, timer_idx_t timer_num,
*/
static inline bool timer_ll_get_use_xtal(timg_dev_t *hw, timer_idx_t timer_num)
{
return hw->hw_timer[timer_num].config.use_xtal;
return hw->hw_timer[timer_num].config.tx_use_xtal;
}
#ifdef __cplusplus

883
components/soc/esp32c3/include/soc/timer_group_reg.h
View File

@ -1,24 +1,17 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_REG_H_
#define _SOC_TIMG_REG_H_
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
@ -29,413 +22,559 @@ extern "C" {
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (BIT(12))
#define TIMG_T0_DIVCNT_RST_V 0x1
#define TIMG_T0_DIVCNT_RST_S 12
/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (BIT(9))
#define TIMG_T0_USE_XTAL_V 0x1
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
#define TIMG_T0_USE_XTAL_V 0x00000001U
#define TIMG_T0_USE_XTAL_S 9
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_HI 0x003FFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0x3FFFFF
/** TIMG_T0HI_REG register
* Timer $x current value, high 22 bits
*/
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (BIT(31))
#define TIMG_T0_UPDATE_V 0x1
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
/** TIMG_T0ALARMLO_REG register
* Timer $x alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_ALARM_HI 0x003FFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0x3FFFFF
/** TIMG_T0ALARMHI_REG register
* Timer $x alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
/** TIMG_T0LOADLO_REG register
* Timer $x reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_LOAD_HI 0x003FFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0x3FFFFF
/** TIMG_T0LOADHI_REG register
* Timer $x reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_V 0x1
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (BIT(21))
#define TIMG_WDT_USE_XTAL_V 0x1
#define TIMG_WDT_USE_XTAL_S 21
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_V 0x1
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_V 0x1
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
#define TIMG_WDT_USE_XTAL_V 0x00000001U
#define TIMG_WDT_USE_XTAL_S 21
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: */
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (BIT(0))
#define TIMG_WDT_DIVCNT_RST_V 0x1
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: */
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: */
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: */
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070)
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (BIT(1))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 1
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074)
/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (BIT(1))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 1
/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 1
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078)
/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (BIT(1))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 1
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c)
/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (BIT(1))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 1
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080)
/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
/*description: timeout if cali value counts over threshold*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
/*description: Cycles that release calibration timeout reset*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: timeout indicator*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_V 0x1
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */
/*description: */
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif
#endif /*_SOC_TIMG_REG_H_ */

761
components/soc/esp32c3/include/soc/timer_group_struct.h
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@ -1,222 +1,561 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
*/
typedef union {
struct {
union {
struct {
uint32_t reserved0: 9;
uint32_t use_xtal: 1;
uint32_t alarm_en: 1;
uint32_t reserved11: 1;
uint32_t divcnt_rst: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t enable: 1;
};
uint32_t val;
} config;
uint32_t cnt_low; /**/
union {
struct {
uint32_t hi: 22;
uint32_t reserved22:10;
};
uint32_t val;
} cnt_high;
union {
struct {
uint32_t reserved0: 31;
uint32_t update: 1;
};
uint32_t val;
} update;
uint32_t alarm_low; /**/
union {
struct {
uint32_t alarm_hi: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} alarm_high;
uint32_t load_low; /**/
union {
struct {
uint32_t load_hi: 22;
uint32_t reserved22:10;
};
uint32_t val;
} load_high;
uint32_t reload; /**/
} hw_timer[1];
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
union {
struct {
uint32_t reserved0: 12;
uint32_t appcpu_reset_en: 1;
uint32_t procpu_reset_en: 1;
uint32_t flashboot_mod_en: 1;
uint32_t sys_reset_length: 3;
uint32_t cpu_reset_length: 3;
uint32_t use_xtal: 1;
uint32_t conf_update_en: 1;
uint32_t stg3: 2;
uint32_t stg2: 2;
uint32_t stg1: 2;
uint32_t stg0: 2;
uint32_t en: 1;
};
uint32_t val;
} wdt_config0;
union {
struct {
uint32_t divcnt_rst: 1;
uint32_t reserved1: 15;
uint32_t clk_prescale: 16;
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
uint32_t wdt_config5; /**/
uint32_t wdt_feed; /**/
uint32_t wdt_wprotect; /**/
union {
struct {
uint32_t reserved0: 12;
uint32_t start_cycling: 1;
uint32_t clk_sel: 2;
uint32_t rdy: 1;
uint32_t max: 15;
uint32_t start: 1;
};
uint32_t val;
} rtc_cali_cfg;
union {
struct {
uint32_t cycling_data_vld: 1;
uint32_t reserved1: 6;
uint32_t value: 25;
};
uint32_t val;
} rtc_cali_cfg1;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t timeout: 1; /*timeout indicator*/
uint32_t reserved1: 2;
uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/
uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/
};
uint32_t val;
} rtc_cali_cfg2;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} timg_date;
union {
struct {
uint32_t reserved0: 29;
uint32_t wdt_clk_is_active: 1;
uint32_t timer_clk_is_active: 1;
uint32_t en: 1;
};
uint32_t val;
} clk;
uint32_t reserved_0:9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
/** tx_en : R/W; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer $x current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer $x alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer $x alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer $x reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer $x reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
uint32_t wdt_use_xtal:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Reserved
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Reserved
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_ena:1;
/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_raw:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_st:1;
/** wdt_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_clr:1;
/** wdt_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
uint32_t wdt_clk_is_active:1;
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
uint32_t timer_clk_is_active:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t config;
volatile timg_txlo_reg_t lo;
volatile timg_txhi_reg_t hi;
volatile timg_txupdate_reg_t update;
volatile timg_txalarmlo_reg_t alarmlo;
volatile timg_txalarmhi_reg_t alarmhi;
volatile timg_txloadlo_reg_t loadlo;
volatile timg_txloadhi_reg_t loadhi;
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct {
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SOC_TIMG_STRUCT_H_ */

888
components/soc/esp32h2/include/soc/timer_group_reg.h
View File

@ -1,24 +1,17 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_REG_H_
#define _SOC_TIMG_REG_H_
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
@ -29,418 +22,559 @@ extern "C" {
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
/* Possible values for TIMG_WDT_STGx */
#define TIMG_WDT_STG_SEL_OFF 0
#define TIMG_WDT_STG_SEL_INT 1
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (BIT(12))
#define TIMG_T0_DIVCNT_RST_V 0x1
#define TIMG_T0_DIVCNT_RST_S 12
/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (BIT(9))
#define TIMG_T0_USE_XTAL_V 0x1
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
#define TIMG_T0_USE_XTAL_V 0x00000001U
#define TIMG_T0_USE_XTAL_S 9
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_HI 0x003FFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0x3FFFFF
/** TIMG_T0HI_REG register
* Timer $x current value, high 22 bits
*/
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (BIT(31))
#define TIMG_T0_UPDATE_V 0x1
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
/** TIMG_T0ALARMLO_REG register
* Timer $x alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_ALARM_HI 0x003FFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0x3FFFFF
/** TIMG_T0ALARMHI_REG register
* Timer $x alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
/** TIMG_T0LOADLO_REG register
* Timer $x reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_LOAD_HI 0x003FFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0x3FFFFF
/** TIMG_T0LOADHI_REG register
* Timer $x reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_V 0x1
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (BIT(21))
#define TIMG_WDT_USE_XTAL_V 0x1
#define TIMG_WDT_USE_XTAL_S 21
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_V 0x1
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_V 0x1
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
#define TIMG_WDT_USE_XTAL_V 0x00000001U
#define TIMG_WDT_USE_XTAL_S 21
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: */
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (BIT(0))
#define TIMG_WDT_DIVCNT_RST_V 0x1
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: */
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: */
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: */
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070)
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (BIT(1))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 1
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074)
/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (BIT(1))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 1
/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 1
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078)
/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (BIT(1))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 1
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c)
/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (BIT(1))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 1
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080)
/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
/*description: timeout if cali value counts over threshold*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
/*description: Cycles that release calibration timeout reset*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: timeout indicator*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_V 0x1
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */
/*description: */
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif
#endif /*_SOC_TIMG_REG_H_ */

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components/soc/esp32h2/include/soc/timer_group_struct.h
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@ -1,222 +1,561 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
*/
typedef union {
struct {
union {
struct {
uint32_t reserved0: 9;
uint32_t use_xtal: 1;
uint32_t alarm_en: 1;
uint32_t reserved11: 1;
uint32_t divcnt_rst: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t enable: 1;
};
uint32_t val;
} config;
uint32_t cnt_low; /**/
union {
struct {
uint32_t hi: 22;
uint32_t reserved22:10;
};
uint32_t val;
} cnt_high;
union {
struct {
uint32_t reserved0: 31;
uint32_t update: 1;
};
uint32_t val;
} update;
uint32_t alarm_low; /**/
union {
struct {
uint32_t alarm_hi: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} alarm_high;
uint32_t load_low; /**/
union {
struct {
uint32_t load_hi: 22;
uint32_t reserved22:10;
};
uint32_t val;
} load_high;
uint32_t reload; /**/
} hw_timer[1];
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
union {
struct {
uint32_t reserved0: 12;
uint32_t appcpu_reset_en: 1;
uint32_t procpu_reset_en: 1;
uint32_t flashboot_mod_en: 1;
uint32_t sys_reset_length: 3;
uint32_t cpu_reset_length: 3;
uint32_t use_xtal: 1;
uint32_t conf_update_en: 1;
uint32_t stg3: 2;
uint32_t stg2: 2;
uint32_t stg1: 2;
uint32_t stg0: 2;
uint32_t en: 1;
};
uint32_t val;
} wdt_config0;
union {
struct {
uint32_t divcnt_rst: 1;
uint32_t reserved1: 15;
uint32_t clk_prescale: 16;
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
uint32_t wdt_config5; /**/
uint32_t wdt_feed; /**/
uint32_t wdt_wprotect; /**/
union {
struct {
uint32_t reserved0: 12;
uint32_t start_cycling: 1;
uint32_t clk_sel: 2;
uint32_t rdy: 1;
uint32_t max: 15;
uint32_t start: 1;
};
uint32_t val;
} rtc_cali_cfg;
union {
struct {
uint32_t cycling_data_vld: 1;
uint32_t reserved1: 6;
uint32_t value: 25;
};
uint32_t val;
} rtc_cali_cfg1;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t timeout: 1; /*timeout indicator*/
uint32_t reserved1: 2;
uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/
uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/
};
uint32_t val;
} rtc_cali_cfg2;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} timg_date;
union {
struct {
uint32_t reserved0: 29;
uint32_t wdt_clk_is_active: 1;
uint32_t timer_clk_is_active: 1;
uint32_t en: 1;
};
uint32_t val;
} clk;
uint32_t reserved_0:9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
/** tx_en : R/W; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer $x current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer $x alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer $x alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer $x reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer $x reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
uint32_t wdt_use_xtal:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Reserved
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Reserved
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_ena:1;
/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_raw:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_st:1;
/** wdt_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_clr:1;
/** wdt_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
uint32_t wdt_clk_is_active:1;
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
uint32_t timer_clk_is_active:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t config;
volatile timg_txlo_reg_t lo;
volatile timg_txhi_reg_t hi;
volatile timg_txupdate_reg_t update;
volatile timg_txalarmlo_reg_t alarmlo;
volatile timg_txalarmhi_reg_t alarmhi;
volatile timg_txloadlo_reg_t loadlo;
volatile timg_txloadhi_reg_t loadhi;
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct {
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SOC_TIMG_STRUCT_H_ */

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components/soc/esp32s2/include/soc/timer_group_reg.h
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components/soc/esp32s2/include/soc/timer_group_struct.h
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