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@ -108,6 +108,7 @@
|
||||
/components/esp_psram/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/system
|
||||
/components/esp_ringbuf/ @esp-idf-codeowners/system
|
||||
/components/esp_rom/ @esp-idf-codeowners/system @esp-idf-codeowners/bluetooth @esp-idf-codeowners/wifi
|
||||
/components/esp_security/ @esp-idf-codeowners/security
|
||||
/components/esp_system/ @esp-idf-codeowners/system
|
||||
/components/esp_timer/ @esp-idf-codeowners/system
|
||||
/components/esp-tls/ @esp-idf-codeowners/app-utilities
|
||||
|
@ -288,8 +288,8 @@ variables:
|
||||
git remote add origin "${CI_REPOSITORY_URL}"
|
||||
fi
|
||||
|
||||
.git_checkout_fetch_head: &git_checkout_fetch_head |
|
||||
git checkout FETCH_HEAD
|
||||
.git_checkout_ci_commit_sha: &git_checkout_ci_commit_sha |
|
||||
git checkout $CI_COMMIT_SHA
|
||||
git clean ${GIT_CLEAN_FLAGS}
|
||||
|
||||
# git diff requires two commits, with different CI env var
|
||||
@ -313,6 +313,7 @@ variables:
|
||||
git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||
git fetch origin $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||
export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_MERGE_REQUEST_DIFF_BASE_SHA $CI_MERGE_REQUEST_SOURCE_BRANCH_SHA)
|
||||
git fetch origin $CI_COMMIT_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||
# merge request pipelines, when the mr got conflicts
|
||||
elif [[ -n $CI_MERGE_REQUEST_DIFF_BASE_SHA ]]; then
|
||||
git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||
@ -328,7 +329,7 @@ variables:
|
||||
git fetch origin $CI_COMMIT_SHA --depth=2 ${GIT_FETCH_EXTRA_FLAGS}
|
||||
export GIT_DIFF_OUTPUT=$(git diff --name-only $CI_COMMIT_SHA~1 $CI_COMMIT_SHA)
|
||||
fi
|
||||
- *git_checkout_fetch_head
|
||||
- *git_checkout_ci_commit_sha
|
||||
- *common-before_scripts
|
||||
- *setup_tools_and_idf_python_venv
|
||||
- add_gitlab_ssh_keys
|
||||
@ -342,7 +343,7 @@ variables:
|
||||
- *git_init
|
||||
- *git_fetch_from_mirror_url_if_exists
|
||||
- git fetch origin "${CI_COMMIT_SHA}" --depth=1 ${GIT_FETCH_EXTRA_FLAGS}
|
||||
- *git_checkout_fetch_head
|
||||
- *git_checkout_ci_commit_sha
|
||||
- *common-before_scripts
|
||||
- *setup_tools_and_idf_python_venv
|
||||
- add_gitlab_ssh_keys
|
||||
|
@ -11,7 +11,7 @@ extra_default_build_targets:
|
||||
- esp32c61
|
||||
|
||||
bypass_check_test_targets:
|
||||
- esp32c61
|
||||
|
||||
#
|
||||
# These lines would
|
||||
# - enable the README.md check for esp32c6. Don't forget to add the build jobs in .gitlab/ci/build.yml
|
||||
|
@ -68,22 +68,6 @@ test_ldgen_on_host:
|
||||
variables:
|
||||
LC_ALL: C.UTF-8
|
||||
|
||||
test_reproducible_build:
|
||||
extends: .host_test_template
|
||||
script:
|
||||
- ./tools/ci/test_reproducible_build.sh
|
||||
artifacts:
|
||||
when: on_failure
|
||||
paths:
|
||||
- "**/sdkconfig"
|
||||
- "**/build*/*.bin"
|
||||
- "**/build*/*.elf"
|
||||
- "**/build*/*.map"
|
||||
- "**/build*/flasher_args.json"
|
||||
- "**/build*/*.bin"
|
||||
- "**/build*/bootloader/*.bin"
|
||||
- "**/build*/partition_table/*.bin"
|
||||
|
||||
test_spiffs_on_host:
|
||||
extends: .host_test_template
|
||||
script:
|
||||
@ -404,3 +388,17 @@ test_idf_build_apps_load_soc_caps:
|
||||
extends: .host_test_template
|
||||
script:
|
||||
- python tools/ci/check_soc_headers_load_in_idf_build_apps.py
|
||||
|
||||
test_nvs_gen_check:
|
||||
extends: .host_test_template
|
||||
artifacts:
|
||||
paths:
|
||||
- XUNIT_RESULT.xml
|
||||
- components/nvs_flash/nvs_partition_tool
|
||||
reports:
|
||||
junit: XUNIT_RESULT.xml
|
||||
variables:
|
||||
LC_ALL: C.UTF-8
|
||||
script:
|
||||
- cd ${IDF_PATH}/components/nvs_flash/nvs_partition_tool
|
||||
- pytest --noconftest test_nvs_gen_check.py --junitxml=XUNIT_RESULT.xml
|
||||
|
@ -168,3 +168,15 @@ pipeline_variables:
|
||||
- pipeline.env
|
||||
expire_in: 1 week
|
||||
when: always
|
||||
|
||||
redundant_pass_job:
|
||||
stage: pre_check
|
||||
tags: [shiny, fast_run]
|
||||
image: $ESP_ENV_IMAGE
|
||||
dependencies: null
|
||||
before_script: []
|
||||
cache: []
|
||||
extends: []
|
||||
script:
|
||||
- echo "This job is redundant to ensure the 'retry_failed_jobs' job can exist and not be skipped"
|
||||
when: always
|
||||
|
@ -1,6 +1,7 @@
|
||||
retry_failed_jobs:
|
||||
stage: retry_failed_jobs
|
||||
tags: [shiny, fast_run]
|
||||
allow_failure: true
|
||||
image: $ESP_ENV_IMAGE
|
||||
dependencies: null
|
||||
before_script: []
|
||||
@ -11,4 +12,4 @@ retry_failed_jobs:
|
||||
- python tools/ci/python_packages/gitlab_api.py retry_failed_jobs $CI_MERGE_REQUEST_PROJECT_ID --pipeline_id $CI_PIPELINE_ID
|
||||
when: manual
|
||||
needs:
|
||||
- generate_failed_jobs_report
|
||||
- redundant_pass_job
|
||||
|
@ -108,8 +108,6 @@
|
||||
- "tools/detect_python.sh"
|
||||
- "tools/detect_python.fish"
|
||||
|
||||
- "tools/ci/test_reproducible_build.sh"
|
||||
|
||||
- "tools/gen_soc_caps_kconfig/*"
|
||||
- "tools/gen_soc_caps_kconfig/test/test_gen_soc_caps_kconfig.py"
|
||||
|
||||
|
@ -16,7 +16,11 @@ endif()
|
||||
if(NOT BOOTLOADER_BUILD)
|
||||
|
||||
if(CONFIG_COMPILER_OPTIMIZATION_SIZE)
|
||||
if(CMAKE_C_COMPILER_ID MATCHES "Clang")
|
||||
list(APPEND compile_options "-Oz")
|
||||
else()
|
||||
list(APPEND compile_options "-Os")
|
||||
endif()
|
||||
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
||||
list(APPEND compile_options "-freorder-blocks")
|
||||
endif()
|
||||
@ -34,7 +38,11 @@ if(NOT BOOTLOADER_BUILD)
|
||||
else() # BOOTLOADER_BUILD
|
||||
|
||||
if(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE)
|
||||
if(CMAKE_C_COMPILER_ID MATCHES "Clang")
|
||||
list(APPEND compile_options "-Oz")
|
||||
else()
|
||||
list(APPEND compile_options "-Os")
|
||||
endif()
|
||||
if(CMAKE_C_COMPILER_ID MATCHES "GNU")
|
||||
list(APPEND compile_options "-freorder-blocks")
|
||||
endif()
|
||||
@ -152,46 +160,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
|
||||
list(APPEND compile_options "-fdump-rtl-expand")
|
||||
endif()
|
||||
|
||||
if(NOT ${CMAKE_C_COMPILER_VERSION} VERSION_LESS 8.0.0)
|
||||
if(CONFIG_COMPILER_HIDE_PATHS_MACROS)
|
||||
list(APPEND compile_options "-fmacro-prefix-map=${CMAKE_SOURCE_DIR}=.")
|
||||
list(APPEND compile_options "-fmacro-prefix-map=${IDF_PATH}=/IDF")
|
||||
endif()
|
||||
|
||||
if(CONFIG_APP_REPRODUCIBLE_BUILD)
|
||||
idf_build_set_property(DEBUG_PREFIX_MAP_GDBINIT "${BUILD_DIR}/prefix_map_gdbinit")
|
||||
|
||||
list(APPEND compile_options "-fdebug-prefix-map=${IDF_PATH}=/IDF")
|
||||
list(APPEND compile_options "-fdebug-prefix-map=${PROJECT_DIR}=/IDF_PROJECT")
|
||||
list(APPEND compile_options "-fdebug-prefix-map=${BUILD_DIR}=/IDF_BUILD")
|
||||
|
||||
# component dirs
|
||||
idf_build_get_property(python PYTHON)
|
||||
idf_build_get_property(idf_path IDF_PATH)
|
||||
idf_build_get_property(component_dirs BUILD_COMPONENT_DIRS)
|
||||
|
||||
execute_process(
|
||||
COMMAND ${python}
|
||||
"${idf_path}/tools/generate_debug_prefix_map.py"
|
||||
"${BUILD_DIR}"
|
||||
"${component_dirs}"
|
||||
OUTPUT_VARIABLE result
|
||||
RESULT_VARIABLE ret
|
||||
)
|
||||
if(NOT ret EQUAL 0)
|
||||
message(FATAL_ERROR "This is a bug. Please report to https://github.com/espressif/esp-idf/issues")
|
||||
endif()
|
||||
|
||||
spaces2list(result)
|
||||
list(LENGTH component_dirs length)
|
||||
math(EXPR max_index "${length} - 1")
|
||||
foreach(index RANGE ${max_index})
|
||||
list(GET component_dirs ${index} folder)
|
||||
list(GET result ${index} after)
|
||||
list(APPEND compile_options "-fdebug-prefix-map=${folder}=${after}")
|
||||
endforeach()
|
||||
endif()
|
||||
endif()
|
||||
__generate_prefix_map(prefix_map_compile_options)
|
||||
list(APPEND compile_options ${prefix_map_compile_options})
|
||||
|
||||
if(CONFIG_COMPILER_DISABLE_GCC12_WARNINGS)
|
||||
list(APPEND compile_options "-Wno-address"
|
||||
@ -227,8 +197,35 @@ endif()
|
||||
list(APPEND link_options "-fno-lto")
|
||||
|
||||
if(CONFIG_IDF_TARGET_LINUX AND CMAKE_HOST_SYSTEM_NAME STREQUAL "Darwin")
|
||||
list(APPEND link_options "-Wl,-dead_strip")
|
||||
# Not all versions of the MacOS linker support the -warn_commons flag.
|
||||
# ld version 1053.12 (and above) have been tested to support it.
|
||||
# Hence, we extract the version string from the linker output
|
||||
# before including the flag.
|
||||
|
||||
# Get the ld version, capturing both stdout and stderr
|
||||
execute_process(
|
||||
COMMAND ${CMAKE_LINKER} -v
|
||||
OUTPUT_VARIABLE LD_VERSION_OUTPUT
|
||||
ERROR_VARIABLE LD_VERSION_ERROR
|
||||
OUTPUT_STRIP_TRAILING_WHITESPACE
|
||||
ERROR_STRIP_TRAILING_WHITESPACE
|
||||
)
|
||||
|
||||
# Combine stdout and stderr
|
||||
set(LD_VERSION_OUTPUT "${LD_VERSION_OUTPUT}\n${LD_VERSION_ERROR}")
|
||||
|
||||
# Extract the version string
|
||||
string(REGEX MATCH "PROJECT:(ld|dyld)-([0-9]+)\\.([0-9]+)" LD_VERSION_MATCH "${LD_VERSION_OUTPUT}")
|
||||
set(LD_VERSION_MAJOR_MINOR "${CMAKE_MATCH_2}.${CMAKE_MATCH_3}")
|
||||
|
||||
message(STATUS "Linker Version: ${LD_VERSION_MAJOR_MINOR}")
|
||||
|
||||
# Compare the version with 1053.12
|
||||
if(LD_VERSION_MAJOR_MINOR VERSION_GREATER_EQUAL "1053.12")
|
||||
list(APPEND link_options "-Wl,-warn_commons")
|
||||
endif()
|
||||
|
||||
list(APPEND link_options "-Wl,-dead_strip")
|
||||
else()
|
||||
list(APPEND link_options "-Wl,--gc-sections")
|
||||
list(APPEND link_options "-Wl,--warn-common")
|
||||
|
21
Kconfig
21
Kconfig
@ -323,8 +323,8 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
||||
help
|
||||
This option sets compiler optimization level (gcc -O argument) for the app.
|
||||
|
||||
- The "Debug" setting will add the -0g flag to CFLAGS.
|
||||
- The "Size" setting will add the -0s flag to CFLAGS.
|
||||
- The "Debug" setting will add the -Og flag to CFLAGS.
|
||||
- The "Size" setting will add the -Os flag to CFLAGS (-Oz with Clang).
|
||||
- The "Performance" setting will add the -O2 flag to CFLAGS.
|
||||
- The "None" setting will add the -O0 flag to CFLAGS.
|
||||
|
||||
@ -345,7 +345,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
||||
config COMPILER_OPTIMIZATION_DEBUG
|
||||
bool "Debug (-Og)"
|
||||
config COMPILER_OPTIMIZATION_SIZE
|
||||
bool "Optimize for size (-Os)"
|
||||
bool "Optimize for size (-Os with GCC, -Oz with Clang)"
|
||||
config COMPILER_OPTIMIZATION_PERF
|
||||
bool "Optimize for performance (-O2)"
|
||||
config COMPILER_OPTIMIZATION_NONE
|
||||
@ -388,6 +388,21 @@ mainmenu "Espressif IoT Development Framework Configuration"
|
||||
|
||||
endchoice # assertions
|
||||
|
||||
config COMPILER_ASSERT_NDEBUG_EVALUATE
|
||||
bool "Enable the evaluation of the expression inside assert(X) when NDEBUG is set"
|
||||
default y
|
||||
help
|
||||
When NDEBUG is set, assert(X) will not cause code to trigger an assertion.
|
||||
With this option set, assert(X) will still evaluate the expression X, though
|
||||
the result will never cause an assertion. This means that if X is a function
|
||||
then the function will be called.
|
||||
|
||||
This is not according to the standard, which states that the assert(X) should
|
||||
be replaced with ((void)0) if NDEBUG is defined.
|
||||
|
||||
In ESP-IDF v6.0 the default behavior will change to "no" to be in line with the
|
||||
standard.
|
||||
|
||||
choice COMPILER_FLOAT_LIB_FROM
|
||||
prompt "Compiler float lib source"
|
||||
default COMPILER_FLOAT_LIB_FROM_RVFPLIB if ESP_ROM_HAS_RVFPLIB
|
||||
|
@ -2,6 +2,6 @@
|
||||
|
||||
components/app_update/test_apps:
|
||||
disable:
|
||||
- if: IDF_TARGET in ["esp32c5", "esp32c61"]
|
||||
- if: IDF_TARGET in ["esp32c61"]
|
||||
temporary: true
|
||||
reason: target esp32c5 is not supported yet # TODO: [ESP32C5] IDF-8640, IDF-10317, [ESP32C61] IDF-9245
|
||||
reason: target esp32c61 is not supported yet # TODO: [ESP32C61] IDF-9245
|
||||
|
@ -1,2 +1,2 @@
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
|
@ -19,7 +19,8 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
|
||||
|
||||
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep') # TODO: [ESP32C5] IDF-8640, IDF-10317
|
||||
# TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-10983
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
|
||||
@pytest.mark.generic
|
||||
def test_app_update(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases(timeout=90)
|
||||
|
@ -20,14 +20,14 @@ menu "Bootloader config"
|
||||
This option sets compiler optimization level (gcc -O argument)
|
||||
for the bootloader.
|
||||
|
||||
- The default "Size" setting will add the -0s flag to CFLAGS.
|
||||
- The default "Size" setting will add the -Os (-Oz with clang) flag to CFLAGS.
|
||||
- The "Debug" setting will add the -Og flag to CFLAGS.
|
||||
- The "Performance" setting will add the -O2 flag to CFLAGS.
|
||||
|
||||
Note that custom optimization levels may be unsupported.
|
||||
|
||||
config BOOTLOADER_COMPILER_OPTIMIZATION_SIZE
|
||||
bool "Size (-Os)"
|
||||
bool "Size (-Os with GCC, -Oz with Clang)"
|
||||
config BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG
|
||||
bool "Debug (-Og)"
|
||||
config BOOTLOADER_COMPILER_OPTIMIZATION_PERF
|
||||
@ -776,6 +776,33 @@ menu "Security features"
|
||||
This can lead to permanent bricking of the device, in case all keys are revoked
|
||||
because of signature verification failure.
|
||||
|
||||
config SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||
bool "Do not disable the ability to further read protect eFuses"
|
||||
depends on SECURE_BOOT_V2_ENABLED
|
||||
default n
|
||||
help
|
||||
If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS
|
||||
efuse when Secure Boot is enabled. This prevents any more efuses from being read protected.
|
||||
|
||||
If this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure
|
||||
Boot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and
|
||||
BLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the secure boot public key digest,
|
||||
causing an immediate denial of service and possibly allowing an additional fault injection attack to
|
||||
bypass the signature protection.
|
||||
|
||||
The option must be set when you need to program any read-protected key type into the efuses,
|
||||
e.g., HMAC, ECDSA etc. after secure boot has already been enabled on the device.
|
||||
Please refer to secure boot V2 documentation guide for more details.
|
||||
|
||||
NOTE: Once a BLOCK is read-protected, the application will read all zeros from that block
|
||||
|
||||
NOTE: If "UART ROM download mode (Permanently disabled (recommended))" or
|
||||
"UART ROM download mode (Permanently switch to Secure mode (recommended))" is set,
|
||||
then it is __NOT__ possible to read/write efuses using espefuse.py utility.
|
||||
However, efuse can be read/written from the application
|
||||
|
||||
Please refer to the Secure Boot V2 documentation guide for more information.
|
||||
|
||||
config SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT
|
||||
bool "Flash bootloader along with other artifacts when using the default flash command"
|
||||
depends on SECURE_BOOT_V2_ENABLED && SECURE_BOOT_BUILD_SIGNED_BINARIES
|
||||
@ -956,26 +983,6 @@ menu "Security features"
|
||||
image to this length. It is generally not recommended to set this option, unless you have a legacy
|
||||
partitioning scheme which doesn't support 64KB aligned partition lengths.
|
||||
|
||||
config SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||
bool "Allow additional read protecting of efuses"
|
||||
depends on SECURE_BOOT_INSECURE && SECURE_BOOT_V2_ENABLED
|
||||
help
|
||||
If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS
|
||||
efuse when Secure Boot is enabled. This prevents any more efuses from being read protected.
|
||||
|
||||
If this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure
|
||||
Boot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and
|
||||
BLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the public key digest, causing an
|
||||
immediate denial of service and possibly allowing an additional fault injection attack to
|
||||
bypass the signature protection.
|
||||
|
||||
NOTE: Once a BLOCK is read-protected, the application will read all zeros from that block
|
||||
|
||||
NOTE: If "UART ROM download mode (Permanently disabled (recommended))" or
|
||||
"UART ROM download mode (Permanently switch to Secure mode (recommended))" is set,
|
||||
then it is __NOT__ possible to read/write efuses using espefuse.py utility.
|
||||
However, efuse can be read/written from the application
|
||||
|
||||
config SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS
|
||||
bool "Leave unused digest slots available (not revoke)"
|
||||
depends on SECURE_BOOT_INSECURE && SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
|
||||
|
@ -18,19 +18,8 @@
|
||||
#endif
|
||||
#include "hal/spi_flash_ll.h"
|
||||
#include "rom/spi_flash.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
# include "soc/spi_struct.h"
|
||||
# include "soc/spi_reg.h"
|
||||
/* SPI flash controller */
|
||||
# define SPIFLASH SPI1
|
||||
# define SPI0 SPI0
|
||||
#else
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
#include "hal/spimem_flash_ll.h"
|
||||
# include "soc/spi_mem_struct.h"
|
||||
# include "soc/spi_mem_reg.h"
|
||||
/* SPI flash controller */
|
||||
# define SPIFLASH SPIMEM1
|
||||
# define SPI0 SPIMEM0
|
||||
#endif
|
||||
|
||||
// This dependency will be removed in the future. IDF-5025
|
||||
@ -334,7 +323,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
|
||||
ESP_EARLY_LOGD(TAG, "mmu set block paddr=0x%08" PRIx32 " (was 0x%08" PRIx32 ")", map_at, current_read_mapping);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//Should never fail if we only map a SPI_FLASH_MMU_PAGE_SIZE to the vaddr starting from FLASH_READ_VADDR
|
||||
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
|
||||
// Return value unused if asserts are disabled
|
||||
int e __attribute__((unused)) = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
|
||||
assert(e == 0);
|
||||
#else
|
||||
uint32_t actual_mapped_len = 0;
|
||||
@ -587,61 +577,43 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common(
|
||||
{
|
||||
assert(mosi_len <= 32);
|
||||
assert(miso_len <= 32);
|
||||
uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
|
||||
uint32_t old_user_reg = SPIFLASH.user.val;
|
||||
uint32_t old_user1_reg = SPIFLASH.user1.val;
|
||||
uint32_t old_user2_reg = SPIFLASH.user2.val;
|
||||
// Clear ctrl regs.
|
||||
SPIFLASH.ctrl.val = 0;
|
||||
uint32_t old_ctrl_reg = 0;
|
||||
uint32_t old_user_reg = 0;
|
||||
uint32_t old_user1_reg = 0;
|
||||
uint32_t old_user2_reg = 0;
|
||||
spi_flash_ll_get_common_command_register_info(&SPIMEM_LL_APB, &old_ctrl_reg, &old_user_reg, &old_user1_reg, &old_user2_reg);
|
||||
SPIMEM_LL_APB.ctrl.val = 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
spi_flash_ll_set_wp_level(&SPIFLASH, true);
|
||||
spi_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
|
||||
#else
|
||||
spimem_flash_ll_set_wp_level(&SPIFLASH, true);
|
||||
spimem_flash_ll_set_wp_level(&SPIMEM_LL_APB, true);
|
||||
#endif
|
||||
//command phase
|
||||
SPIFLASH.user.usr_command = 1;
|
||||
SPIFLASH.user2.usr_command_bitlen = 7;
|
||||
SPIFLASH.user2.usr_command_value = command;
|
||||
spi_flash_ll_set_command(&SPIMEM_LL_APB, command, 8);
|
||||
//addr phase
|
||||
SPIFLASH.user.usr_addr = addr_len > 0;
|
||||
SPIFLASH.user1.usr_addr_bitlen = addr_len - 1;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPIFLASH.addr = (addr_len > 0)? (address << (32-addr_len)) : 0;
|
||||
#else
|
||||
SPIFLASH.addr = address;
|
||||
#endif
|
||||
spi_flash_ll_set_addr_bitlen(&SPIMEM_LL_APB, addr_len);
|
||||
spi_flash_ll_set_usr_address(&SPIMEM_LL_APB, address, addr_len);
|
||||
//dummy phase
|
||||
uint32_t total_dummy = dummy_len;
|
||||
if (miso_len > 0) {
|
||||
total_dummy += g_rom_spiflash_dummy_len_plus[1];
|
||||
}
|
||||
SPIFLASH.user.usr_dummy = total_dummy > 0;
|
||||
SPIFLASH.user1.usr_dummy_cyclelen = total_dummy - 1;
|
||||
spi_flash_ll_set_dummy(&SPIMEM_LL_APB, total_dummy);
|
||||
//output data
|
||||
SPIFLASH.user.usr_mosi = mosi_len > 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
|
||||
#else
|
||||
SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
|
||||
#endif
|
||||
SPIFLASH.data_buf[0] = mosi_data;
|
||||
|
||||
spi_flash_ll_set_mosi_bitlen(&SPIMEM_LL_APB, mosi_len);
|
||||
spi_flash_ll_set_buffer_data(&SPIMEM_LL_APB, &mosi_data, mosi_len / 8);
|
||||
//input data
|
||||
SPIFLASH.user.usr_miso = miso_len > 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
|
||||
#else
|
||||
SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
|
||||
#endif
|
||||
spi_flash_ll_set_miso_bitlen(&SPIMEM_LL_APB, miso_len);
|
||||
|
||||
SPIFLASH.cmd.usr = 1;
|
||||
while (SPIFLASH.cmd.usr != 0) {
|
||||
spi_flash_ll_user_start(&SPIMEM_LL_APB, false);
|
||||
while(!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
|
||||
}
|
||||
SPIFLASH.ctrl.val = old_ctrl_reg;
|
||||
SPIFLASH.user.val = old_user_reg;
|
||||
SPIFLASH.user1.val = old_user1_reg;
|
||||
SPIFLASH.user2.val = old_user2_reg;
|
||||
spi_flash_ll_set_common_command_register_info(&SPIMEM_LL_APB, old_ctrl_reg, old_user_reg, old_user1_reg, old_user2_reg);
|
||||
|
||||
uint32_t ret = SPIFLASH.data_buf[0];
|
||||
uint32_t output_data = 0;
|
||||
spi_flash_ll_get_buffer_data(&SPIMEM_LL_APB, &output_data, miso_len / 8);
|
||||
uint32_t ret = output_data;
|
||||
if (miso_len < 32) {
|
||||
//set unused bits to 0
|
||||
ret &= ~(UINT32_MAX << miso_len);
|
||||
@ -793,28 +765,9 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
|
||||
|
||||
#endif //XMC_SUPPORT
|
||||
|
||||
FORCE_INLINE_ATTR void bootloader_mspi_reset(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SPI1.slave.sync_reset = 0;
|
||||
SPI0.slave.sync_reset = 0;
|
||||
SPI1.slave.sync_reset = 1;
|
||||
SPI0.slave.sync_reset = 1;
|
||||
SPI1.slave.sync_reset = 0;
|
||||
SPI0.slave.sync_reset = 0;
|
||||
#else
|
||||
SPIMEM1.ctrl2.sync_reset = 0;
|
||||
SPIMEM0.ctrl2.sync_reset = 0;
|
||||
SPIMEM1.ctrl2.sync_reset = 1;
|
||||
SPIMEM0.ctrl2.sync_reset = 1;
|
||||
SPIMEM1.ctrl2.sync_reset = 0;
|
||||
SPIMEM0.ctrl2.sync_reset = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
|
||||
{
|
||||
bootloader_mspi_reset();
|
||||
spi_flash_ll_sync_reset();
|
||||
// Seems that sync_reset cannot make host totally idle.'
|
||||
// Sending an extra(useless) command to make the host idle in order to send reset command.
|
||||
bootloader_execute_flash_command(0x05, 0, 0, 0);
|
||||
@ -844,7 +797,7 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
|
||||
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
|
||||
{
|
||||
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
|
||||
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0);
|
||||
uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPIMEM_LL_CACHE);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if (spi_ctrl & SPI_FREAD_QIO) {
|
||||
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -28,12 +28,12 @@
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_init.h"
|
||||
|
||||
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
|
||||
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
|
||||
#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
|
||||
#define FLASH_SPID_IO SPI_D_GPIO_NUM
|
||||
#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
|
||||
#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
|
||||
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
|
||||
#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0
|
||||
#define FLASH_SPIQ_IO MSPI_IOMUX_PIN_NUM_MISO
|
||||
#define FLASH_SPID_IO MSPI_IOMUX_PIN_NUM_MOSI
|
||||
#define FLASH_SPIWP_IO MSPI_IOMUX_PIN_NUM_WP
|
||||
#define FLASH_SPIHD_IO MSPI_IOMUX_PIN_NUM_HD
|
||||
|
||||
void bootloader_flash_update_id(void)
|
||||
{
|
||||
@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
|
||||
} else {
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
|
||||
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
|
||||
//select pin function gpio
|
||||
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
|
||||
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
|
||||
@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
|
||||
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
|
||||
return ESP32_PICO_V3_GPIO;
|
||||
default:
|
||||
return SPI_WP_GPIO_NUM;
|
||||
return MSPI_IOMUX_PIN_NUM_WP;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
// IDF-4066
|
||||
const uint32_t spiconfig = 0;
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
}
|
||||
|
@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
|
@ -74,12 +74,12 @@ static const char *TAG = "boot.esp32c5";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -24,6 +24,7 @@
|
||||
#include "hal/mmu_ll.h"
|
||||
#include "hal/cache_hal.h"
|
||||
#include "hal/cache_ll.h"
|
||||
#include "hal/mspi_timing_tuning_ll.h"
|
||||
|
||||
static const char *TAG __attribute__((unused)) = "boot.esp32c61";
|
||||
|
||||
@ -69,12 +70,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
@ -197,6 +198,13 @@ static void bootloader_spi_flash_resume(void)
|
||||
|
||||
esp_err_t bootloader_init_spi_flash(void)
|
||||
{
|
||||
|
||||
// Set source mspi pll clock as 80M in bootloader stage.
|
||||
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
|
||||
// in this stage, set divider as 6
|
||||
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
|
||||
mspi_ll_fast_set_hs_divider(6);
|
||||
|
||||
bootloader_init_flash_configure();
|
||||
bootloader_spi_flash_resume();
|
||||
bootloader_flash_unlock();
|
||||
|
@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -66,12 +66,12 @@ static const char *TAG = "boot.esp32p4";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
|
@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
|
||||
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
|
||||
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
|
||||
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
|
||||
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
|
||||
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
} else {
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -181,6 +181,20 @@ uint32_t bootloader_common_get_chip_ver_pkg(void);
|
||||
*/
|
||||
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type);
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
/**
|
||||
* @brief Check the eFuse block revision
|
||||
*
|
||||
* @param[in] min_rev_full The required minimum revision of the eFuse block
|
||||
* @param[in] max_rev_full The required maximum revision of the eFuse block
|
||||
* @return
|
||||
* - ESP_OK: The eFuse block revision is in the required range.
|
||||
* - ESP_OK: DISABLE_BLK_VERSION_MAJOR has been set in the eFuse of the SoC. No requirements shall be checked at this time.
|
||||
* - ESP_FAIL: The eFuse block revision of this chip does not match the requirement of the current image.
|
||||
*/
|
||||
esp_err_t bootloader_common_check_efuse_blk_validity(uint32_t min_rev_full, uint32_t max_rev_full);
|
||||
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
/**
|
||||
* @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
|
||||
*/
|
||||
|
@ -87,7 +87,7 @@ typedef enum {
|
||||
*
|
||||
* @return key type for the selected secure boot scheme
|
||||
*/
|
||||
static inline char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme)
|
||||
static inline const char* esp_secure_boot_get_scheme_name(esp_secure_boot_sig_scheme_t scheme)
|
||||
{
|
||||
switch (scheme) {
|
||||
case ESP_SECURE_BOOT_V2_RSA:
|
||||
|
@ -27,7 +27,7 @@
|
||||
#include "esp_rom_caps.h"
|
||||
|
||||
#define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
|
||||
#define IS_MAX_REV_SET(max_chip_rev_full) (((max_chip_rev_full) != 65535) && ((max_chip_rev_full) != 0))
|
||||
#define IS_FIELD_SET(rev_full) (((rev_full) != 65535) && ((rev_full) != 0))
|
||||
|
||||
static const char* TAG = "boot_comm";
|
||||
|
||||
@ -57,6 +57,31 @@ int bootloader_common_get_active_otadata(esp_ota_select_entry_t *two_otadata)
|
||||
return bootloader_common_select_otadata(two_otadata, valid_two_otadata, true);
|
||||
}
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
esp_err_t bootloader_common_check_efuse_blk_validity(uint32_t min_rev_full, uint32_t max_rev_full)
|
||||
{
|
||||
esp_err_t err = ESP_OK;
|
||||
#ifndef CONFIG_IDF_ENV_FPGA
|
||||
// Check whether the efuse block version satisfy the requirements of current image.
|
||||
uint32_t revision = efuse_hal_blk_version();
|
||||
uint32_t major_rev = revision / 100;
|
||||
uint32_t minor_rev = revision % 100;
|
||||
if (IS_FIELD_SET(min_rev_full) && !ESP_EFUSE_BLK_REV_ABOVE(revision, min_rev_full)) {
|
||||
ESP_LOGE(TAG, "Image requires efuse blk rev >= v%"PRIu32".%"PRIu32", but chip is v%"PRIu32".%"PRIu32,
|
||||
min_rev_full / 100, min_rev_full % 100, major_rev, minor_rev);
|
||||
err = ESP_FAIL;
|
||||
}
|
||||
// If burnt `disable_blk_version_major` bit, skip the max version check
|
||||
if ((IS_FIELD_SET(max_rev_full) && (revision > max_rev_full) && !efuse_hal_get_disable_blk_version_major())) {
|
||||
ESP_LOGE(TAG, "Image requires efuse blk rev <= v%"PRIu32".%"PRIu32", but chip is v%"PRIu32".%"PRIu32,
|
||||
max_rev_full / 100, max_rev_full % 100, major_rev, minor_rev);
|
||||
err = ESP_FAIL;
|
||||
}
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type)
|
||||
{
|
||||
esp_err_t err = ESP_OK;
|
||||
@ -80,7 +105,7 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
|
||||
}
|
||||
if (type == ESP_IMAGE_APPLICATION) {
|
||||
unsigned max_rev = img_hdr->max_chip_rev_full;
|
||||
if ((IS_MAX_REV_SET(max_rev) && (revision > max_rev) && !efuse_hal_get_disable_wafer_version_major())) {
|
||||
if ((IS_FIELD_SET(max_rev) && (revision > max_rev) && !efuse_hal_get_disable_wafer_version_major())) {
|
||||
ESP_LOGE(TAG, "Image requires chip rev <= v%d.%d, but chip is v%d.%d",
|
||||
max_rev / 100, max_rev % 100,
|
||||
major_rev, minor_rev);
|
||||
|
@ -48,8 +48,8 @@ void bootloader_console_init(void)
|
||||
|
||||
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
|
||||
// Some constants to make the following code less upper-case
|
||||
const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
|
||||
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
|
||||
const int uart_tx_gpio = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM;
|
||||
const int uart_rx_gpio = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM;
|
||||
|
||||
// Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
|
||||
esp_rom_output_set_as_console(uart_num);
|
||||
|
@ -43,10 +43,17 @@ esp_err_t bootloader_read_bootloader_header(void)
|
||||
|
||||
esp_err_t bootloader_check_bootloader_validity(void)
|
||||
{
|
||||
unsigned int revision = efuse_hal_chip_revision();
|
||||
unsigned int major = revision / 100;
|
||||
unsigned int minor = revision % 100;
|
||||
ESP_EARLY_LOGI(TAG, "chip revision: v%d.%d", major, minor);
|
||||
unsigned int chip_revision = efuse_hal_chip_revision();
|
||||
unsigned int chip_major_rev = chip_revision / 100;
|
||||
unsigned int chip_minor_rev = chip_revision % 100;
|
||||
ESP_EARLY_LOGI(TAG, "chip revision: v%d.%d", chip_major_rev, chip_minor_rev);
|
||||
/* ESP32 doesn't have more memory and more efuse bits for block major version. */
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
unsigned int efuse_revision = efuse_hal_blk_version();
|
||||
unsigned int efuse_major_rev = efuse_revision / 100;
|
||||
unsigned int efuse_minor_rev = efuse_revision % 100;
|
||||
ESP_EARLY_LOGI(TAG, "efuse block revision: v%d.%d", efuse_major_rev, efuse_minor_rev);
|
||||
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||
/* compare with the one set in bootloader image header */
|
||||
if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) {
|
||||
return ESP_FAIL;
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -69,11 +69,11 @@ static void bootloader_reset_mmu(void)
|
||||
}
|
||||
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
|
||||
static esp_err_t bootloader_check_rated_cpu_clock(void)
|
||||
static inline esp_err_t bootloader_check_rated_cpu_clock(void)
|
||||
{
|
||||
int rated_freq = bootloader_clock_get_rated_freq_mhz();
|
||||
if (rated_freq < CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) {
|
||||
ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig",
|
||||
ESP_LOGE(TAG, "Chip CPU freq rated for %dMHz, configured for %dMHz. Modify CPU freq in menuconfig",
|
||||
rated_freq, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
|
||||
return ESP_FAIL;
|
||||
}
|
||||
@ -119,19 +119,19 @@ static void wdt_reset_info_dump(int cpu)
|
||||
|
||||
if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
|
||||
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
|
||||
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
|
||||
ESP_LOGW(TAG, "WDT rst info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
|
||||
} else {
|
||||
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
|
||||
ESP_LOGW(TAG, "WDT rst info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
|
||||
}
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
|
||||
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
|
||||
ESP_LOGD(TAG, "WDT rst info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
|
||||
}
|
||||
|
||||
static void bootloader_check_wdt_reset(void)
|
||||
@ -143,12 +143,12 @@ static void bootloader_check_wdt_reset(void)
|
||||
rst_reas[1] = esp_rom_get_reset_reason(1);
|
||||
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
|
||||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
|
||||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
|
||||
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
|
||||
ESP_LOGW(TAG, "APP CPU has been reset by WDT");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (wdt_rst) {
|
||||
@ -215,7 +215,7 @@ esp_err_t bootloader_init(void)
|
||||
bootloader_flash_update_id();
|
||||
// Check and run XMC startup flow
|
||||
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
|
||||
ESP_LOGE(TAG, "XMC startup flow failed, reboot!");
|
||||
return ret;
|
||||
}
|
||||
// read bootloader header
|
||||
@ -232,7 +232,7 @@ esp_err_t bootloader_init(void)
|
||||
}
|
||||
#endif // #if !CONFIG_APP_BUILD_TYPE_RAM
|
||||
|
||||
// check whether a WDT reset happend
|
||||
// check whether a WDT reset happened
|
||||
bootloader_check_wdt_reset();
|
||||
// config WDT
|
||||
bootloader_config_wdt();
|
||||
|
@ -42,6 +42,7 @@
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "hal/lpwdt_ll.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "hal/brownout_ll.h"
|
||||
|
||||
static const char *TAG = "boot.esp32c5";
|
||||
|
||||
@ -94,9 +95,8 @@ static inline void bootloader_ana_reset_config(void)
|
||||
// TODO: [ESP32C5] IDF-8650
|
||||
//Enable super WDT reset.
|
||||
// bootloader_ana_super_wdt_reset_config(true);
|
||||
// TODO: [ESP32C5] IDF-8647
|
||||
//Enable BOD reset TODO: [ESP32C5] IDF-8667
|
||||
// brownout_ll_ana_reset_enable(true);
|
||||
//Enable BOD reset (mode1)
|
||||
brownout_ll_ana_reset_enable(true);
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init(void)
|
||||
|
@ -19,6 +19,6 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
|
||||
//Not supported but common bootloader calls the function. Do nothing
|
||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8667
|
||||
// TODO: [ESP32C5] IDF-8667, PM-207
|
||||
(void)enable;
|
||||
}
|
||||
|
@ -43,6 +43,7 @@
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "hal/lpwdt_ll.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "hal/brownout_ll.h"
|
||||
|
||||
static const char *TAG = "boot.esp32c61";
|
||||
|
||||
@ -94,8 +95,8 @@ static inline void bootloader_ana_reset_config(void)
|
||||
{
|
||||
//Enable super WDT reset.
|
||||
bootloader_ana_super_wdt_reset_config(true);
|
||||
//Enable BOD reset TODO: IDF-9254 BOD support
|
||||
// brownout_ll_ana_reset_enable(true);
|
||||
//Enable BOD reset (mode1)
|
||||
brownout_ll_ana_reset_enable(true);
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init(void)
|
||||
|
@ -691,19 +691,28 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
|
||||
|
||||
const uint32_t *src = data;
|
||||
|
||||
#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
||||
// Case I: Bootloader verifying application
|
||||
// Case II: Bootloader verifying bootloader
|
||||
// Anti-rollback check should handle only Case I from above.
|
||||
if (segment == 0 && metadata->start_addr != ESP_BOOTLOADER_OFFSET) {
|
||||
ESP_LOGD(TAG, "additional anti-rollback check 0x%"PRIx32, data_addr);
|
||||
// The esp_app_desc_t structure is located in DROM and is always in segment #0.
|
||||
// Anti-rollback check and efuse block version check should handle only Case I from above.
|
||||
if (segment == 0 && metadata->start_addr != ESP_BOOTLOADER_OFFSET) {
|
||||
/* ESP32 doesn't have more memory and more efuse bits for block major version. */
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
const esp_app_desc_t *app_desc = (const esp_app_desc_t *)src;
|
||||
esp_err_t ret = bootloader_common_check_efuse_blk_validity(app_desc->min_efuse_blk_rev_full, app_desc->max_efuse_blk_rev_full);
|
||||
if (ret != ESP_OK) {
|
||||
bootloader_munmap(data);
|
||||
return ret;
|
||||
}
|
||||
#endif // !CONFIG_IDF_TARGET_ESP32
|
||||
#if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
||||
ESP_LOGD(TAG, "additional anti-rollback check 0x%"PRIx32, data_addr);
|
||||
size_t len = process_esp_app_desc_data(src, sha_handle, checksum, metadata);
|
||||
data_len -= len;
|
||||
src += len / 4;
|
||||
// In BOOTLOADER_BUILD, for DROM (segment #0) we do not load it into dest (only map it), do_load = false.
|
||||
}
|
||||
#endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < data_len; i += 4) {
|
||||
int w_i = i / 4; // Word index
|
||||
|
@ -17,16 +17,15 @@
|
||||
#include "hal/wdt_hal.h"
|
||||
|
||||
// Need to remove check and merge accordingly for ESP32C5 once key manager support added in IDF-8621
|
||||
#if SOC_KEY_MANAGER_SUPPORTED || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "soc/keymng_reg.h"
|
||||
#include "hal/key_mgr_types.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#else
|
||||
#include "hal/key_mgr_hal.h"
|
||||
#else /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#include "hal/key_mgr_ll.h"
|
||||
#include "hal/mspi_timing_tuning_ll.h"
|
||||
#endif /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif
|
||||
#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||
|
||||
#ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
|
||||
#include "soc/sensitive_reg.h"
|
||||
@ -223,17 +222,25 @@ static esp_err_t check_and_generate_encryption_keys(void)
|
||||
ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
|
||||
}
|
||||
// Need to remove check for ESP32C5 and merge accordingly once key manager support added in IDF-8621
|
||||
#if SOC_KEY_MANAGER_SUPPORTED || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
|
||||
REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
||||
REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
|
||||
#else
|
||||
#else /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
// Enable and reset key manager
|
||||
// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
|
||||
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
|
||||
key_mgr_ll_enable_bus_clock(true);
|
||||
key_mgr_ll_enable_peripheral_clock(true);
|
||||
key_mgr_ll_reset_register();
|
||||
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
|
||||
};
|
||||
// Force Key Manager to use eFuse key for XTS-AES operation
|
||||
key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
|
||||
_mspi_timing_ll_reset_mspi();
|
||||
#endif /* CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif
|
||||
#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
|
||||
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -124,7 +124,31 @@ static size_t write_value(uint16_t conn_handle, uint16_t attr_handle,
|
||||
}
|
||||
}
|
||||
|
||||
/* Data may come in linked om. So retrieve all data */
|
||||
if (SLIST_NEXT(ctxt->om, om_next) != NULL) {
|
||||
uint8_t *fw_buf = (uint8_t *)malloc(517 * sizeof(uint8_t));
|
||||
memset(fw_buf, 0x0, 517);
|
||||
|
||||
memcpy(fw_buf, &ctxt->om->om_data[0], ctxt->om->om_len);
|
||||
struct os_mbuf *last;
|
||||
last = ctxt->om;
|
||||
uint32_t offset = ctxt->om->om_len;
|
||||
|
||||
while (SLIST_NEXT(last, om_next) != NULL) {
|
||||
struct os_mbuf *temp = SLIST_NEXT(last, om_next);
|
||||
memcpy(fw_buf + offset , &temp->om_data[0], temp->om_len);
|
||||
offset += temp->om_len;
|
||||
last = SLIST_NEXT(last, om_next);
|
||||
temp = NULL;
|
||||
}
|
||||
btc_blufi_recv_handler(fw_buf, offset);
|
||||
|
||||
free(fw_buf);
|
||||
}
|
||||
else {
|
||||
btc_blufi_recv_handler(&ctxt->om->om_data[0], ctxt->om->om_len);
|
||||
}
|
||||
|
||||
rc = ble_hs_mbuf_to_flat(ctxt->om, value->buf->om_data,
|
||||
value->buf->om_len, &len);
|
||||
if (rc != 0) {
|
||||
|
@ -271,11 +271,11 @@ _err:
|
||||
}
|
||||
|
||||
for (int i = 0; i < thread->work_queue_num; i++) {
|
||||
if (thread->work_queues[i]) {
|
||||
if (thread->work_queues && thread->work_queues[i]) {
|
||||
osi_work_queue_delete(thread->work_queues[i]);
|
||||
}
|
||||
thread->work_queues[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
if (thread->work_queues) {
|
||||
osi_free(thread->work_queues);
|
||||
|
@ -96,6 +96,7 @@ do{\
|
||||
#define OSI_VERSION 0x00010005
|
||||
#define OSI_MAGIC_VALUE 0xFADEBEAD
|
||||
|
||||
#define BLE_CONTROLLER_MALLOC_CAPS (MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL)
|
||||
/* Types definition
|
||||
************************************************************************
|
||||
*/
|
||||
@ -868,7 +869,21 @@ static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no)
|
||||
|
||||
static void *malloc_internal_wrapper(size_t size)
|
||||
{
|
||||
return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
|
||||
return heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||
}
|
||||
|
||||
void *malloc_ble_controller_mem(size_t size)
|
||||
{
|
||||
void *p = heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||
if(p == NULL) {
|
||||
ESP_LOGE(BTDM_LOG_TAG, "Malloc failed");
|
||||
}
|
||||
return p;
|
||||
}
|
||||
|
||||
uint32_t get_ble_controller_free_heap_size(void)
|
||||
{
|
||||
return heap_caps_get_free_size(BLE_CONTROLLER_MALLOC_CAPS);
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
||||
|
@ -49,6 +49,7 @@
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
#include "esp_private/sleep_modem.h"
|
||||
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
@ -75,11 +76,6 @@
|
||||
#define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
|
||||
|
||||
#define BT_ASSERT_PRINT ets_printf
|
||||
typedef enum ble_rtc_slow_clk_src {
|
||||
BT_SLOW_CLK_SRC_MAIN_XTAL,
|
||||
BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0,
|
||||
} ble_rtc_slow_clk_src_t;
|
||||
|
||||
/* Types definition
|
||||
************************************************************************
|
||||
*/
|
||||
@ -442,6 +438,7 @@ static bool s_ble_active = false;
|
||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||
|
||||
#define BLE_RTC_DELAY_US (1800)
|
||||
|
||||
@ -556,6 +553,20 @@ void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
|
||||
}
|
||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||
{
|
||||
return s_bt_lpclk_src;
|
||||
}
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||
{
|
||||
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
s_bt_lpclk_src = clk_src;
|
||||
}
|
||||
|
||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||
{
|
||||
if (!s_ble_active) {
|
||||
@ -582,7 +593,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
|
||||
s_ble_active = true;
|
||||
}
|
||||
|
||||
esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
|
||||
esp_err_t controller_sleep_init(modem_clock_lpclk_src_t slow_clk_src)
|
||||
{
|
||||
esp_err_t rc = 0;
|
||||
#ifdef CONFIG_BT_LE_SLEEP_ENABLE
|
||||
@ -590,7 +601,7 @@ esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
|
||||
r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
|
||||
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
if (slow_clk_src == BT_SLOW_CLK_SRC_MAIN_XTAL) {
|
||||
if (slow_clk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
|
||||
} else {
|
||||
esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
|
||||
@ -645,11 +656,11 @@ void controller_sleep_deinit(void)
|
||||
#endif //CONFIG_PM_ENABLE
|
||||
}
|
||||
|
||||
static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
|
||||
static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)
|
||||
{
|
||||
/* Select slow clock source for BT momdule */
|
||||
switch (slow_clk_src) {
|
||||
case BT_SLOW_CLK_SRC_MAIN_XTAL:
|
||||
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
|
||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
|
||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
|
||||
@ -661,7 +672,7 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
|
||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
|
||||
#endif // CONFIG_XTAL_FREQ_26
|
||||
break;
|
||||
case BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0:
|
||||
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
|
||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
|
||||
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
|
||||
@ -678,40 +689,39 @@ static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
|
||||
SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
|
||||
}
|
||||
|
||||
static ble_rtc_slow_clk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||
static modem_clock_lpclk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
ble_rtc_slow_clk_src_t slow_clk_src;
|
||||
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
#ifdef CONFIG_XTAL_FREQ_26
|
||||
cfg->rtc_freq = 40000;
|
||||
#else
|
||||
cfg->rtc_freq = 32000;
|
||||
#endif // CONFIG_XTAL_FREQ_26
|
||||
slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
#else
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
|
||||
cfg->rtc_freq = 32768;
|
||||
slow_clk_src = BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0;
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
}
|
||||
#endif // CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
}
|
||||
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||
cfg->rtc_freq = 32768;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||
#ifdef CONFIG_XTAL_FREQ_26
|
||||
cfg->rtc_freq = 40000;
|
||||
#else
|
||||
cfg->rtc_freq = 32000;
|
||||
#endif // CONFIG_XTAL_FREQ_26
|
||||
slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
|
||||
}
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
esp_bt_rtc_slow_clk_select(slow_clk_src);
|
||||
return slow_clk_src;
|
||||
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||
return s_bt_lpclk_src;
|
||||
}
|
||||
|
||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
ble_npl_count_info_t npl_info;
|
||||
ble_rtc_slow_clk_src_t rtc_clk_src;
|
||||
modem_clock_lpclk_src_t rtc_clk_src;
|
||||
uint8_t hci_transport_mode;
|
||||
|
||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||
|
@ -120,6 +120,7 @@ do{\
|
||||
|
||||
#define BLE_PWR_HDL_INVL 0xFFFF
|
||||
|
||||
#define BLE_CONTROLLER_MALLOC_CAPS (MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA)
|
||||
/* Types definition
|
||||
************************************************************************
|
||||
*/
|
||||
@ -689,13 +690,27 @@ static bool IRAM_ATTR is_in_isr_wrapper(void)
|
||||
|
||||
static void *malloc_internal_wrapper(size_t size)
|
||||
{
|
||||
void *p = heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA);
|
||||
void *p = heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||
if(p == NULL) {
|
||||
ESP_LOGE(BT_LOG_TAG, "Malloc failed");
|
||||
}
|
||||
return p;
|
||||
}
|
||||
|
||||
void *malloc_ble_controller_mem(size_t size)
|
||||
{
|
||||
void *p = heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
|
||||
if(p == NULL) {
|
||||
ESP_LOGE(BT_LOG_TAG, "Malloc failed");
|
||||
}
|
||||
return p;
|
||||
}
|
||||
|
||||
uint32_t get_ble_controller_free_heap_size(void)
|
||||
{
|
||||
return heap_caps_get_free_size(BLE_CONTROLLER_MALLOC_CAPS);
|
||||
}
|
||||
|
||||
static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
||||
{
|
||||
int ret = esp_read_mac(mac, ESP_MAC_BT);
|
||||
|
@ -39,11 +39,10 @@
|
||||
#include "esp_pm.h"
|
||||
#include "esp_phy_init.h"
|
||||
#include "esp_private/periph_ctrl.h"
|
||||
#include "bt_osi_mem.h"
|
||||
|
||||
#if SOC_PM_RETENTION_HAS_CLOCK_BUG
|
||||
#include "soc/retention_periph_defs.h"
|
||||
#include "esp_private/sleep_retention.h"
|
||||
#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
|
||||
#include "soc/regdma.h"
|
||||
#include "bt_osi_mem.h"
|
||||
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
#include "esp_private/sleep_modem.h"
|
||||
@ -52,9 +51,6 @@
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
#include "esp_private/periph_ctrl.h"
|
||||
#include "esp_sleep.h"
|
||||
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "soc/rtc.h"
|
||||
/* Macro definition
|
||||
@ -190,6 +186,7 @@ static bool s_ble_active = false;
|
||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||
|
||||
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
|
||||
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
|
||||
@ -333,6 +330,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
|
||||
}
|
||||
}
|
||||
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||
{
|
||||
return s_bt_lpclk_src;
|
||||
}
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||
{
|
||||
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
s_bt_lpclk_src = clk_src;
|
||||
}
|
||||
|
||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||
{
|
||||
if (!s_ble_active) {
|
||||
@ -362,25 +373,53 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
|
||||
}
|
||||
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
// TODO: IDF-10765
|
||||
// static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
|
||||
// {
|
||||
// uint8_t size;
|
||||
// int extra = *(int *)arg;
|
||||
// const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
||||
// esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
// if (err == ESP_OK) {
|
||||
// ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||
// }
|
||||
// return err;
|
||||
// return ESP_OK;
|
||||
// }
|
||||
|
||||
static esp_err_t sleep_modem_ble_mac_modem_state_init(uint8_t extra)
|
||||
{
|
||||
uint8_t size;
|
||||
const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
||||
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
if (err == ESP_OK) {
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||
}
|
||||
return err;
|
||||
// TODO: IDF-10765
|
||||
// int retention_args = extra;
|
||||
// sleep_retention_module_init_param_t init_param = {
|
||||
// .cbs = { .create = { .handle = sleep_modem_ble_mac_retention_init, .arg = &retention_args } },
|
||||
// .depends = BIT(SLEEP_RETENTION_MODULE_BT_BB)
|
||||
// };
|
||||
// esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_BLE_MAC, &init_param);
|
||||
// if (err == ESP_OK) {
|
||||
// err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
// }
|
||||
// return err;
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "This func temporary not supported for current target!");
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static void sleep_modem_ble_mac_modem_state_deinit(void)
|
||||
{
|
||||
sleep_retention_entries_destroy(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
// TODO: IDF-10765
|
||||
// esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
// if (err == ESP_OK) {
|
||||
// err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
// assert(err == ESP_OK);
|
||||
// }
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "This func temporary not supported for current target!");
|
||||
}
|
||||
|
||||
void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
|
||||
{
|
||||
esp_ble_set_wakeup_overhead(overhead);
|
||||
// TODO: IDF-10765
|
||||
// esp_ble_set_wakeup_overhead(overhead);
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "This func temporary not supported for current target!");
|
||||
}
|
||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||
|
||||
@ -534,12 +573,51 @@ void ble_controller_scan_duplicate_config(void)
|
||||
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
||||
}
|
||||
|
||||
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
#else
|
||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
}
|
||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||
#else
|
||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||
assert(0);
|
||||
#endif
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
}
|
||||
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||
cfg->rtc_freq = 100000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
|
||||
cfg->rtc_freq = 32768;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
|
||||
cfg->rtc_freq = 30000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
|
||||
cfg->rtc_freq = 32000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||
cfg->rtc_freq = 32000;
|
||||
}
|
||||
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||
}
|
||||
|
||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
uint8_t mac[6];
|
||||
esp_err_t ret = ESP_OK;
|
||||
ble_npl_count_info_t npl_info;
|
||||
uint32_t slow_clk_freq = 0;
|
||||
uint8_t hci_transport_mode;
|
||||
|
||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||
@ -592,33 +670,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
modem_clock_module_enable(PERIPH_BT_MODULE);
|
||||
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
||||
/* Select slow clock source for BT momdule */
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
||||
slow_clk_freq = 100000;
|
||||
#else
|
||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
|
||||
slow_clk_freq = 30000;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
|
||||
slow_clk_freq = 32768;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
||||
slow_clk_freq = 100000;
|
||||
}
|
||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
|
||||
slow_clk_freq = 32000;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
|
||||
slow_clk_freq = 32000;
|
||||
#else
|
||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||
assert(0);
|
||||
#endif
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
ble_rtc_clk_init(cfg);
|
||||
esp_phy_modem_init();
|
||||
|
||||
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
||||
@ -664,7 +716,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
}
|
||||
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
||||
r_esp_ble_change_rtc_freq(slow_clk_freq);
|
||||
|
||||
ble_controller_scan_duplicate_config();
|
||||
|
||||
|
@ -134,7 +134,7 @@ extern void r_ble_rtc_wake_up_state_clr(void);
|
||||
extern int os_msys_init(void);
|
||||
extern void os_msys_deinit(void);
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
||||
extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
||||
extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
|
||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||
extern void r_esp_ble_change_rtc_freq(uint32_t freq);
|
||||
@ -393,6 +393,7 @@ static bool s_ble_active = false;
|
||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||
|
||||
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
|
||||
#define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
|
||||
@ -536,6 +537,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
|
||||
}
|
||||
}
|
||||
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||
{
|
||||
return s_bt_lpclk_src;
|
||||
}
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||
{
|
||||
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
s_bt_lpclk_src = clk_src;
|
||||
}
|
||||
|
||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||
{
|
||||
if (!s_ble_active) {
|
||||
@ -569,7 +584,7 @@ static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
|
||||
{
|
||||
uint8_t size;
|
||||
int extra = *(int *)arg;
|
||||
const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
||||
sleep_retention_entries_config_t *ble_mac_modem_config = r_esp_ble_mac_retention_link_get(&size, extra);
|
||||
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
if (err == ESP_OK) {
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||
@ -759,12 +774,51 @@ void ble_controller_scan_duplicate_config(void)
|
||||
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
||||
}
|
||||
|
||||
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
#else
|
||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
}
|
||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||
#else
|
||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||
assert(0);
|
||||
#endif
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
}
|
||||
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||
cfg->rtc_freq = 100000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
|
||||
cfg->rtc_freq = 32768;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
|
||||
cfg->rtc_freq = 30000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
|
||||
cfg->rtc_freq = 32000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||
cfg->rtc_freq = 32000;
|
||||
}
|
||||
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||
}
|
||||
|
||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
uint8_t mac[6];
|
||||
esp_err_t ret = ESP_OK;
|
||||
ble_npl_count_info_t npl_info;
|
||||
uint32_t slow_clk_freq = 0;
|
||||
uint8_t hci_transport_mode;
|
||||
|
||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||
@ -816,33 +870,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
modem_clock_module_enable(PERIPH_BT_MODULE);
|
||||
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
||||
/* Select slow clock source for BT momdule */
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
||||
slow_clk_freq = 100000;
|
||||
#else
|
||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
|
||||
slow_clk_freq = 30000;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
|
||||
slow_clk_freq = 32768;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
||||
slow_clk_freq = 100000;
|
||||
}
|
||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
|
||||
slow_clk_freq = 32000;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
|
||||
slow_clk_freq = 32000;
|
||||
#else
|
||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||
assert(0);
|
||||
#endif
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
ble_rtc_clk_init(cfg);
|
||||
esp_phy_modem_init();
|
||||
|
||||
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
||||
@ -875,7 +903,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
}
|
||||
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
||||
r_esp_ble_change_rtc_freq(slow_clk_freq);
|
||||
|
||||
ble_controller_scan_duplicate_config();
|
||||
|
||||
|
@ -126,9 +126,12 @@ extern void r_ble_rtc_wake_up_state_clr(void);
|
||||
extern int os_msys_init(void);
|
||||
extern void os_msys_deinit(void);
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
||||
extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
|
||||
extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
|
||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||
#if CONFIG_PM_ENABLE
|
||||
extern void r_esp_ble_stop_wakeup_timing(void);
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
extern void r_esp_ble_change_rtc_freq(uint32_t freq);
|
||||
extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
|
||||
const uint8_t *peer_pub_key_y,
|
||||
@ -384,6 +387,7 @@ static bool s_ble_active = false;
|
||||
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
|
||||
#define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
||||
|
||||
#define BLE_RTC_DELAY_US_LIGHT_SLEEP (5100)
|
||||
#define BLE_RTC_DELAY_US_MODEM_SLEEP (1500)
|
||||
@ -522,6 +526,20 @@ void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
|
||||
}
|
||||
}
|
||||
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
|
||||
{
|
||||
return s_bt_lpclk_src;
|
||||
}
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
|
||||
{
|
||||
if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
|
||||
return;
|
||||
}
|
||||
|
||||
s_bt_lpclk_src = clk_src;
|
||||
}
|
||||
|
||||
IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
|
||||
{
|
||||
if (!s_ble_active) {
|
||||
@ -555,7 +573,7 @@ static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
|
||||
{
|
||||
uint8_t size;
|
||||
int extra = *(int *)arg;
|
||||
const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
|
||||
sleep_retention_entries_config_t *ble_mac_modem_config = r_esp_ble_mac_retention_link_get(&size, extra);
|
||||
esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
|
||||
if (err == ESP_OK) {
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
|
||||
@ -613,6 +631,9 @@ esp_err_t controller_sleep_init(void)
|
||||
if (rc != ESP_OK) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
rc = esp_deep_sleep_register_hook(&r_esp_ble_stop_wakeup_timing);
|
||||
assert(rc == 0);
|
||||
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
|
||||
/* Create a new regdma link for BLE related register restoration */
|
||||
rc = sleep_modem_ble_mac_modem_state_init(0);
|
||||
@ -633,6 +654,7 @@ error:
|
||||
esp_sleep_disable_bt_wakeup();
|
||||
esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
|
||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||
esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
|
||||
/*lock should release first and then delete*/
|
||||
if (s_pm_lock != NULL) {
|
||||
esp_pm_lock_delete(s_pm_lock);
|
||||
@ -652,6 +674,7 @@ void controller_sleep_deinit(void)
|
||||
esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
|
||||
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
|
||||
/* lock should be released first */
|
||||
esp_pm_lock_delete(s_pm_lock);
|
||||
s_pm_lock = NULL;
|
||||
@ -729,12 +752,51 @@ void ble_controller_scan_duplicate_config(void)
|
||||
ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
|
||||
}
|
||||
|
||||
static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
#else
|
||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
|
||||
}
|
||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
|
||||
#else
|
||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||
assert(0);
|
||||
#endif
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
}
|
||||
|
||||
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
||||
cfg->rtc_freq = 100000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
|
||||
cfg->rtc_freq = 32768;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
|
||||
cfg->rtc_freq = 30000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
|
||||
cfg->rtc_freq = 32000;
|
||||
} else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
|
||||
cfg->rtc_freq = 32000;
|
||||
}
|
||||
esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
|
||||
}
|
||||
|
||||
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
{
|
||||
uint8_t mac[6];
|
||||
esp_err_t ret = ESP_OK;
|
||||
ble_npl_count_info_t npl_info;
|
||||
uint32_t slow_clk_freq = 0;
|
||||
uint8_t hci_transport_mode;
|
||||
|
||||
memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
|
||||
@ -786,33 +848,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
modem_clock_module_enable(PERIPH_BT_MODULE);
|
||||
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
|
||||
/* Select slow clock source for BT momdule */
|
||||
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
||||
slow_clk_freq = 100000;
|
||||
#else
|
||||
#if CONFIG_RTC_CLK_SRC_INT_RC
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
|
||||
slow_clk_freq = 30000;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
|
||||
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
|
||||
slow_clk_freq = 32768;
|
||||
} else {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
|
||||
slow_clk_freq = 100000;
|
||||
}
|
||||
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
|
||||
slow_clk_freq = 32000;
|
||||
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
|
||||
esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
|
||||
slow_clk_freq = 32000;
|
||||
#else
|
||||
ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
|
||||
assert(0);
|
||||
#endif
|
||||
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
|
||||
ble_rtc_clk_init(cfg);
|
||||
|
||||
if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
|
||||
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
|
||||
@ -844,7 +880,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
||||
}
|
||||
|
||||
ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
|
||||
r_esp_ble_change_rtc_freq(slow_clk_freq);
|
||||
|
||||
ble_controller_scan_duplicate_config();
|
||||
|
||||
|
@ -1 +1 @@
|
||||
Subproject commit 70337acad449a838ebe8e49b92e201a82bcb9773
|
||||
Subproject commit 8112ca2c575c6feb32d755623f097f1b66759490
|
@ -1 +1 @@
|
||||
Subproject commit eefd7794e627dca4fa20f2d8e43385c1360d9a58
|
||||
Subproject commit e652624750341aca124e9f850e261b0c1ac63529
|
@ -1 +1 @@
|
||||
Subproject commit ef1dfc518572e9cda55f13906e32207b40ee280b
|
||||
Subproject commit d874f55e1132416fe18293ae1aa9ac73c40b3261
|
@ -1 +1 @@
|
||||
Subproject commit cd00b30bbce183062b5231488e97c20a464aa460
|
||||
Subproject commit 53056440bc6e76f5bf00fd920769a4979dcc7d66
|
@ -1 +1 @@
|
||||
Subproject commit aa8d03a0ff51c166267207e54002613bcedc576e
|
||||
Subproject commit f95513f22be7b21429b01ba05dbfbc98097b5e67
|
@ -1 +1 @@
|
||||
Subproject commit 1db0566dcdf5a0bd69632415f6dd148ab2ea0ac6
|
||||
Subproject commit 58a293a2b4c305157723908ea29c2776f5803bbc
|
@ -244,7 +244,8 @@ static void time_get(struct bt_mesh_model *model,
|
||||
change.time_status.subsecond = srv->state->time.subsecond;
|
||||
change.time_status.uncertainty = srv->state->time.uncertainty;
|
||||
change.time_status.time_authority = srv->state->time.time_authority;
|
||||
change.time_status.tai_utc_delta_curr = srv->state->time.subsecond;
|
||||
change.time_status.tai_utc_delta_curr = srv->state->time.tai_utc_delta_curr;
|
||||
change.time_status.time_zone_offset_curr = srv->state->time.time_zone_offset_curr;
|
||||
bt_mesh_time_scene_server_cb_evt_to_btc(BTC_BLE_MESH_EVT_TIME_SCENE_SERVER_STATE_CHANGE,
|
||||
model, ctx, (const uint8_t *)&change, sizeof(change));
|
||||
|
||||
@ -386,7 +387,8 @@ static void time_set(struct bt_mesh_model *model,
|
||||
change.time_set.subsecond = srv->state->time.subsecond;
|
||||
change.time_set.uncertainty = srv->state->time.uncertainty;
|
||||
change.time_set.time_authority = srv->state->time.time_authority;
|
||||
change.time_set.tai_utc_delta_curr = srv->state->time.subsecond;
|
||||
change.time_set.tai_utc_delta_curr = srv->state->time.tai_utc_delta_curr;
|
||||
change.time_set.time_zone_offset_curr = srv->state->time.time_zone_offset_curr;
|
||||
break;
|
||||
case BLE_MESH_MODEL_OP_TIME_ZONE_SET:
|
||||
change.time_zone_set.time_zone_offset_new = srv->state->time.time_zone_offset_new;
|
||||
|
@ -238,3 +238,14 @@ esp_err_t esp_bluedroid_deinit(void)
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_EXAMPLE_CI_ID) && defined(CONFIG_EXAMPLE_CI_PIPELINE_ID)
|
||||
char *esp_bluedroid_get_example_name(void)
|
||||
{
|
||||
static char example_name[ESP_BLE_ADV_NAME_LEN_MAX];
|
||||
memset(example_name, 0, sizeof(example_name));
|
||||
sprintf(example_name, "BE%02X_%05X_%02X", CONFIG_EXAMPLE_CI_ID & 0xFF,
|
||||
CONFIG_EXAMPLE_CI_PIPELINE_ID & 0xFFFFF, CONFIG_IDF_FIRMWARE_CHIP_ID & 0xFF);
|
||||
return example_name;
|
||||
}
|
||||
#endif
|
||||
|
@ -504,21 +504,37 @@ esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
uint8_t *esp_ble_resolve_adv_data( uint8_t *adv_data, uint8_t type, uint8_t *length)
|
||||
uint8_t *esp_ble_resolve_adv_data_by_type( uint8_t *adv_data, uint16_t adv_data_len, esp_ble_adv_data_type type, uint8_t *length)
|
||||
{
|
||||
if (length == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (((type < ESP_BLE_AD_TYPE_FLAG) || (type > ESP_BLE_AD_TYPE_128SERVICE_DATA)) &&
|
||||
(type != ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE)) {
|
||||
LOG_ERROR("the eir type not define, type = %x\n", type);
|
||||
LOG_ERROR("The advertising data type is not defined, type = %x", type);
|
||||
*length = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (adv_data_len == 0) {
|
||||
*length = 0;
|
||||
return NULL;
|
||||
}
|
||||
if (adv_data == NULL) {
|
||||
LOG_ERROR("Invalid p_eir data.\n");
|
||||
LOG_ERROR("Invalid advertising data.");
|
||||
*length = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (BTM_CheckAdvData( adv_data, type, length));
|
||||
return (BTM_CheckAdvData( adv_data, adv_data_len, type, length));
|
||||
}
|
||||
|
||||
uint8_t *esp_ble_resolve_adv_data( uint8_t *adv_data, uint8_t type, uint8_t *length)
|
||||
{
|
||||
return esp_ble_resolve_adv_data_by_type( adv_data, ESP_BLE_ADV_DATA_LEN_MAX + ESP_BLE_SCAN_RSP_DATA_LEN_MAX, (esp_ble_adv_data_type) type, length);
|
||||
}
|
||||
|
||||
#if (BLE_42_FEATURE_SUPPORT == TRUE)
|
||||
esp_err_t esp_ble_gap_config_adv_data_raw(uint8_t *raw_data, uint32_t raw_data_len)
|
||||
{
|
||||
|
@ -184,6 +184,7 @@ esp_err_t esp_bt_gap_set_cod(esp_bt_cod_t cod, esp_bt_cod_mode_t mode)
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case ESP_BT_SET_COD_RESERVED_2:
|
||||
case ESP_BT_SET_COD_MAJOR_MINOR:
|
||||
case ESP_BT_SET_COD_SERVICE_CLASS:
|
||||
case ESP_BT_CLR_COD_SERVICE_CLASS:
|
||||
|
@ -209,6 +209,8 @@ typedef uint8_t esp_ble_key_mask_t; /* the key mask type */
|
||||
#define ESP_BD_ADDR_STR "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#define ESP_BD_ADDR_HEX(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]
|
||||
|
||||
#define ESP_BLE_ADV_NAME_LEN_MAX 29
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -95,6 +95,11 @@ esp_err_t esp_bluedroid_init_with_cfg(esp_bluedroid_config_t *cfg);
|
||||
*/
|
||||
esp_err_t esp_bluedroid_deinit(void);
|
||||
|
||||
#if defined(CONFIG_EXAMPLE_CI_ID) && defined(CONFIG_EXAMPLE_CI_PIPELINE_ID)
|
||||
// Only for internal used (CI example test)
|
||||
char *esp_bluedroid_get_example_name(void);
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -1903,9 +1903,32 @@ esp_err_t esp_ble_gap_get_device_name(void);
|
||||
*
|
||||
*/
|
||||
esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t * addr_type);
|
||||
|
||||
/**
|
||||
* @brief This function is called to get ADV data for a specific type.
|
||||
*
|
||||
* @note This is the recommended function to use for resolving ADV data by type.
|
||||
* It improves upon the deprecated `esp_ble_resolve_adv_data` function by
|
||||
* including an additional parameter to specify the length of the ADV data,
|
||||
* thereby offering better safety and reliability.
|
||||
*
|
||||
* @param[in] adv_data - pointer of ADV data which to be resolved
|
||||
* @param[in] adv_data_len - the length of ADV data which to be resolved.
|
||||
* @param[in] type - finding ADV data type
|
||||
* @param[out] length - return the length of ADV data not including type
|
||||
*
|
||||
* @return pointer of ADV data
|
||||
*
|
||||
*/
|
||||
uint8_t *esp_ble_resolve_adv_data_by_type( uint8_t *adv_data, uint16_t adv_data_len, esp_ble_adv_data_type type, uint8_t *length);
|
||||
|
||||
/**
|
||||
* @brief This function is called to get ADV data for a specific type.
|
||||
*
|
||||
* @note This function has been deprecated and will be removed in a future release.
|
||||
* Please use `esp_ble_resolve_adv_data_by_type` instead, which provides
|
||||
* better parameter validation and supports more accurate data resolution.
|
||||
*
|
||||
* @param[in] adv_data - pointer of ADV data which to be resolved
|
||||
* @param[in] type - finding ADV data type
|
||||
* @param[out] length - return the length of ADV data not including type
|
||||
@ -1914,6 +1937,7 @@ esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t
|
||||
*
|
||||
*/
|
||||
uint8_t *esp_ble_resolve_adv_data(uint8_t *adv_data, uint8_t type, uint8_t *length);
|
||||
|
||||
#if (BLE_42_FEATURE_SUPPORT == TRUE)
|
||||
/**
|
||||
* @brief This function is called to set raw advertising data. User need to fill
|
||||
|
@ -33,8 +33,9 @@ typedef enum {
|
||||
ESP_BT_SET_COD_MAJOR_MINOR = 0x01, /*!< overwrite major, minor class */
|
||||
ESP_BT_SET_COD_SERVICE_CLASS = 0x02, /*!< set the bits in the input, the current bit will remain */
|
||||
ESP_BT_CLR_COD_SERVICE_CLASS = 0x04, /*!< clear the bits in the input, others will remain */
|
||||
ESP_BT_SET_COD_ALL = 0x08, /*!< overwrite major, minor, set the bits in service class */
|
||||
ESP_BT_INIT_COD = 0x0a, /*!< overwrite major, minor, and service class */
|
||||
ESP_BT_SET_COD_ALL = 0x08, /*!< overwrite major, minor, set the bits in service class, reserved_2 remain unchanged */
|
||||
ESP_BT_INIT_COD = 0x0a, /*!< overwrite major, minor, and service class, reserved_2 remain unchanged */
|
||||
ESP_BT_SET_COD_RESERVED_2 = 0x10, /*!< overwrite the two least significant bits reserved_2 whose default value is 0b00; other values of reserved_2 are invalid according to Bluetooth Core Specification 5.4 */
|
||||
} esp_bt_cod_mode_t;
|
||||
|
||||
#define ESP_BT_GAP_AFH_CHANNELS_LEN 10
|
||||
@ -209,6 +210,28 @@ typedef enum {
|
||||
ESP_BT_COD_MAJOR_DEV_UNCATEGORIZED = 31, /*!< Uncategorized: device not specified */
|
||||
} esp_bt_cod_major_dev_t;
|
||||
|
||||
/// Minor device class field of Class of Device for Peripheral Major Class
|
||||
typedef enum {
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_KEYBOARD = 0x10, /*!< Keyboard */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_POINTING = 0x20, /*!< Pointing */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_COMBO = 0x30, /*!< Combo
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_KEYBOARD, ESP_BT_COD_MINOR_PERIPHERAL_POINTING
|
||||
and ESP_BT_COD_MINOR_PERIPHERAL_COMBO can be OR'd with one of the
|
||||
following values to identify a multifunctional device. e.g.
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_KEYBOARD | ESP_BT_COD_MINOR_PERIPHERAL_GAMEPAD
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_POINTING | ESP_BT_COD_MINOR_PERIPHERAL_SENSING_DEVICE
|
||||
*/
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_JOYSTICK = 0x01, /*!< Joystick */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_GAMEPAD = 0x02, /*!< Gamepad */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_REMOTE_CONTROL = 0x03, /*!< Remote Control */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_SENSING_DEVICE = 0x04, /*!< Sensing Device */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_DIGITIZING_TABLET = 0x05, /*!< Digitizing Tablet */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_CARD_READER = 0x06, /*!< Card Reader */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_DIGITAL_PAN = 0x07, /*!< Digital Pan */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_HAND_SCANNER = 0x08, /*!< Hand Scanner */
|
||||
ESP_BT_COD_MINOR_PERIPHERAL_HAND_GESTURAL_INPUT = 0x09, /*!< Hand Gestural Input */
|
||||
} esp_bt_cod_minor_peripheral_t;
|
||||
|
||||
/// Bits of major device class field
|
||||
#define ESP_BT_COD_MAJOR_DEV_BIT_MASK (0x1f00) /*!< Major device bit mask */
|
||||
#define ESP_BT_COD_MAJOR_DEV_BIT_OFFSET (8) /*!< Major device bit offset */
|
||||
|
@ -413,7 +413,11 @@ static void bta_hf_client_api_enable(tBTA_HF_CLIENT_DATA *p_data)
|
||||
|
||||
/* check if mSBC support enabled */
|
||||
if (bta_hf_client_version >= HFP_HF_VERSION_1_6) {
|
||||
#if (BTM_WBS_INCLUDED == TRUE)
|
||||
bta_hf_client_cb.msbc_enabled = TRUE;
|
||||
#else
|
||||
bta_hf_client_cb.msbc_enabled = FALSE;
|
||||
#endif
|
||||
} else{
|
||||
bta_hf_client_cb.msbc_enabled = FALSE;
|
||||
}
|
||||
|
@ -36,6 +36,7 @@
|
||||
#define BTA_UTL_CLR_COD_SERVICE_CLASS 0x04
|
||||
#define BTA_UTL_SET_COD_ALL 0x08 /* take service class as the input (may clear some set bits!!) */
|
||||
#define BTA_UTL_INIT_COD 0x0a
|
||||
#define BTA_UTL_SET_COD_RESERVED_2 0x10 /* overwrite the two least significant bits reserved_2 */
|
||||
|
||||
/*****************************************************************************
|
||||
** Type Definitions
|
||||
@ -43,6 +44,7 @@
|
||||
|
||||
/** for utl_set_device_class() **/
|
||||
typedef struct {
|
||||
UINT8 reserved_2;
|
||||
UINT8 minor;
|
||||
UINT8 major;
|
||||
UINT16 service;
|
||||
@ -125,11 +127,12 @@ extern void utl_freebuf(void **p);
|
||||
** p_cod - Pointer to the device class to set to
|
||||
**
|
||||
** cmd - the fields of the device class to update.
|
||||
** BTA_UTL_SET_COD_RESERVED_2 - overwrite the two least significant bits reserved_2
|
||||
** BTA_UTL_SET_COD_MAJOR_MINOR, - overwrite major, minor class
|
||||
** BTA_UTL_SET_COD_SERVICE_CLASS - set the bits in the input
|
||||
** BTA_UTL_CLR_COD_SERVICE_CLASS - clear the bits in the input
|
||||
** BTA_UTL_SET_COD_ALL - overwrite major, minor, set the bits in service class
|
||||
** BTA_UTL_INIT_COD - overwrite major, minor, and service class
|
||||
** BTA_UTL_SET_COD_ALL - overwrite major, minor, set the bits in service class, reserved_2 remain unchanged
|
||||
** BTA_UTL_INIT_COD - overwrite major, minor, and service class, reserved_2 remain unchanged
|
||||
**
|
||||
** Returns TRUE if successful, Otherwise FALSE
|
||||
**
|
||||
|
@ -170,11 +170,12 @@ void utl_freebuf(void **p)
|
||||
** p_cod - Pointer to the device class to set to
|
||||
**
|
||||
** cmd - the fields of the device class to update.
|
||||
** BTA_UTL_SET_COD_RESERVED_2 - overwrite the two least significant bits reserved_2
|
||||
** BTA_UTL_SET_COD_MAJOR_MINOR, - overwrite major, minor class
|
||||
** BTA_UTL_SET_COD_SERVICE_CLASS - set the bits in the input
|
||||
** BTA_UTL_CLR_COD_SERVICE_CLASS - clear the bits in the input
|
||||
** BTA_UTL_SET_COD_ALL - overwrite major, minor, set the bits in service class
|
||||
** BTA_UTL_INIT_COD - overwrite major, minor, and service class
|
||||
** BTA_UTL_SET_COD_ALL - overwrite major, minor, set the bits in service class, reserved_2 remain unchanged
|
||||
** BTA_UTL_INIT_COD - overwrite major, minor, and service class, reserved_2 remain unchanged
|
||||
**
|
||||
** Returns TRUE if successful, Otherwise FALSE
|
||||
**
|
||||
@ -183,15 +184,19 @@ BOOLEAN utl_set_device_class(tBTA_UTL_COD *p_cod, UINT8 cmd)
|
||||
{
|
||||
UINT8 *dev;
|
||||
UINT16 service;
|
||||
UINT8 minor, major;
|
||||
UINT8 minor, major, reserved_2;
|
||||
DEV_CLASS dev_class;
|
||||
|
||||
dev = BTM_ReadDeviceClass();
|
||||
BTM_COD_SERVICE_CLASS( service, dev );
|
||||
BTM_COD_MINOR_CLASS(minor, dev );
|
||||
BTM_COD_MAJOR_CLASS(major, dev );
|
||||
BTM_COD_RESERVED_2(reserved_2, dev);
|
||||
|
||||
switch (cmd) {
|
||||
case BTA_UTL_SET_COD_RESERVED_2:
|
||||
reserved_2 = p_cod->reserved_2 & BTM_COD_RESERVED_2_MASK;
|
||||
break;
|
||||
case BTA_UTL_SET_COD_MAJOR_MINOR:
|
||||
minor = p_cod->minor & BTM_COD_MINOR_CLASS_MASK;
|
||||
major = p_cod->major & BTM_COD_MAJOR_CLASS_MASK;
|
||||
@ -226,7 +231,7 @@ BOOLEAN utl_set_device_class(tBTA_UTL_COD *p_cod, UINT8 cmd)
|
||||
}
|
||||
|
||||
/* convert the fields into the device class type */
|
||||
FIELDS_TO_COD(dev_class, minor, major, service);
|
||||
FIELDS_TO_COD(dev_class, reserved_2, minor, major, service);
|
||||
|
||||
if (BTM_SetDeviceClass(dev_class) == BTM_SUCCESS) {
|
||||
return TRUE;
|
||||
@ -252,16 +257,18 @@ BOOLEAN utl_get_device_class(tBTA_UTL_COD *p_cod)
|
||||
{
|
||||
UINT8 *dev;
|
||||
UINT16 service;
|
||||
UINT8 minor, major;
|
||||
UINT8 minor, major, reserved_2;
|
||||
|
||||
dev = BTM_ReadDeviceClass();
|
||||
BTM_COD_SERVICE_CLASS( service, dev );
|
||||
BTM_COD_MINOR_CLASS(minor, dev );
|
||||
BTM_COD_MAJOR_CLASS(major, dev );
|
||||
BTM_COD_RESERVED_2(reserved_2, dev );
|
||||
|
||||
p_cod->minor = minor;
|
||||
p_cod->major = major;
|
||||
p_cod->service = service;
|
||||
p_cod->reserved_2 = reserved_2;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
@ -585,6 +585,7 @@ static void btc_gap_bt_set_cod(btc_gap_bt_args_t *arg)
|
||||
{
|
||||
tBTA_UTL_COD p_cod;
|
||||
esp_bt_cod_t *cod = &(arg->set_cod.cod);
|
||||
p_cod.reserved_2 = cod->reserved_2;
|
||||
p_cod.minor = cod->minor << 2;
|
||||
p_cod.major = cod->major;
|
||||
p_cod.service = cod->service << 5;
|
||||
@ -602,6 +603,7 @@ esp_err_t btc_gap_bt_get_cod(esp_bt_cod_t *cod)
|
||||
BTC_TRACE_ERROR("%s get class of device failed!",__func__);
|
||||
return ESP_BT_STATUS_FAIL;
|
||||
}
|
||||
cod->reserved_2 = p_cod.reserved_2;
|
||||
cod->minor = p_cod.minor >> 2;
|
||||
cod->major = p_cod.major;
|
||||
cod->service = p_cod.service >> 5;
|
||||
|
@ -2101,7 +2101,7 @@ BOOLEAN BTM_BleGetCurrentAddress(BD_ADDR addr, uint8_t *addr_type)
|
||||
** Returns pointer of ADV data
|
||||
**
|
||||
*******************************************************************************/
|
||||
UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT8 type, UINT8 *p_length)
|
||||
UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT16 adv_data_len, UINT8 type, UINT8 *p_length)
|
||||
{
|
||||
UINT8 *p = p_adv;
|
||||
UINT8 length;
|
||||
@ -2110,7 +2110,7 @@ UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT8 type, UINT8 *p_length)
|
||||
|
||||
STREAM_TO_UINT8(length, p);
|
||||
|
||||
while ( length && (p - p_adv < BTM_BLE_CACHE_ADV_DATA_MAX)) {
|
||||
while ( length && (p - p_adv < adv_data_len)) {
|
||||
STREAM_TO_UINT8(adv_type, p);
|
||||
|
||||
if ( adv_type == type ) {
|
||||
@ -2123,7 +2123,7 @@ UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT8 type, UINT8 *p_length)
|
||||
|
||||
/* Break loop if advertising data is in an incorrect format,
|
||||
as it may lead to memory overflow */
|
||||
if (p >= p_adv + BTM_BLE_CACHE_ADV_DATA_MAX) {
|
||||
if (p >= p_adv + adv_data_len) {
|
||||
break;
|
||||
}
|
||||
|
||||
@ -3176,7 +3176,7 @@ UINT8 btm_ble_is_discoverable(BD_ADDR bda, UINT8 evt_type, UINT8 *p)
|
||||
}
|
||||
|
||||
if (p_le_inq_cb->adv_len != 0) {
|
||||
if ((p_flag = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache,
|
||||
if ((p_flag = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache, p_le_inq_cb->adv_len,
|
||||
BTM_BLE_AD_TYPE_FLAG, &data_len)) != NULL) {
|
||||
flag = * p_flag;
|
||||
|
||||
@ -3392,7 +3392,7 @@ BOOLEAN btm_ble_update_inq_result(BD_ADDR bda, tINQ_DB_ENT *p_i, UINT8 addr_type
|
||||
p_i->inq_count = p_inq->inq_counter; /* Mark entry for current inquiry */
|
||||
|
||||
if (p_le_inq_cb->adv_len != 0) {
|
||||
if ((p_flag = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache, BTM_BLE_AD_TYPE_FLAG, &len)) != NULL) {
|
||||
if ((p_flag = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache, p_le_inq_cb->adv_len, BTM_BLE_AD_TYPE_FLAG, &len)) != NULL) {
|
||||
p_cur->flag = * p_flag;
|
||||
}
|
||||
}
|
||||
@ -3402,11 +3402,11 @@ BOOLEAN btm_ble_update_inq_result(BD_ADDR bda, tINQ_DB_ENT *p_i, UINT8 addr_type
|
||||
* then try to convert the appearance value to a class of device value Bluedroid can use.
|
||||
* Otherwise fall back to trying to infer if it is a HID device based on the service class.
|
||||
*/
|
||||
p_uuid16 = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache, BTM_BLE_AD_TYPE_APPEARANCE, &len);
|
||||
p_uuid16 = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache, p_le_inq_cb->adv_len, BTM_BLE_AD_TYPE_APPEARANCE, &len);
|
||||
if (p_uuid16 && len == 2) {
|
||||
btm_ble_appearance_to_cod((UINT16)p_uuid16[0] | (p_uuid16[1] << 8), p_cur->dev_class);
|
||||
} else {
|
||||
if ((p_uuid16 = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache,
|
||||
if ((p_uuid16 = BTM_CheckAdvData(p_le_inq_cb->adv_data_cache, p_le_inq_cb->adv_len,
|
||||
BTM_BLE_AD_TYPE_16SRV_CMPL, &len)) != NULL) {
|
||||
UINT8 i;
|
||||
for (i = 0; i + 2 <= len; i = i + 2) {
|
||||
@ -3493,10 +3493,10 @@ void btm_send_sel_conn_callback(BD_ADDR remote_bda, UINT8 evt_type, UINT8 *p_dat
|
||||
|
||||
/* get the device name if exist in ADV data */
|
||||
if (data_len != 0) {
|
||||
p_dev_name = BTM_CheckAdvData(p_data, BTM_BLE_AD_TYPE_NAME_CMPL, &len);
|
||||
p_dev_name = BTM_CheckAdvData(p_data, data_len, BTM_BLE_AD_TYPE_NAME_CMPL, &len);
|
||||
|
||||
if (p_dev_name == NULL) {
|
||||
p_dev_name = BTM_CheckAdvData(p_data, BTM_BLE_AD_TYPE_NAME_SHORT, &len);
|
||||
p_dev_name = BTM_CheckAdvData(p_data, data_len, BTM_BLE_AD_TYPE_NAME_SHORT, &len);
|
||||
}
|
||||
|
||||
if (p_dev_name) {
|
||||
|
@ -163,7 +163,7 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter
|
||||
UINT8 scan_mode = 0;
|
||||
UINT16 service_class;
|
||||
UINT8 *p_cod;
|
||||
UINT8 major, minor;
|
||||
UINT8 major, minor, reserved_2;
|
||||
DEV_CLASS cod;
|
||||
LAP temp_lap[2];
|
||||
BOOLEAN is_limited;
|
||||
@ -255,13 +255,14 @@ tBTM_STATUS BTM_SetDiscoverability (UINT16 inq_mode, UINT16 window, UINT16 inter
|
||||
if (is_limited ^ cod_limited) {
|
||||
BTM_COD_MINOR_CLASS(minor, p_cod );
|
||||
BTM_COD_MAJOR_CLASS(major, p_cod );
|
||||
BTM_COD_RESERVED_2(reserved_2, p_cod);
|
||||
if (is_limited) {
|
||||
service_class |= BTM_COD_SERVICE_LMTD_DISCOVER;
|
||||
} else {
|
||||
service_class &= ~BTM_COD_SERVICE_LMTD_DISCOVER;
|
||||
}
|
||||
|
||||
FIELDS_TO_COD(cod, minor, major, service_class);
|
||||
FIELDS_TO_COD(cod, reserved_2, minor, major, service_class);
|
||||
(void) BTM_SetDeviceClass (cod);
|
||||
}
|
||||
|
||||
@ -515,7 +516,7 @@ tBTM_STATUS BTM_SetPeriodicInquiryMode (tBTM_INQ_PARMS *p_inqparms, UINT16 max_d
|
||||
|
||||
/* Before beginning the inquiry the current filter must be cleared, so initiate the command */
|
||||
if ((status = btm_set_inq_event_filter (p_inqparms->filter_cond_type, &p_inqparms->filter_cond)) != BTM_CMD_STARTED) {
|
||||
/* If set filter command is not succesful reset the state */
|
||||
/* If set filter command is not successful reset the state */
|
||||
p_inq->p_inq_results_cb = NULL;
|
||||
p_inq->state = BTM_INQ_INACTIVE_STATE;
|
||||
|
||||
@ -688,7 +689,7 @@ UINT16 BTM_ReadConnectability (UINT16 *p_window, UINT16 *p_interval)
|
||||
** Description This function returns a bit mask of the current inquiry state
|
||||
**
|
||||
** Returns BTM_INQUIRY_INACTIVE if inactive (0)
|
||||
** BTM_LIMITED_INQUIRY_ACTIVE if a limted inquiry is active
|
||||
** BTM_LIMITED_INQUIRY_ACTIVE if a limited inquiry is active
|
||||
** BTM_GENERAL_INQUIRY_ACTIVE if a general inquiry is active
|
||||
** BTM_PERIODIC_INQUIRY_ACTIVE if a periodic inquiry is active
|
||||
**
|
||||
@ -783,7 +784,7 @@ tBTM_STATUS BTM_CancelInquiry(void)
|
||||
** Description This function is called to start an inquiry.
|
||||
**
|
||||
** Parameters: p_inqparms - pointer to the inquiry information
|
||||
** mode - GENERAL or LIMITED inquiry, BR/LE bit mask seperately
|
||||
** mode - GENERAL or LIMITED inquiry, BR/LE bit mask separately
|
||||
** duration - length in 1.28 sec intervals (If '0', the inquiry is CANCELLED)
|
||||
** max_resps - maximum amount of devices to search for before ending the inquiry
|
||||
** filter_cond_type - BTM_CLR_INQUIRY_FILTER, BTM_FILTER_COND_DEVICE_CLASS, or
|
||||
@ -1858,7 +1859,7 @@ void btm_process_inq_results (UINT8 *p, UINT8 inq_res_mode)
|
||||
#if BLE_INCLUDED == TRUE
|
||||
/* new device response */
|
||||
&& ( p_i == NULL ||
|
||||
/* exisiting device with BR/EDR info */
|
||||
/* existing device with BR/EDR info */
|
||||
(p_i && (p_i->inq_info.results.device_type & BT_DEVICE_TYPE_BREDR) != 0)
|
||||
)
|
||||
#endif
|
||||
|
@ -2162,7 +2162,9 @@ static void btu_ble_ext_adv_report_evt(UINT8 *p, UINT16 evt_len)
|
||||
{
|
||||
tBTM_BLE_EXT_ADV_REPORT ext_adv_report = {0};
|
||||
UINT8 num_reports = {0};
|
||||
#if (defined BLE_PRIVACY_SPT && BLE_PRIVACY_SPT == TRUE)
|
||||
UINT8 *pp = p;
|
||||
#endif
|
||||
//UINT8 legacy_event_type = 0;
|
||||
UINT16 evt_type = 0;
|
||||
uint8_t addr_type;
|
||||
|
@ -457,22 +457,22 @@ typedef enum {
|
||||
#define BTM_COD_SERVICE_INFORMATION 0x8000
|
||||
|
||||
/* class of device field macros */
|
||||
#define BTM_COD_FORMAT_TYPE(u8, pd) {u8 = pd[2]&0x03;}
|
||||
#define BTM_COD_RESERVED_2(u8, pd) {u8 = pd[2]&0x03;}
|
||||
#define BTM_COD_MINOR_CLASS(u8, pd) {u8 = pd[2]&0xFC;}
|
||||
#define BTM_COD_MAJOR_CLASS(u8, pd) {u8 = pd[1]&0x1F;}
|
||||
#define BTM_COD_SERVICE_CLASS(u16, pd) {u16 = pd[0]; u16<<=8; u16 += pd[1]&0xE0;}
|
||||
|
||||
/* to set the fields (assumes that format type is always 0) */
|
||||
#define FIELDS_TO_COD(pd, mn, mj, sv) {pd[2] = mn; pd[1] = \
|
||||
mj+ ((sv)&BTM_COD_SERVICE_CLASS_LO_B); \
|
||||
#define FIELDS_TO_COD(pd, rs, mn, mj, sv) {pd[2] = (mn & BTM_COD_MINOR_CLASS_MASK) + (rs & BTM_COD_RESERVED_2_MASK); \
|
||||
pd[1] = mj+ ((sv)&BTM_COD_SERVICE_CLASS_LO_B); \
|
||||
pd[0] = (sv) >> 8;}
|
||||
|
||||
/* the COD masks */
|
||||
#define BTM_COD_FORMAT_TYPE_MASK 0x03
|
||||
#define BTM_COD_MINOR_CLASS_MASK 0xFC
|
||||
#define BTM_COD_MAJOR_CLASS_MASK 0x1F
|
||||
#define BTM_COD_SERVICE_CLASS_LO_B 0x00E0
|
||||
#define BTM_COD_SERVICE_CLASS_MASK 0xFFE0
|
||||
#define BTM_COD_RESERVED_2_MASK 0x03
|
||||
|
||||
/* BTM service definitions
|
||||
** Used for storing EIR data to bit mask
|
||||
|
@ -2112,7 +2112,7 @@ void BTM_BleReadControllerFeatures(tBTM_BLE_CTRL_FEATURES_CBACK *p_vsc_cback);
|
||||
**
|
||||
*******************************************************************************/
|
||||
//extern
|
||||
UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT8 type, UINT8 *p_length);
|
||||
UINT8 *BTM_CheckAdvData( UINT8 *p_adv, UINT16 adv_data_len, UINT8 type, UINT8 *p_length);
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
|
@ -940,6 +940,12 @@ config BT_NIMBLE_HIGH_DUTY_ADV_ITVL
|
||||
help
|
||||
This enable BLE high duty advertising interval feature
|
||||
|
||||
config BT_NIMBLE_HOST_ALLOW_CONNECT_WITH_SCAN
|
||||
bool "Allow Connections with scanning in progress"
|
||||
depends on BT_NIMBLE_ENABLED && (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3)
|
||||
help
|
||||
This enables support for user to initiate a new connection with scan in progress
|
||||
|
||||
config BT_NIMBLE_HOST_QUEUE_CONG_CHECK
|
||||
bool "BLE queue congestion check"
|
||||
depends on BT_NIMBLE_ENABLED
|
||||
|
@ -1 +1 @@
|
||||
Subproject commit d47cb44f245919fcf776c5ee094ec60f28b43fce
|
||||
Subproject commit d1f02191a1b17673ee0f539514f50d2e5fdc7863
|
@ -1824,7 +1824,7 @@
|
||||
#ifdef CONFIG_BT_NIMBLE_HOST_QUEUE_CONG_CHECK
|
||||
#define MYNEWT_VAL_BLE_QUEUE_CONG_CHECK CONFIG_BT_NIMBLE_HOST_QUEUE_CONG_CHECK
|
||||
#else
|
||||
#define MYNEWT_VAL_BLE_QUEUE_CONG_CHECK FALSE
|
||||
#define MYNEWT_VAL_BLE_QUEUE_CONG_CHECK (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -1844,6 +1844,22 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef MYNEWT_VAL_BLE_HOST_ALLOW_CONNECT_WITH_SCAN
|
||||
#ifdef CONFIG_BT_NIMBLE_HOST_ALLOW_CONNECT_WITH_SCAN
|
||||
#define MYNEWT_VAL_BLE_HOST_ALLOW_CONNECT_WITH_SCAN CONFIG_BT_NIMBLE_HOST_ALLOW_CONNECT_WITH_SCAN
|
||||
#else
|
||||
#define MYNEWT_VAL_BLE_HOST_ALLOW_CONNECT_WITH_SCAN (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef MYNEWT_VAL_BT_HCI_LOG_INCLUDED
|
||||
#ifdef CONFIG_BT_HCI_LOG_DEBUG_EN
|
||||
#define MYNEWT_VAL_BT_HCI_LOG_INCLUDED CONFIG_BT_HCI_LOG_DEBUG_EN
|
||||
#else
|
||||
#define MYNEWT_VAL_BT_HCI_LOG_INCLUDED (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if CONFIG_BT_CONTROLLER_DISABLED && CONFIG_BT_NIMBLE_TRANSPORT_UART
|
||||
#ifndef MYNEWT_VAL_BLE_TRANSPORT_UART_PORT
|
||||
#define MYNEWT_VAL_BLE_TRANSPORT_UART_PORT CONFIG_BT_NIMBLE_TRANSPORT_UART_PORT
|
||||
@ -1877,4 +1893,6 @@
|
||||
#define MYNEWT_VAL_BLE_TRANSPORT_UART_STOP_BITS (1)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
@ -16,6 +16,7 @@
|
||||
#include "nimble/nimble_npl.h"
|
||||
#include "../../../../controller/esp32c2/esp_bt_cfg.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
|
||||
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
#include "driver/uart.h"
|
||||
@ -428,6 +429,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr);
|
||||
void esp_ble_controller_log_dump_all(bool output);
|
||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||
|
||||
#if CONFIG_PM_ENABLE
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void);
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src);
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -16,6 +16,7 @@
|
||||
#include "nimble/nimble_npl.h"
|
||||
#include "../../../../controller/esp32c5/esp_bt_cfg.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
|
||||
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
#include "driver/uart.h"
|
||||
@ -415,6 +416,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr);
|
||||
void esp_ble_controller_log_dump_all(bool output);
|
||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||
|
||||
#if CONFIG_PM_ENABLE
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void);
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src);
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -16,6 +16,7 @@
|
||||
#include "nimble/nimble_npl.h"
|
||||
#include "../../../../controller/esp32c6/esp_bt_cfg.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
|
||||
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
#include "driver/uart.h"
|
||||
@ -414,6 +415,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr);
|
||||
void esp_ble_controller_log_dump_all(bool output);
|
||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||
|
||||
#if CONFIG_PM_ENABLE
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void);
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src);
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -15,6 +15,7 @@
|
||||
|
||||
#include "nimble/nimble_npl.h"
|
||||
#include "../../../../controller/esp32h2/esp_bt_cfg.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
|
||||
#ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
|
||||
#include "driver/uart.h"
|
||||
@ -418,6 +419,12 @@ extern int esp_ble_hw_get_static_addr(esp_ble_addr_t *addr);
|
||||
void esp_ble_controller_log_dump_all(bool output);
|
||||
#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
|
||||
|
||||
#if CONFIG_PM_ENABLE
|
||||
modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void);
|
||||
|
||||
void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src);
|
||||
#endif // CONFIG_PM_ENABLE
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -444,13 +444,13 @@ static void hci_driver_uart_dma_install(void)
|
||||
.direction = GDMA_CHANNEL_DIRECTION_TX,
|
||||
};
|
||||
|
||||
ESP_ERROR_CHECK(gdma_new_channel(&tx_channel_config, &s_tx_channel));
|
||||
ESP_ERROR_CHECK(gdma_new_ahb_channel(&tx_channel_config, &s_tx_channel));
|
||||
gdma_channel_alloc_config_t rx_channel_config = {
|
||||
.direction = GDMA_CHANNEL_DIRECTION_RX,
|
||||
.sibling_chan = s_tx_channel,
|
||||
};
|
||||
|
||||
ESP_ERROR_CHECK(gdma_new_channel(&rx_channel_config, &s_rx_channel));
|
||||
ESP_ERROR_CHECK(gdma_new_ahb_channel(&rx_channel_config, &s_rx_channel));
|
||||
gdma_connect(s_tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0));
|
||||
gdma_connect(s_rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UHCI, 0));
|
||||
gdma_strategy_config_t strategy_config = {
|
||||
|
@ -139,6 +139,10 @@ esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
|
||||
void
|
||||
esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
|
||||
{
|
||||
if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
||||
return;
|
||||
}
|
||||
|
||||
hci_driver_vhci_tx(data[0], data, len, HCI_DRIVER_DIR_H2C);
|
||||
}
|
||||
|
||||
|
@ -14,6 +14,7 @@ extern "C" {
|
||||
#include "esp_heap_caps.h"
|
||||
#include "esp_err.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "soc/uart_channel.h"
|
||||
|
||||
// Forward declaration. Definition in linenoise/linenoise.h.
|
||||
typedef struct linenoiseCompletions linenoiseCompletions;
|
||||
@ -88,8 +89,8 @@ typedef struct {
|
||||
{ \
|
||||
.channel = CONFIG_ESP_CONSOLE_UART_NUM, \
|
||||
.baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \
|
||||
.tx_gpio_num = CONFIG_ESP_CONSOLE_UART_TX_GPIO, \
|
||||
.rx_gpio_num = CONFIG_ESP_CONSOLE_UART_RX_GPIO, \
|
||||
.tx_gpio_num = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : UART_NUM_0_TXD_DIRECT_GPIO_NUM, \
|
||||
.rx_gpio_num = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : UART_NUM_0_RXD_DIRECT_GPIO_NUM, \
|
||||
}
|
||||
#else
|
||||
#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \
|
||||
|
@ -290,7 +290,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
|
||||
gdma_channel_alloc_config_t rx_alloc_config = {
|
||||
.direction = GDMA_CHANNEL_DIRECTION_RX,
|
||||
};
|
||||
ret = gdma_new_channel(&rx_alloc_config, &s_adc_digi_ctx->rx_dma_channel);
|
||||
ret = gdma_new_ahb_channel(&rx_alloc_config, &s_adc_digi_ctx->rx_dma_channel);
|
||||
if (ret != ESP_OK) {
|
||||
goto cleanup;
|
||||
}
|
||||
|
@ -371,7 +371,7 @@ static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
|
||||
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
|
||||
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_TX;
|
||||
/* Register a new GDMA tx channel */
|
||||
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error");
|
||||
ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error");
|
||||
ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->tx_dma_chan, trig), TAG, "Connect tx dma channel error");
|
||||
gdma_tx_event_callbacks_t cb = {.on_trans_eof = i2s_dma_tx_callback};
|
||||
/* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
|
||||
@ -380,7 +380,7 @@ static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
|
||||
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
|
||||
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_RX;
|
||||
/* Register a new GDMA rx channel */
|
||||
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error");
|
||||
ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error");
|
||||
ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->rx_dma_chan, trig), TAG, "Connect rx dma channel error");
|
||||
gdma_rx_event_callbacks_t cb = {.on_recv_eof = i2s_dma_rx_callback};
|
||||
/* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
|
||||
|
@ -30,13 +30,7 @@ components/driver/test_apps/legacy_adc_driver:
|
||||
|
||||
components/driver/test_apps/legacy_i2c_driver:
|
||||
disable:
|
||||
- if: IDF_TARGET in ["esp32c5", "esp32c61"]
|
||||
temporary: true
|
||||
reason: not support yet # TODO: [ESP32C5] IDF-10307, [ESP32C61] IDF-9296
|
||||
disable_test:
|
||||
- if: IDF_TARGET == "esp32p4"
|
||||
temporary: true
|
||||
reason: lack of runner
|
||||
- if: SOC_I2C_SUPPORTED != 1
|
||||
depends_filepatterns:
|
||||
- components/driver/i2c/**
|
||||
# Following dependency is needed because they might increase lazy installed memory
|
||||
|
@ -99,7 +99,7 @@
|
||||
#define TEST_DMA_CHAN_MASTER GET_DMA_CHAN(TEST_SPI_HOST)
|
||||
#define TEST_DMA_CHAN_SLAVE GET_DMA_CHAN(TEST_SLAVE_HOST)
|
||||
|
||||
#define FUNC_SPI 1
|
||||
#define FUNC_SPI SPI2_FUNC_NUM
|
||||
#define FUNC_GPIO PIN_FUNC_GPIO
|
||||
|
||||
//Delay information
|
||||
|
@ -1,2 +1,2 @@
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
|
@ -23,6 +23,7 @@
|
||||
#include "hal/i2c_types.h"
|
||||
#include "soc/uart_periph.h"
|
||||
#include "test_utils.h"
|
||||
#include "esp_private/gpio.h"
|
||||
|
||||
#define DATA_LENGTH 512 /*!<Data buffer length for test buffer*/
|
||||
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
|
||||
@ -675,7 +676,7 @@ TEST_CASE("I2C general API test", "[i2c]")
|
||||
//Init uart baud rate detection
|
||||
static void uart_aut_baud_det_init(int rxd_io_num)
|
||||
{
|
||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rxd_io_num], PIN_FUNC_GPIO);
|
||||
gpio_func_sel(rxd_io_num, PIN_FUNC_GPIO);
|
||||
gpio_set_direction(rxd_io_num, GPIO_MODE_INPUT_OUTPUT);
|
||||
esp_rom_gpio_connect_out_signal(rxd_io_num, i2c_periph_signal[0].scl_out_sig, 0, 0);
|
||||
esp_rom_gpio_connect_in_signal(rxd_io_num, UART_PERIPH_SIGNAL(1, SOC_UART_RX_PIN_IDX), 0);
|
||||
|
@ -5,7 +5,6 @@ from pytest_embedded import Dut
|
||||
|
||||
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5'], reason='esp32p4 support TBD, C5 failed') # TODO: IDF-8960, [ESP32C5] IDF-10307
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
@ -22,7 +21,9 @@ def test_i2c_legacy(dut: Dut) -> None:
|
||||
@pytest.mark.esp32
|
||||
@pytest.mark.esp32c3
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.esp32s2
|
||||
@pytest.mark.esp32s3
|
||||
@pytest.mark.generic_multi_device
|
||||
|
@ -1,2 +1,2 @@
|
||||
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
|
@ -11,6 +11,7 @@ from pytest_embedded import Dut
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.esp32c5
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize('config', [
|
||||
'release',
|
||||
|
@ -49,9 +49,8 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
|
||||
|
||||
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8727
|
||||
abort();
|
||||
// Currently calibration is not supported on ESP32-C5, IDF-5236
|
||||
// Allow no calibration
|
||||
*tsens_cal = 0;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
@ -9,7 +9,7 @@
|
||||
#include <assert.h>
|
||||
#include "esp_efuse_table.h"
|
||||
|
||||
// md5_digest_table eb005412b657c9be0ce4bb699e5813c9
|
||||
// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -23,6 +23,34 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
|
||||
{EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_RND_SWITCH_CYCLE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_XTS_KEY_LENGTH_256[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_XTS_KEY_LENGTH_256,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE,
|
||||
};
|
||||
@ -35,6 +63,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI,
|
||||
};
|
||||
@ -51,6 +83,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
|
||||
{EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL,
|
||||
};
|
||||
@ -99,6 +135,22 @@ static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ECDSA_DISABLE_P192[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECDSA_DISABLE_P192,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
|
||||
{EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
|
||||
};
|
||||
@ -107,8 +159,12 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
|
||||
{EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
{EFUSE_BLK0, 17, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
|
||||
static const esp_efuse_desc_t WR_DIS_XTAL_48M_SEL[] = {
|
||||
{EFUSE_BLK0, 17, 1}, // [] wr_dis of XTAL_48M_SEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_XTAL_48M_SEL_MODE[] = {
|
||||
{EFUSE_BLK0, 17, 1}, // [] wr_dis of XTAL_48M_SEL_MODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
|
||||
@ -148,7 +204,11 @@ static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
|
||||
{EFUSE_BLK0, 19, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = {
|
||||
{EFUSE_BLK0, 19, 1}, // [] wr_dis of HUK_GEN_STATE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLK1[] = {
|
||||
@ -163,12 +223,76 @@ static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_TEMP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PA_TRIM_VERSION[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PA_TRIM_VERSION,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_TRIM_N_BIAS[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TRIM_N_BIAS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_TRIM_P_BIAS[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TRIM_P_BIAS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK_SYS_DATA1,
|
||||
static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_OCODE[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
|
||||
@ -464,8 +588,72 @@ static const esp_efuse_desc_t MAC_EXT[] = {
|
||||
{EFUSE_BLK1, 48, 16}, // [] Represents the extended bits of MAC address,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = {
|
||||
{EFUSE_BLK2, 0, 256}, // [] System data part 1 (reserved),
|
||||
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
|
||||
{EFUSE_BLK1, 64, 4}, // [] Minor chip version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 68, 2}, // [] Minor chip version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
|
||||
{EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_CAP[] = {
|
||||
{EFUSE_BLK1, 77, 3}, // [] Flash capacity,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_VENDOR[] = {
|
||||
{EFUSE_BLK1, 80, 3}, // [] Flash vendor,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_CAP[] = {
|
||||
{EFUSE_BLK1, 83, 3}, // [] Psram capacity,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_VENDOR[] = {
|
||||
{EFUSE_BLK1, 86, 2}, // [] Psram vendor,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t TEMP[] = {
|
||||
{EFUSE_BLK1, 88, 2}, // [] Temp (die embedded inside),
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PKG_VERSION[] = {
|
||||
{EFUSE_BLK1, 90, 3}, // [] Package version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PA_TRIM_VERSION[] = {
|
||||
{EFUSE_BLK1, 93, 3}, // [] PADC CAL PA trim version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t TRIM_N_BIAS[] = {
|
||||
{EFUSE_BLK1, 96, 5}, // [] PADC CAL N bias,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t TRIM_P_BIAS[] = {
|
||||
{EFUSE_BLK1, 101, 5}, // [] PADC CAL P bias,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
|
||||
{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t OCODE[] = {
|
||||
{EFUSE_BLK2, 137, 8}, // [] ADC OCode,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t USER_DATA[] = {
|
||||
@ -518,6 +706,41 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = {
|
||||
&WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = {
|
||||
&WR_DIS_KM_RND_SWITCH_CYCLE[0], // [] wr_dis of KM_RND_SWITCH_CYCLE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = {
|
||||
&WR_DIS_KM_DEPLOY_ONLY_ONCE[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = {
|
||||
&WR_DIS_FORCE_USE_KEY_MANAGER_KEY[0], // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = {
|
||||
&WR_DIS_FORCE_DISABLE_SW_INIT_KEY[0], // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[] = {
|
||||
&WR_DIS_KM_XTS_KEY_LENGTH_256[0], // [] wr_dis of KM_XTS_KEY_LENGTH_256
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = {
|
||||
&WR_DIS_LOCK_KM_KEY[0], // [] wr_dis of LOCK_KM_KEY
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = {
|
||||
&WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE
|
||||
NULL
|
||||
@ -533,6 +756,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
&WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = {
|
||||
&WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI
|
||||
NULL
|
||||
@ -553,6 +781,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = {
|
||||
&WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
|
||||
&WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL
|
||||
NULL
|
||||
@ -613,6 +846,26 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = {
|
||||
&WR_DIS_XTS_DPA_PSEUDO_LEVEL[0], // [] wr_dis of XTS_DPA_PSEUDO_LEVEL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = {
|
||||
&WR_DIS_XTS_DPA_CLK_ENABLE[0], // [] wr_dis of XTS_DPA_CLK_ENABLE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[] = {
|
||||
&WR_DIS_ECDSA_DISABLE_P192[0], // [] wr_dis of ECDSA_DISABLE_P192
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = {
|
||||
&WR_DIS_ECC_FORCE_CONST_TIME[0], // [] wr_dis of ECC_FORCE_CONST_TIME
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
|
||||
&WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN
|
||||
NULL
|
||||
@ -623,8 +876,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
&WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL[] = {
|
||||
&WR_DIS_XTAL_48M_SEL[0], // [] wr_dis of XTAL_48M_SEL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL_MODE[] = {
|
||||
&WR_DIS_XTAL_48M_SEL_MODE[0], // [] wr_dis of XTAL_48M_SEL_MODE
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -678,6 +936,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = {
|
||||
&WR_DIS_HUK_GEN_STATE[0], // [] wr_dis of HUK_GEN_STATE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
|
||||
&WR_DIS_BLK1[0], // [] wr_dis of BLOCK1
|
||||
NULL
|
||||
@ -693,13 +956,93 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
|
||||
&WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
|
||||
&WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
|
||||
&WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
&WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
|
||||
&WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
|
||||
&WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
|
||||
&WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
|
||||
&WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
|
||||
&WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = {
|
||||
&WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = {
|
||||
&WR_DIS_TEMP[0], // [] wr_dis of TEMP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
|
||||
&WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[] = {
|
||||
&WR_DIS_PA_TRIM_VERSION[0], // [] wr_dis of PA_TRIM_VERSION
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[] = {
|
||||
&WR_DIS_TRIM_N_BIAS[0], // [] wr_dis of TRIM_N_BIAS
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[] = {
|
||||
&WR_DIS_TRIM_P_BIAS[0], // [] wr_dis of TRIM_P_BIAS
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
|
||||
&WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = {
|
||||
&WR_DIS_BLOCK_SYS_DATA1[0], // [] wr_dis of BLOCK_SYS_DATA1
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
|
||||
&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
|
||||
&WR_DIS_OCODE[0], // [] wr_dis of OCODE
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1068,8 +1411,88 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = {
|
||||
&BLOCK_SYS_DATA1[0], // [] System data part 1 (reserved)
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
|
||||
&WAFER_VERSION_MINOR[0], // [] Minor chip version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
|
||||
&WAFER_VERSION_MAJOR[0], // [] Minor chip version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
|
||||
&DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
&DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
|
||||
&BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
|
||||
&BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
|
||||
&FLASH_CAP[0], // [] Flash capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
|
||||
&FLASH_VENDOR[0], // [] Flash vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
|
||||
&PSRAM_CAP[0], // [] Psram capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
|
||||
&PSRAM_VENDOR[0], // [] Psram vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
|
||||
&TEMP[0], // [] Temp (die embedded inside)
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
|
||||
&PKG_VERSION[0], // [] Package version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[] = {
|
||||
&PA_TRIM_VERSION[0], // [] PADC CAL PA trim version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[] = {
|
||||
&TRIM_N_BIAS[0], // [] PADC CAL N bias
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[] = {
|
||||
&TRIM_P_BIAS[0], // [] PADC CAL P bias
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
|
||||
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
|
||||
&OCODE[0], // [] ADC OCode
|
||||
NULL
|
||||
};
|
||||
|
||||
|
@ -9,17 +9,26 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 64acd55d57b7452dbb6838b7237c795b
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: b09fa417de505238a601eddce188b696
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
|
||||
WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE
|
||||
WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
|
||||
WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
|
||||
WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
|
||||
WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256
|
||||
WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI
|
||||
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
@ -32,9 +41,14 @@ WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.K
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
|
||||
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
|
||||
WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
|
||||
WR_DIS.ECDSA_DISABLE_P192, EFUSE_BLK0, 14, 1, [] wr_dis of ECDSA_DISABLE_P192
|
||||
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.XTAL_48M_SEL, EFUSE_BLK0, 17, 1, [] wr_dis of XTAL_48M_SEL
|
||||
WR_DIS.XTAL_48M_SEL_MODE, EFUSE_BLK0, 17, 1, [] wr_dis of XTAL_48M_SEL_MODE
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
|
||||
@ -44,12 +58,29 @@ WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT
|
||||
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
|
||||
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
|
||||
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
|
||||
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
|
||||
WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.PA_TRIM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PA_TRIM_VERSION
|
||||
WR_DIS.TRIM_N_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_N_BIAS
|
||||
WR_DIS.TRIM_P_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_P_BIAS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK_SYS_DATA1
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -127,7 +158,23 @@ MAC, EFUSE_BLK1, 40, 8, [MAC_FACT
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
MAC_EXT, EFUSE_BLK1, 48, 16, [] Represents the extended bits of MAC address
|
||||
BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [] System data part 1 (reserved)
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Minor chip version
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2
|
||||
FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity
|
||||
FLASH_VENDOR, EFUSE_BLK1, 80, 3, [] Flash vendor
|
||||
PSRAM_CAP, EFUSE_BLK1, 83, 3, [] Psram capacity
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] Psram vendor
|
||||
TEMP, EFUSE_BLK1, 88, 2, [] Temp (die embedded inside)
|
||||
PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version
|
||||
PA_TRIM_VERSION, EFUSE_BLK1, 93, 3, [] PADC CAL PA trim version
|
||||
TRIM_N_BIAS, EFUSE_BLK1, 96, 5, [] PADC CAL N bias
|
||||
TRIM_P_BIAS, EFUSE_BLK1, 101, 5, [] PADC CAL P bias
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table eb005412b657c9be0ce4bb699e5813c9
|
||||
// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -19,13 +19,22 @@ extern "C" {
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
@ -44,9 +53,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_P192[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTAL_48M_SEL_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
@ -57,12 +71,29 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -159,7 +190,23 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
|
@ -24,6 +24,7 @@ static __attribute__((unused)) const char *TAG = "efuse";
|
||||
uint32_t esp_efuse_get_pkg_ver(void)
|
||||
{
|
||||
uint32_t pkg_ver = 0;
|
||||
esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
|
||||
return pkg_ver;
|
||||
}
|
||||
|
||||
|
@ -9,7 +9,7 @@
|
||||
#include <assert.h>
|
||||
#include "esp_efuse_table.h"
|
||||
|
||||
// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381
|
||||
// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -23,6 +23,98 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
|
||||
{EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_RND_SWITCH_CYCLE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_XTS_KEY_LENGTH_256[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of XTS_KEY_LENGTH_256,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = {
|
||||
{EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of WDT_DELAY_SEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_0[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_0,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_1[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_1,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_2[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_3[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_3,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_WDT[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_WDT,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_SWD[] = {
|
||||
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_SWD,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL[] = {
|
||||
{EFUSE_BLK0, 3, 1}, // [] wr_dis of HP_PWR_SRC_SEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
|
||||
{EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT,
|
||||
};
|
||||
@ -63,10 +155,86 @@ static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
|
||||
{EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = {
|
||||
{EFUSE_BLK0, 14, 1}, // [] wr_dis of CRYPT_DPA_ENABLE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
|
||||
{EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
|
||||
{EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ECDSA_ENABLE_SOFT_K[] = {
|
||||
{EFUSE_BLK0, 17, 1}, // [] wr_dis of ECDSA_ENABLE_SOFT_K,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_TYPE[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_PAGE_SIZE[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_PAGE_SIZE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DIRECT_BOOT,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
|
||||
{EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_KM_HUK_GEN_STATE[] = {
|
||||
{EFUSE_BLK0, 19, 1}, // [] wr_dis of KM_HUK_GEN_STATE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLK1[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1,
|
||||
};
|
||||
@ -99,24 +267,12 @@ static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PSRAM_TEMP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_TEMP,
|
||||
static const esp_efuse_desc_t WR_DIS_TEMP[] = {
|
||||
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
|
||||
@ -171,6 +327,22 @@ static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
|
||||
{EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
|
||||
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_DEVICE_EXCHG_PINS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_USB_OTG11_EXCHG_PINS[] = {
|
||||
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_OTG11_EXCHG_PINS,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = {
|
||||
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_PHY_SEL,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
|
||||
{EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t RD_DIS[] = {
|
||||
{EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10,
|
||||
};
|
||||
@ -476,32 +648,20 @@ static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_CAP[] = {
|
||||
{EFUSE_BLK1, 77, 3}, // [] Flash capacity,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_TEMP[] = {
|
||||
{EFUSE_BLK1, 80, 2}, // [] Flash temperature,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_VENDOR[] = {
|
||||
{EFUSE_BLK1, 82, 3}, // [] Flash vendor,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_CAP[] = {
|
||||
{EFUSE_BLK1, 85, 2}, // [] PSRAM capacity,
|
||||
{EFUSE_BLK1, 77, 3}, // [] PSRAM capacity,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_TEMP[] = {
|
||||
{EFUSE_BLK1, 87, 2}, // [] PSRAM temperature,
|
||||
static const esp_efuse_desc_t TEMP[] = {
|
||||
{EFUSE_BLK1, 80, 2}, // [] Operating temperature of the ESP chip,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_VENDOR[] = {
|
||||
{EFUSE_BLK1, 89, 2}, // [] PSRAM vendor,
|
||||
{EFUSE_BLK1, 82, 2}, // [] PSRAM vendor,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PKG_VERSION[] = {
|
||||
{EFUSE_BLK1, 91, 3}, // [] Package version,
|
||||
{EFUSE_BLK1, 84, 3}, // [] Package version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
|
||||
@ -558,6 +718,121 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = {
|
||||
&WR_DIS_KM_RND_SWITCH_CYCLE[0], // [] wr_dis of KM_RND_SWITCH_CYCLE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = {
|
||||
&WR_DIS_KM_DEPLOY_ONLY_ONCE[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = {
|
||||
&WR_DIS_FORCE_USE_KEY_MANAGER_KEY[0], // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = {
|
||||
&WR_DIS_FORCE_DISABLE_SW_INIT_KEY[0], // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[] = {
|
||||
&WR_DIS_XTS_KEY_LENGTH_256[0], // [] wr_dis of XTS_KEY_LENGTH_256
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = {
|
||||
&WR_DIS_LOCK_KM_KEY[0], // [] wr_dis of LOCK_KM_KEY
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = {
|
||||
&WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = {
|
||||
&WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
|
||||
&WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
|
||||
&WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = {
|
||||
&WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = {
|
||||
&WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = {
|
||||
&WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
|
||||
&WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
|
||||
&WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = {
|
||||
&WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[] = {
|
||||
&WR_DIS_PXA0_TIEH_SEL_0[0], // [] wr_dis of PXA0_TIEH_SEL_0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[] = {
|
||||
&WR_DIS_PXA0_TIEH_SEL_1[0], // [] wr_dis of PXA0_TIEH_SEL_1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[] = {
|
||||
&WR_DIS_PXA0_TIEH_SEL_2[0], // [] wr_dis of PXA0_TIEH_SEL_2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[] = {
|
||||
&WR_DIS_PXA0_TIEH_SEL_3[0], // [] wr_dis of PXA0_TIEH_SEL_3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[] = {
|
||||
&WR_DIS_DIS_WDT[0], // [] wr_dis of DIS_WDT
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[] = {
|
||||
&WR_DIS_DIS_SWD[0], // [] wr_dis of DIS_SWD
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[] = {
|
||||
&WR_DIS_HP_PWR_SRC_SEL[0], // [] wr_dis of HP_PWR_SRC_SEL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
|
||||
&WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
NULL
|
||||
@ -608,11 +883,106 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
|
||||
&WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = {
|
||||
&WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
|
||||
&WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
|
||||
&WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[] = {
|
||||
&WR_DIS_ECDSA_ENABLE_SOFT_K[0], // [] wr_dis of ECDSA_ENABLE_SOFT_K
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[] = {
|
||||
&WR_DIS_FLASH_TYPE[0], // [] wr_dis of FLASH_TYPE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[] = {
|
||||
&WR_DIS_FLASH_PAGE_SIZE[0], // [] wr_dis of FLASH_PAGE_SIZE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = {
|
||||
&WR_DIS_FLASH_ECC_EN[0], // [] wr_dis of FLASH_ECC_EN
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = {
|
||||
&WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = {
|
||||
&WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = {
|
||||
&WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = {
|
||||
&WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
|
||||
&WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
|
||||
&WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
|
||||
&WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = {
|
||||
&WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = {
|
||||
&WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = {
|
||||
&WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
|
||||
&WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[] = {
|
||||
&WR_DIS_KM_HUK_GEN_STATE[0], // [] wr_dis of KM_HUK_GEN_STATE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
|
||||
&WR_DIS_BLK1[0], // [] wr_dis of BLOCK1
|
||||
NULL
|
||||
@ -653,28 +1023,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
|
||||
&WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = {
|
||||
&WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
|
||||
&WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
|
||||
&WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[] = {
|
||||
&WR_DIS_PSRAM_TEMP[0], // [] wr_dis of PSRAM_TEMP
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = {
|
||||
&WR_DIS_TEMP[0], // [] wr_dis of TEMP
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -743,6 +1098,26 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
|
||||
&WR_DIS_USB_DEVICE_EXCHG_PINS[0], // [] wr_dis of USB_DEVICE_EXCHG_PINS
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = {
|
||||
&WR_DIS_USB_OTG11_EXCHG_PINS[0], // [] wr_dis of USB_OTG11_EXCHG_PINS
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = {
|
||||
&WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
|
||||
&WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
|
||||
&RD_DIS[0], // [] Disable reading from BlOCK4-10
|
||||
NULL
|
||||
@ -1123,28 +1498,13 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
|
||||
&FLASH_CAP[0], // [] Flash capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = {
|
||||
&FLASH_TEMP[0], // [] Flash temperature
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
|
||||
&FLASH_VENDOR[0], // [] Flash vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
|
||||
&PSRAM_CAP[0], // [] PSRAM capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[] = {
|
||||
&PSRAM_TEMP[0], // [] PSRAM temperature
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
|
||||
&TEMP[0], // [] Operating temperature of the ESP chip
|
||||
NULL
|
||||
};
|
||||
|
||||
|
@ -9,10 +9,33 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 6b72374c237a3473c8832aadee437405
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: d4a48929387e281bd05db8cfb3a85f60
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE
|
||||
WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
|
||||
WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
|
||||
WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
|
||||
WR_DIS.XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of XTS_KEY_LENGTH_256
|
||||
WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY
|
||||
WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI
|
||||
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD
|
||||
WR_DIS.PXA0_TIEH_SEL_0, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_0
|
||||
WR_DIS.PXA0_TIEH_SEL_1, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_1
|
||||
WR_DIS.PXA0_TIEH_SEL_2, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_2
|
||||
WR_DIS.PXA0_TIEH_SEL_3, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_3
|
||||
WR_DIS.DIS_WDT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_WDT
|
||||
WR_DIS.DIS_SWD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_SWD
|
||||
WR_DIS.HP_PWR_SRC_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of HP_PWR_SRC_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
|
||||
@ -23,7 +46,26 @@ WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.K
|
||||
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
|
||||
WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.ECDSA_ENABLE_SOFT_K, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_ENABLE_SOFT_K
|
||||
WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE
|
||||
WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE
|
||||
WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN
|
||||
WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.KM_HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of KM_HUK_GEN_STATE
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
|
||||
@ -32,11 +74,8 @@ WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
|
||||
WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
|
||||
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
|
||||
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
|
||||
WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP
|
||||
WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
|
||||
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
@ -50,6 +89,10 @@ WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.K
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS
|
||||
WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG11_EXCHG_PINS
|
||||
WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL
|
||||
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||
@ -130,13 +173,10 @@ DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disabl
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2
|
||||
FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity
|
||||
FLASH_TEMP, EFUSE_BLK1, 80, 2, [] Flash temperature
|
||||
FLASH_VENDOR, EFUSE_BLK1, 82, 3, [] Flash vendor
|
||||
PSRAM_CAP, EFUSE_BLK1, 85, 2, [] PSRAM capacity
|
||||
PSRAM_TEMP, EFUSE_BLK1, 87, 2, [] PSRAM temperature
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 89, 2, [] PSRAM vendor
|
||||
PKG_VERSION, EFUSE_BLK1, 91, 3, [] Package version
|
||||
PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM capacity
|
||||
TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor
|
||||
PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381
|
||||
// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -19,6 +19,29 @@ extern "C" {
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
@ -35,7 +58,26 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
@ -45,11 +87,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
@ -73,6 +112,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
@ -162,11 +205,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
|
@ -132,7 +132,7 @@ static ssize_t tcp_write(esp_tls_t *tls, const char *data, size_t datalen)
|
||||
|
||||
ssize_t esp_tls_conn_read(esp_tls_t *tls, void *data, size_t datalen)
|
||||
{
|
||||
if (!tls || !data) {
|
||||
if (!tls) {
|
||||
return -1;
|
||||
}
|
||||
return tls->read(tls, (char *)data, datalen);
|
||||
|
@ -126,7 +126,7 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a
|
||||
if (init_config->ulp_mode == ADC_ULP_MODE_DISABLE) {
|
||||
sar_periph_ctrl_adc_oneshot_power_acquire();
|
||||
} else {
|
||||
#if !CONFIG_IDF_TARGET_ESP32C5// # TODO: IDF-8638, IDF-8640
|
||||
#if SOC_LIGHT_SLEEP_SUPPORTED || SOC_DEEP_SLEEP_SUPPORTED
|
||||
esp_sleep_enable_adc_tsens_monitor(true);
|
||||
#endif
|
||||
}
|
||||
@ -229,7 +229,7 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle)
|
||||
if (ulp_mode == ADC_ULP_MODE_DISABLE) {
|
||||
sar_periph_ctrl_adc_oneshot_power_release();
|
||||
} else {
|
||||
#if !CONFIG_IDF_TARGET_ESP32C5// # TODO: IDF-8638, IDF-8640
|
||||
#if SOC_LIGHT_SLEEP_SUPPORTED || SOC_DEEP_SLEEP_SUPPORTED
|
||||
esp_sleep_enable_adc_tsens_monitor(false);
|
||||
#endif
|
||||
}
|
||||
|
@ -31,7 +31,7 @@ esp_err_t adc_dma_init(adc_dma_t *adc_dma)
|
||||
gdma_channel_alloc_config_t rx_alloc_config = {
|
||||
.direction = GDMA_CHANNEL_DIRECTION_RX,
|
||||
};
|
||||
ret = gdma_new_channel(&rx_alloc_config, &(adc_dma->gdma_chan));
|
||||
ret = gdma_new_ahb_channel(&rx_alloc_config, &(adc_dma->gdma_chan));
|
||||
if (ret != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
|
@ -57,6 +57,8 @@ const __attribute__((weak)) __attribute__((section(".rodata_desc"))) esp_app_de
|
||||
.time = "",
|
||||
.date = "",
|
||||
#endif
|
||||
.min_efuse_blk_rev_full = CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL,
|
||||
.max_efuse_blk_rev_full = CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL,
|
||||
};
|
||||
|
||||
#ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR
|
||||
|
@ -33,7 +33,9 @@ typedef struct {
|
||||
char date[16]; /*!< Compile date*/
|
||||
char idf_ver[32]; /*!< Version IDF */
|
||||
uint8_t app_elf_sha256[32]; /*!< sha256 of elf file */
|
||||
uint32_t reserv2[20]; /*!< reserv2 */
|
||||
uint16_t min_efuse_blk_rev_full; /*!< Minimal eFuse block revision supported by image, in format: major * 100 + minor */
|
||||
uint16_t max_efuse_blk_rev_full; /*!< Maximal eFuse block revision supported by image, in format: major * 100 + minor */
|
||||
uint32_t reserv2[19]; /*!< reserv2 */
|
||||
} esp_app_desc_t;
|
||||
|
||||
/** @cond */
|
||||
|
164
components/esp_coex/esp32c61/esp_coex_adapter.c
Normal file
164
components/esp_coex/esp32c61/esp_coex_adapter.c
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <pthread.h>
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "freertos/portmacro.h"
|
||||
#include "esp_heap_caps.h"
|
||||
#include "esp_timer.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "esp_private/esp_clk.h"
|
||||
#include "private/esp_coexist_adapter.h"
|
||||
#include "esp32c61/rom/ets_sys.h"
|
||||
|
||||
#define TAG "esp_coex_adapter"
|
||||
|
||||
#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
|
||||
|
||||
bool IRAM_ATTR esp_coex_common_env_is_chip_wrapper(void)
|
||||
{
|
||||
#ifdef CONFIG_IDF_ENV_FPGA
|
||||
return false;
|
||||
#else
|
||||
return true;
|
||||
#endif
|
||||
}
|
||||
|
||||
void *esp_coex_common_spin_lock_create_wrapper(void)
|
||||
{
|
||||
portMUX_TYPE tmp = portMUX_INITIALIZER_UNLOCKED;
|
||||
void *mux = malloc(sizeof(portMUX_TYPE));
|
||||
|
||||
if (mux) {
|
||||
memcpy(mux, &tmp, sizeof(portMUX_TYPE));
|
||||
return mux;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR esp_coex_common_int_disable_wrapper(void *wifi_int_mux)
|
||||
{
|
||||
if (xPortInIsrContext()) {
|
||||
portENTER_CRITICAL_ISR(wifi_int_mux);
|
||||
} else {
|
||||
portENTER_CRITICAL(wifi_int_mux);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_int_restore_wrapper(void *wifi_int_mux, uint32_t tmp)
|
||||
{
|
||||
if (xPortInIsrContext()) {
|
||||
portEXIT_CRITICAL_ISR(wifi_int_mux);
|
||||
} else {
|
||||
portEXIT_CRITICAL(wifi_int_mux);
|
||||
}
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void)
|
||||
{
|
||||
portYIELD_FROM_ISR();
|
||||
}
|
||||
|
||||
void *esp_coex_common_semphr_create_wrapper(uint32_t max, uint32_t init)
|
||||
{
|
||||
return (void *)xSemaphoreCreateCounting(max, init);
|
||||
}
|
||||
|
||||
void esp_coex_common_semphr_delete_wrapper(void *semphr)
|
||||
{
|
||||
vSemaphoreDelete(semphr);
|
||||
}
|
||||
|
||||
int32_t esp_coex_common_semphr_take_wrapper(void *semphr, uint32_t block_time_tick)
|
||||
{
|
||||
if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) {
|
||||
return (int32_t)xSemaphoreTake(semphr, portMAX_DELAY);
|
||||
} else {
|
||||
return (int32_t)xSemaphoreTake(semphr, block_time_tick);
|
||||
}
|
||||
}
|
||||
|
||||
int32_t esp_coex_common_semphr_give_wrapper(void *semphr)
|
||||
{
|
||||
return (int32_t)xSemaphoreGive(semphr);
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_timer_disarm_wrapper(void *timer)
|
||||
{
|
||||
ets_timer_disarm(timer);
|
||||
}
|
||||
|
||||
void esp_coex_common_timer_done_wrapper(void *ptimer)
|
||||
{
|
||||
ets_timer_done(ptimer);
|
||||
}
|
||||
|
||||
void esp_coex_common_timer_setfn_wrapper(void *ptimer, void *pfunction, void *parg)
|
||||
{
|
||||
ets_timer_setfn(ptimer, pfunction, parg);
|
||||
}
|
||||
|
||||
void IRAM_ATTR esp_coex_common_timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repeat)
|
||||
{
|
||||
ets_timer_arm_us(ptimer, us, repeat);
|
||||
}
|
||||
|
||||
uint32_t esp_coex_common_clk_slowclk_cal_get_wrapper(void)
|
||||
{
|
||||
/* The bit width of WiFi light sleep clock calibration is 12 while the one of
|
||||
* system is 19. It should shift 19 - 12 = 7.
|
||||
*/
|
||||
return (esp_clk_slowclk_cal_get() >> (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH));
|
||||
}
|
||||
|
||||
void *IRAM_ATTR esp_coex_common_malloc_internal_wrapper(size_t size)
|
||||
{
|
||||
return heap_caps_malloc(size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
|
||||
}
|
||||
|
||||
/* static wrapper */
|
||||
|
||||
static int32_t IRAM_ATTR esp_coex_semphr_take_from_isr_wrapper(void *semphr, void *hptw)
|
||||
{
|
||||
return (int32_t)xSemaphoreTakeFromISR(semphr, hptw);
|
||||
}
|
||||
|
||||
static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, void *hptw)
|
||||
{
|
||||
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
|
||||
}
|
||||
|
||||
coex_adapter_funcs_t g_coex_adapter_funcs = {
|
||||
._version = COEX_ADAPTER_VERSION,
|
||||
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
|
||||
._semphr_create = esp_coex_common_semphr_create_wrapper,
|
||||
._semphr_delete = esp_coex_common_semphr_delete_wrapper,
|
||||
._semphr_take_from_isr = esp_coex_semphr_take_from_isr_wrapper,
|
||||
._semphr_give_from_isr = esp_coex_semphr_give_from_isr_wrapper,
|
||||
._semphr_take = esp_coex_common_semphr_take_wrapper,
|
||||
._semphr_give = esp_coex_common_semphr_give_wrapper,
|
||||
._is_in_isr = xPortInIsrContext,
|
||||
._malloc_internal = esp_coex_common_malloc_internal_wrapper,
|
||||
._free = free,
|
||||
._esp_timer_get_time = esp_timer_get_time,
|
||||
._env_is_chip = esp_coex_common_env_is_chip_wrapper,
|
||||
._timer_disarm = esp_coex_common_timer_disarm_wrapper,
|
||||
._timer_done = esp_coex_common_timer_done_wrapper,
|
||||
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
|
||||
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
|
||||
._magic = COEX_ADAPTER_MAGIC,
|
||||
};
|
@ -1 +1 @@
|
||||
Subproject commit 3880b604ad7529c91fb4173da479dd9713ce1f66
|
||||
Subproject commit 6a3c4b312155e49593b5df184ffecb54404d295d
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user