Software support for PMS module.
Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W)
On/locked by default, configurable in Kconfig (esp_system)
Closes https://jira.espressif.com:8443/browse/IDF-2092
Also:
1. Separate static configuration into init phase to improve
performance
2. Add a init code config layer to avoid duplicated configuration
3. Add a HW_CALIBRATION_V1 caps
- Adds arbitration between the erase and write in suspend mode
(If the flash memory is suspended then only a read operation can be performed.)
- espcoredump: Dump does not use suspend feature, just resume before continue.
- spi_flash: Add release_cpu() to do suspend/release_cpu/resume
esp32s2: fix wrong deepsleep configuration issue.
1. if RTC_CK8M_ENABLE_WAIT_DEFAULT set to 1, rtc peripherals will not poweron successfully if pd peripherals in light_sleep, the minimum RTC_CK8M_ENABLE_WAIT_DEFAULT is RTC_POWERUP_CYCLES + RTC_WAIT_CYCLES + 2;
2. when goto deepsleep after lightsleep waking up, rtc regulator should not force pu.
- add lock for single read and continuous read APIs
- update onetime read start singal delay for hardware limitation[*]
- move adc_caps to soc_caps.h
- update license dates
[*] There is a hardware limitation. If the APB clock frequency is high, the
step of this reg signal: ``onetime_start`` may not be captured by the
ADC digital controller (when its clock frequency is too slow). A rough
estimate for this step should be at least 3 ADC digital controller
clock cycle.
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.
This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
longer signed/unsigned int).
Changes come from internal branch commit a6723fc
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).
Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h
This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
freertos/port: update the port files and split into xtensa and riscv ports
freertos: separated cpu files from rest of the kernel sources
freertos/port_xtensa: separated private include files into a folder
freertos/tasks: added task create pinned to core function do not break current IDF API
freertos/tasks: mimiced task create pinned function into tasks.c to do not break the IDF API.
freertos: freertos component now compiling
freertos: freertos component now building
freertos: moved critical sections outside from FR kernel section to portable section
portmacro_xtensa: add void indentifier on functions that take no arguments
freertos: fix critical sections implementation to match with their function prototype
freertos: add cmake changes of freertos into make
freertos: remove portDONT_DISCARD attribute from switch context function, it was breaking the docs building.
freertos: fix conflicitng types of vApplicationSleep function
license: update the license of freertos
freertos: Doxygen comments refactored to render them correctly on docs
freertos: added new functions of freertos into the documentation
freertos: added message buffers and stream buffers to documentation
sysview: update freertos system view to the compatible with version 10
freertos: fixed event group documentation rendering
freertos: update static task structure to match the actual tcb size
freertos: removed backported test functions
freertos/smp: brought SMP code to FreeRTOS 10 port
freertos/portmacro: added missing crosscore interrupt for yielding tasks
freertos: replaced soft-critical sections with hard-critical sections used by SMP
freertos: placed muxes inside of kernel objects
freertos: replaced original FR critical sections with SMP enabled spinlocks critical sections
freertos: moved xtensa port files to a separated folder
freertos: added multiple instance of global variables required to SMP
freertos: added SMP modifications on specific tasks module functions
freertos: added TLS deletion function to task module
freertos/tls: initialize TLS deletion callback to avoid crashing when calling task delete
freertos: modified vTaskDelete to do not erase current task that runs on other core
freertos: reverted taskhandle and timerhandle as void* type
freertos: fixed de-referencing void pointer to get run time counter
freertos: fix system view trace enter macro arguments
freertos: Replaced soft critical sections with spinlocks on event_groups
freertos: fixed tick function to avoid calling tick hooks twice
freertos: Nofity give checking per CPU if schedule is suspended
freertos: added mpu release on TCB deletion
freertos: Added SMP changes when deleting a TCB on idle task
freertos/license: update freertos license in COPYRIGHT.rst
freertos: unicore configurations can use task create pinned to core, it will be always pinned to core 0
freertos/portmacro: added cpu_hal_get_core_id() function instead of inline assembly
freertos/xtensa: update xtensa specific files used in master branch
newlib/locks: revert the preemption checking in lock acquisition and release
ref_clock: fix initial state of ref_clock interrupt handler
freertos: added missing critical sections and yielding checkings
freertos: remove magic numbers in vTaskDelete
freertos: added missing critical section in prvIsQueueEmpty
Fix for issues where RTC FAST memory is updated as part of going into deep
sleep. Very high risk if heaps are in RTC memory - in particular task stacks
may be in RTC memory, but also other variables.
Also fixes potential concurrency problems as RTC FAST memory is not accessible
by CPU during the CRC calculation itself.
Method:
- Disable interrupts (currently for single core only, will need update for S3)
- Load all registers before calculating CRC or going to sleep
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.
This commit helps to clear WEL when flash configuration is done.
**RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.
2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.
Status register bitmap of ISSI chip and GD chip:
| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0 | WIP | WIP |
| 1 | WEL | WEL |
| 2 | BP0 | BP0 |
| 3 | BP1 | BP1 |
| 4 | BP2 | BP2 |
| 5 | BP3 | BP3 |
| 6 | QE | BP4 |
| 7 | SRWD | SRP0 |
| 8 | | SRP1 |
| 9 | | QE |
| 10 | | SUS2 |
| 11 | | LB1 |
| 12 | | LB2 |
| 13 | | LB3 |
| 14 | | CMP |
| 15 | | SUS1 |
QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.
However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.
Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.
This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).
3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.
This commit skips the clearing of status register if there is no protection bits active.
Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
