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efuse(esp32c3): Adds getting chip_revision and chip_pkg
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@ -13,16 +13,16 @@
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// limitations under the License.
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#include <stdint.h>
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#include "soc/efuse_reg.h"
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uint8_t bootloader_common_get_chip_revision(void)
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{
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// should return the same value as esp_efuse_get_chip_ver()
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/* No other revisions for ESP32-C3 */
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return 0;
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return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
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}
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uint32_t bootloader_common_get_chip_ver_pkg(void)
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{
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// should return the same value as esp_efuse_get_pkg_ver()
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return 0;
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return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
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}
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@ -17,7 +17,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table 96cd6235ddc0947b4a296add3f942acb
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// md5_digest_table 69693bb96832f42833460571ebc1f865
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -392,8 +392,24 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
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{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
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};
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static const esp_efuse_desc_t WAFER_VERSION[] = {
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{EFUSE_BLK1, 114, 3}, // WAFER version,
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};
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static const esp_efuse_desc_t PKG_VERSION[] = {
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{EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3,
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};
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static const esp_efuse_desc_t BLOCK1_VERSION[] = {
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{EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version,
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};
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static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
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};
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static const esp_efuse_desc_t BLOCK2_VERSION[] = {
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{EFUSE_BLK2, 128, 3}, // Version of Block2,
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{EFUSE_BLK2, 128, 3}, // Version of BLOCK2,
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};
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static const esp_efuse_desc_t TEMP_CALIB[] = {
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@ -932,8 +948,28 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
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&WAFER_VERSION[0], // WAFER version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
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&PKG_VERSION[0], // Package version 0:ESP32C3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
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&BLOCK1_VERSION[0], // BLOCK1 efuse version
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
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&OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
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&BLOCK2_VERSION[0], // Version of Block2
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&BLOCK2_VERSION[0], // Version of BLOCK2
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NULL
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};
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@ -125,10 +125,14 @@
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SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
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SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
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SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
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WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
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PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
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BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
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# SYS_DATA_PART1 #
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# SYS_DATA_PART1 BLOCK# - System configuration
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#######################
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BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of Block2
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OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
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BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2
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TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
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OCODE, EFUSE_BLK2, 140, 8, ADC OCode
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ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
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Can't render this file because it contains an unexpected character in line 7 and column 87.
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@ -17,7 +17,7 @@ extern "C" {
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#endif
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// md5_digest_table 96cd6235ddc0947b4a296add3f942acb
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// md5_digest_table 69693bb96832f42833460571ebc1f865
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -115,6 +115,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
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extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
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extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
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@ -33,7 +33,7 @@ const static char *TAG = "efuse";
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uint8_t esp_efuse_get_chip_ver(void)
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{
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uint32_t chip_ver = 0;
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// ESP32C3 does not have this field
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esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
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return chip_ver;
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}
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@ -41,7 +41,7 @@ uint8_t esp_efuse_get_chip_ver(void)
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uint32_t esp_efuse_get_pkg_ver(void)
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{
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uint32_t pkg_ver = 0;
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// ESP32C3 does not have this field
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esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
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return pkg_ver;
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}
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@ -17,6 +17,7 @@
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_efuse.h"
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#include "esp_log.h"
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/cache_err_int.h"
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@ -142,6 +143,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
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{
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memset(out_info, 0, sizeof(*out_info));
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out_info->model = CHIP_ESP32C3;
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out_info->revision = esp_efuse_get_chip_ver();
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out_info->cores = 1;
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out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
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}
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@ -1 +1 @@
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Subproject commit 692a0fce388744a071503216ae3f8a2907e9c608
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Subproject commit fc1780090683a3bd7d336d3250826f85362964b4
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@ -760,12 +760,24 @@ extern "C" {
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#define EFUSE_SPI_PAD_CONF_1_S 0
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#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050)
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/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
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/*description: Stores the fist 14 bits of the zeroth part of system data.*/
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#define EFUSE_SYS_DATA_PART0_0 0x00003FFF
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/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
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/*description: Stores the fist 8 bits of the zeroth part of system data.*/
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#define EFUSE_SYS_DATA_PART0_0 0x000000FF
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#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
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#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF
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#define EFUSE_SYS_DATA_PART0_0_S 18
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#define EFUSE_SYS_DATA_PART0_0_V 0xFF
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#define EFUSE_SYS_DATA_PART0_0_S 25
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/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */
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/*description: Package version 0:ESP32-C3 */
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#define EFUSE_PKG_VERSION 0x00000007
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#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
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#define EFUSE_PKG_VERSION_V 0x7
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#define EFUSE_PKG_VERSION_S 21
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/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */
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/*description: WAFER version 0:A */
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#define EFUSE_WAFER_VERSION 0x00000007
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#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S))
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#define EFUSE_WAFER_VERSION_V 0x7
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#define EFUSE_WAFER_VERSION_S 18
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/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
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/*description: Stores the second part of SPI_PAD_CONF.*/
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#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF
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