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efuse/esp32: Expands PKG_VER from 3 bit to 4 bits

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Closes: IDF-1919
This commit is contained in:
KonstantinKondrashov 2020-08-05 14:56:01 +08:00 committed by bot
parent 6d14bdf068
commit 2373f115fc
14 changed files with 81 additions and 33 deletions
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7
components/bootloader_support/include/bootloader_common.h
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@ -167,6 +167,13 @@ esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t
*/
uint8_t bootloader_common_get_chip_revision(void);
/**
* @brief Get chip package
*
* @return Chip package number
*/
uint32_t bootloader_common_get_chip_ver_pkg(void);
/**
* @brief Query reset reason
*

7
components/bootloader_support/src/bootloader_efuse_esp32.c
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@ -45,6 +45,13 @@ uint8_t bootloader_common_get_chip_revision(void)
return chip_ver;
}
uint32_t bootloader_common_get_chip_ver_pkg(void)
{
uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
return (pkg_version_4bit << 3) | pkg_version;
}
int bootloader_clock_get_rated_freq_mhz()
{
//Check if ESP32 is rated for a CPU frequency of 160MHz only

7
components/bootloader_support/src/bootloader_efuse_esp32s2.c
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@ -15,6 +15,7 @@
#include "sdkconfig.h"
#include "bootloader_clock.h"
#include "bootloader_common.h"
#include "soc/efuse_reg.h"
uint8_t bootloader_common_get_chip_revision(void)
{
@ -22,3 +23,9 @@ uint8_t bootloader_common_get_chip_revision(void)
/* No other revisions for ESP32-S2 */
return 0;
}
uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
}

5
components/bootloader_support/src/bootloader_flash_config_esp32.c
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@ -78,8 +78,7 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
drv = 3;
}
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_ver = chip_ver & 0x7;
uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
@ -176,7 +175,7 @@ int bootloader_flash_get_wp_pin(void)
#else
// no custom value, find it based on the package eFuse value
uint8_t chip_ver;
uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
switch(pkg_ver) {
case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
return ESP32_D2WD_WP_GPIO;

3
components/bootloader_support/src/esp32/bootloader_esp32.c
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@ -52,8 +52,7 @@ static const char *TAG = "boot.esp32";
void bootloader_configure_spi_pins(int drv)
{
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_ver = chip_ver & 0x7;
uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||

8
components/efuse/esp32/esp_efuse_table.c
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@ -17,7 +17,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 8c9f6537b47cc5b26a1a5896158c612a
// md5_digest_table f552d73ac112985991efa6734a60c8d9
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -148,7 +148,8 @@ static const esp_efuse_desc_t CHIP_VER_DIS_BT[] = {
};
static const esp_efuse_desc_t CHIP_VER_PKG[] = {
{EFUSE_BLK0, 105, 3}, // EFUSE_RD_CHIP_VER_PKG,
{EFUSE_BLK0, 105, 3}, // EFUSE_RD_CHIP_VER_PKG least significant bits,
{EFUSE_BLK0, 98, 1}, // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit,
};
static const esp_efuse_desc_t CHIP_CPU_FREQ_LOW[] = {
@ -348,7 +349,8 @@ const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[] = {
};
const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[] = {
&CHIP_VER_PKG[0], // EFUSE_RD_CHIP_VER_PKG
&CHIP_VER_PKG[0], // EFUSE_RD_CHIP_VER_PKG least significant bits
&CHIP_VER_PKG[1], // EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit
NULL
};

3
components/efuse/esp32/esp_efuse_table.csv
View File

@ -65,7 +65,8 @@ RD_DIS_BLK3, EFUSE_BLK0, 18, 1, Read protection for EFUSE_BL
#############
CHIP_VER_DIS_APP_CPU, EFUSE_BLK0, 96, 1, EFUSE_RD_CHIP_VER_DIS_APP_CPU
CHIP_VER_DIS_BT, EFUSE_BLK0, 97, 1, EFUSE_RD_CHIP_VER_DIS_BT
CHIP_VER_PKG, EFUSE_BLK0, 105, 3, EFUSE_RD_CHIP_VER_PKG
CHIP_VER_PKG, EFUSE_BLK0, 105, 3, EFUSE_RD_CHIP_VER_PKG least significant bits
, EFUSE_BLK0, 98, 1, EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit
CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW
CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED
CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1

Can't render this file because it contains an unexpected character in line 7 and column 87.

2
components/efuse/esp32/include/esp_efuse_table.h
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@ -17,7 +17,7 @@ extern "C" {
#endif
// md5_digest_table 8c9f6537b47cc5b26a1a5896158c612a
// md5_digest_table f552d73ac112985991efa6734a60c8d9
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.

2
components/efuse/src/esp32/esp_efuse_fields.c
View File

@ -62,7 +62,7 @@ uint8_t esp_efuse_get_chip_ver(void)
uint32_t esp_efuse_get_pkg_ver(void)
{
uint32_t pkg_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_PKG, &pkg_ver, 3);
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_PKG, &pkg_ver, 4);
return pkg_ver;
}

13
components/efuse/test/test_efuse.c
View File

@ -17,6 +17,7 @@
#include "test_utils.h"
#include "sdkconfig.h"
#include "esp_rom_efuse.h"
#include "bootloader_common.h"
static const char* TAG = "efuse_test";
@ -845,3 +846,15 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]")
}
}
#endif // CONFIG_IDF_ENV_FPGA
TEST_CASE("Test chip_ver_pkg APIs return the same value", "[efuse]")
{
esp_efuse_utility_update_virt_blocks();
TEST_ASSERT_EQUAL_INT(esp_efuse_get_pkg_ver(), bootloader_common_get_chip_ver_pkg());
}
TEST_CASE("Test chip_revision APIs return the same value", "[efuse]")
{
esp_efuse_utility_update_virt_blocks();
TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision());
}

4
components/esp32/spiram_psram.c
View File

@ -23,6 +23,7 @@
#include "esp_err.h"
#include "esp_types.h"
#include "esp_log.h"
#include "esp_efuse.h"
#include "spiram_psram.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
@ -804,8 +805,7 @@ bool psram_is_32mbit_ver0(void)
esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
{
psram_io_t psram_io={0};
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_ver = chip_ver & 0x7;
uint32_t pkg_ver = esp_efuse_get_pkg_ver();
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
ESP_EARLY_LOGI(TAG, "This chip is ESP32-D2WD");
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();

2
components/esp32/system_api_esp32.c
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@ -159,7 +159,7 @@ void esp_chip_info(esp_chip_info_t* out_info)
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
}
int package = (efuse_rd3 & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
uint32_t package = esp_efuse_get_pkg_ver();
if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||

29
components/soc/soc/esp32/include/soc/efuse_reg.h
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@ -104,7 +104,7 @@
#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1
#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12
/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
/*description: chip package */
/*description: least significant bits of chip package */
#define EFUSE_RD_CHIP_VER_PKG 0x00000007
#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
#define EFUSE_RD_CHIP_VER_PKG_V 0x7
@ -127,12 +127,12 @@
#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3))
#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1
#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2))
#define EFUSE_RD_CHIP_VER_32PAD_V 0x1
#define EFUSE_RD_CHIP_VER_32PAD_S 2
/* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: most significant bit of chip package */
#define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2))
#define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2))
#define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1
#define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2
/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
@ -381,7 +381,7 @@
#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1
#define EFUSE_CHIP_CPU_FREQ_LOW_S 12
/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
/*description: */
/*description: least significant bits of chip package */
#define EFUSE_CHIP_VER_PKG 0x00000007
#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
#define EFUSE_CHIP_VER_PKG_V 0x7
@ -391,6 +391,7 @@
#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2
#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4
#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5
#define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6
/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
/*description: program for SPI_pad_config_hd*/
#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F
@ -403,12 +404,12 @@
#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3))
#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1
#define EFUSE_CHIP_VER_DIS_CACHE_S 3
/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_32PAD (BIT(2))
#define EFUSE_CHIP_VER_32PAD_M (BIT(2))
#define EFUSE_CHIP_VER_32PAD_V 0x1
#define EFUSE_CHIP_VER_32PAD_S 2
/* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: most significant bit of chip package */
#define EFUSE_CHIP_VER_PKG_4BIT (BIT(2))
#define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2))
#define EFUSE_CHIP_VER_PKG_4BIT_V 0x1
#define EFUSE_CHIP_VER_PKG_4BIT_S 2
/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define EFUSE_CHIP_VER_DIS_BT (BIT(1))

22
components/soc/soc/esp32s2/include/soc/efuse_reg.h
View File

@ -917,12 +917,24 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_1_S 0
#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050)
/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
/*description: Stores the fist 14 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_0 0x00003FFF
/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:25] ;default: 7'h0 ; */
/*description: Stores the fist 7 bits of the zeroth part of system data.*/
#define EFUSE_SYS_DATA_PART0_0 0x0000007F
#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF
#define EFUSE_SYS_DATA_PART0_0_S 18
#define EFUSE_SYS_DATA_PART0_0_V 0x7F
#define EFUSE_SYS_DATA_PART0_0_S 25
/* EFUSE_PKG_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */
/*description: Package version 0:ESP32-S2, 1:ESP32-S2FH16, 2:ESP32-S2FH32 */
#define EFUSE_PKG_VERSION 0x0000000F
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0xF
#define EFUSE_PKG_VERSION_S 21
/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */
/*description: WAFER version 0:A */
#define EFUSE_WAFER_VERSION 0x00000007
#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S))
#define EFUSE_WAFER_VERSION_V 0x7
#define EFUSE_WAFER_VERSION_S 18
/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
/*description: Stores the second part of SPI_PAD_CONF.*/
#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF