soc: move implementations to esp_hw_support

components/bootloader/subproject/main/ld/esp32/bootloader.ld

@@ -56,8 +56,8 @@ SECTIONS
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
     *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)

components/bootloader/subproject/main/ld/esp32s2/bootloader.ld

@@ -43,9 +43,9 @@ SECTIONS
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
     *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_time.*(.literal .text .literal.* .text.*)
-    *libsoc.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)

components/bootloader/subproject/main/ld/esp32s3/bootloader.ld

@@ -44,9 +44,9 @@ SECTIONS
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
     *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_time.*(.literal .text .literal.* .text.*)
-    *libsoc.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)

components/esp_hw_support/CMakeLists.txt

@@ -1,4 +1,8 @@
 idf_component_register(SRCS "compare_set.c"
                             "cpu_util.c"
                        INCLUDE_DIRS include
-                       REQUIRES soc)
+                       REQUIRES soc
+                       LDFRAGMENTS linker.lf)
+
+idf_build_get_property(target IDF_TARGET)
+add_subdirectory(port/${target})

components/esp_hw_support/component.mk

@@ -1,2 +1,4 @@
-COMPONENT_SRCDIRS := .
-COMPONENT_ADD_INCLUDEDIRS := . include
+COMPONENT_SRCDIRS := . port/$(IDF_TARGET)
+COMPONENT_ADD_INCLUDEDIRS := . include port/$(IDF_TARGET)/private_include
+
+port/$(IDF_TARGET)/rtc_clk.o: CFLAGS += -fno-jump-tables -fno-tree-switch-conversion

components/esp_hw_support/include/soc_log.h

@@ -14,6 +14,7 @@
 
 #pragma once
 #include "esp_rom_sys.h"
+
 /**
  * @file soc_log.h
  * @brief SOC library logging functions

components/esp_hw_support/linker.lf

@@ -0,0 +1,11 @@
+[mapping:esp_hw_support]
+archive: libesp_hw_support.a
+entries:
+    cpu_util (noflash_text)
+    rtc_clk (noflash)
+    rtc_init:rtc_vddsdio_set_config (noflash)
+    rtc_periph (noflash_text)
+    rtc_pm (noflash_text)
+    rtc_sleep (noflash_text)
+    rtc_time (noflash_text)
+    rtc_wdt (noflash_text)

components/esp_hw_support/port/esp32/CMakeLists.txt

@@ -0,0 +1,19 @@
+target_include_directories(${COMPONENT_LIB} PUBLIC .)
+target_include_directories(${COMPONENT_LIB} PRIVATE private_include)
+
+set(srcs 
+    "rtc_clk.c"
+    "rtc_clk_init.c"
+    "rtc_init.c"
+    "rtc_pm.c"
+    "rtc_sleep.c"
+    "rtc_time.c"
+    "rtc_wdt.c")
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+
+if(NOT CMAKE_BUILD_EARLY_EXPANSION)
+    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/rtc_clk.c" PROPERTIES
+                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
+endif()

components/esp_hw_support/port/esp32s2/CMakeLists.txt

@@ -0,0 +1,20 @@
+target_include_directories(${COMPONENT_LIB} PUBLIC .)
+target_include_directories(${COMPONENT_LIB} PUBLIC private_include)
+
+set(srcs 
+    "rtc_clk.c"
+    "rtc_clk_init.c"
+    "rtc_init.c"
+    "rtc_pm.c"
+    "rtc_sleep.c"
+    "rtc_time.c"
+    "rtc_wdt.c"
+    "regi2c_ctrl.c")
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+
+if(NOT CMAKE_BUILD_EARLY_EXPANSION)
+    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/rtc_clk.c" PROPERTIES
+                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
+endif()

components/esp_hw_support/port/esp32s3/CMakeLists.txt

@@ -0,0 +1,18 @@
+target_include_directories(${COMPONENT_LIB} PUBLIC .)
+target_include_directories(${COMPONENT_LIB} PUBLIC private_include)
+
+set(srcs 
+    "rtc_clk.c"
+    "rtc_clk_init.c"
+    "rtc_init.c"
+    "rtc_pm.c"
+    "rtc_sleep.c"
+    "rtc_time.c")
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+
+if(NOT CMAKE_BUILD_EARLY_EXPANSION)
+    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/rtc_clk.c" PROPERTIES
+                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
+endif()

components/esp_hw_support/test/CMakeLists.txt

@@ -0,0 +1,3 @@
+idf_component_register(SRC_DIRS "."
+                    PRIV_INCLUDE_DIRS "${include_dirs}"
+                    PRIV_REQUIRES cmock test_utils esp_hw_support)

components/soc/CMakeLists.txt

@@ -1,10 +1,8 @@
-idf_build_get_property(target IDF_TARGET)
-
 idf_component_register(SRCS "lldesc.c"
                             "soc_include_legacy_warn.c"
                             "memory_layout_utils.c"
                        INCLUDE_DIRS include
-                       PRIV_REQUIRES hal # [refactor-todo] soc dependency on hal for rtc sources
                        LDFRAGMENTS linker.lf)
 
-add_subdirectory(${target})
+idf_build_get_property(target IDF_TARGET)
+add_subdirectory(${target})

components/soc/esp32/CMakeLists.txt

@@ -7,15 +7,8 @@ set(srcs
     "interrupts.c"
     "pcnt_periph.c"
     "ledc_periph.c"
-    "rtc_clk.c"
-    "rtc_clk_init.c"
-    "rtc_init.c"
     "rtc_io_periph.c"
     "rtc_periph.c"
-    "rtc_pm.c"
-    "rtc_sleep.c"
-    "rtc_time.c"
-    "rtc_wdt.c"
     "sdio_slave_periph.c"
     "sdmmc_periph.c"
     "soc_memory_layout.c"
@@ -27,8 +20,3 @@ add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
 target_include_directories(${COMPONENT_LIB} PUBLIC . include)
-
-if(NOT CMAKE_BUILD_EARLY_EXPANSION)
-    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/rtc_clk.c" PROPERTIES
-                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
-endif()

components/soc/esp32s2/CMakeLists.txt

@@ -8,16 +8,8 @@ set(srcs
     "interrupts.c"
     "ledc_periph.c"
     "pcnt_periph.c"
-    "regi2c_ctrl.c"
-    "rtc_clk.c"
-    "rtc_clk_init.c"
-    "rtc_init.c"
     "rtc_io_periph.c"
     "rtc_periph.c"
-    "rtc_pm.c"
-    "rtc_sleep.c"
-    "rtc_time.c"
-    "rtc_wdt.c"
     "soc_memory_layout.c"
     "spi_periph.c"
     "touch_sensor_periph.c"
@@ -28,8 +20,3 @@ add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
 target_include_directories(${COMPONENT_LIB} PUBLIC . include)
-
-if(NOT CMAKE_BUILD_EARLY_EXPANSION)
-    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/rtc_clk.c" PROPERTIES
-                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
-endif()

components/soc/esp32s2/i2c_apll.h

@@ -1,136 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_apll.h
- * @brief Register definitions for audio PLL (APLL)
- *
- * This file lists register fields of APLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_clk_apll_enable function in rtc_clk.c.
- */
-
-#define I2C_APLL            0X6D
-#define I2C_APLL_HOSTID     1
-
-#define I2C_APLL_IR_CAL_DELAY        0
-#define I2C_APLL_IR_CAL_DELAY_MSB    3
-#define I2C_APLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_APLL_IR_CAL_RSTB        0
-#define I2C_APLL_IR_CAL_RSTB_MSB    4
-#define I2C_APLL_IR_CAL_RSTB_LSB    4
-
-#define I2C_APLL_IR_CAL_START        0
-#define I2C_APLL_IR_CAL_START_MSB    5
-#define I2C_APLL_IR_CAL_START_LSB    5
-
-#define I2C_APLL_IR_CAL_UNSTOP        0
-#define I2C_APLL_IR_CAL_UNSTOP_MSB    6
-#define I2C_APLL_IR_CAL_UNSTOP_LSB    6
-
-#define I2C_APLL_OC_ENB_FCAL        0
-#define I2C_APLL_OC_ENB_FCAL_MSB    7
-#define I2C_APLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_APLL_IR_CAL_EXT_CAP        1
-#define I2C_APLL_IR_CAL_EXT_CAP_MSB    4
-#define I2C_APLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_APLL_IR_CAL_ENX_CAP        1
-#define I2C_APLL_IR_CAL_ENX_CAP_MSB    5
-#define I2C_APLL_IR_CAL_ENX_CAP_LSB    5
-
-#define I2C_APLL_OC_LBW        1
-#define I2C_APLL_OC_LBW_MSB    6
-#define I2C_APLL_OC_LBW_LSB    6
-
-#define I2C_APLL_IR_CAL_CK_DIV        2
-#define I2C_APLL_IR_CAL_CK_DIV_MSB    3
-#define I2C_APLL_IR_CAL_CK_DIV_LSB    0
-
-#define I2C_APLL_OC_DCHGP        2
-#define I2C_APLL_OC_DCHGP_MSB    6
-#define I2C_APLL_OC_DCHGP_LSB    4
-
-#define I2C_APLL_OC_ENB_VCON        2
-#define I2C_APLL_OC_ENB_VCON_MSB    7
-#define I2C_APLL_OC_ENB_VCON_LSB    7
-
-#define I2C_APLL_OR_CAL_CAP        3
-#define I2C_APLL_OR_CAL_CAP_MSB    4
-#define I2C_APLL_OR_CAL_CAP_LSB    0
-
-#define I2C_APLL_OR_CAL_UDF        3
-#define I2C_APLL_OR_CAL_UDF_MSB    5
-#define I2C_APLL_OR_CAL_UDF_LSB    5
-
-#define I2C_APLL_OR_CAL_OVF        3
-#define I2C_APLL_OR_CAL_OVF_MSB    6
-#define I2C_APLL_OR_CAL_OVF_LSB    6
-
-#define I2C_APLL_OR_CAL_END        3
-#define I2C_APLL_OR_CAL_END_MSB    7
-#define I2C_APLL_OR_CAL_END_LSB    7
-
-#define I2C_APLL_OR_OUTPUT_DIV        4
-#define I2C_APLL_OR_OUTPUT_DIV_MSB    4
-#define I2C_APLL_OR_OUTPUT_DIV_LSB    0
-
-#define I2C_APLL_OC_TSCHGP        4
-#define I2C_APLL_OC_TSCHGP_MSB    6
-#define I2C_APLL_OC_TSCHGP_LSB    6
-
-#define I2C_APLL_EN_FAST_CAL        4
-#define I2C_APLL_EN_FAST_CAL_MSB    7
-#define I2C_APLL_EN_FAST_CAL_LSB    7
-
-#define I2C_APLL_OC_DHREF_SEL        5
-#define I2C_APLL_OC_DHREF_SEL_MSB    1
-#define I2C_APLL_OC_DHREF_SEL_LSB    0
-
-#define I2C_APLL_OC_DLREF_SEL        5
-#define I2C_APLL_OC_DLREF_SEL_MSB    3
-#define I2C_APLL_OC_DLREF_SEL_LSB    2
-
-#define I2C_APLL_SDM_DITHER        5
-#define I2C_APLL_SDM_DITHER_MSB    4
-#define I2C_APLL_SDM_DITHER_LSB    4
-
-#define I2C_APLL_SDM_STOP        5
-#define I2C_APLL_SDM_STOP_MSB    5
-#define I2C_APLL_SDM_STOP_LSB    5
-
-#define I2C_APLL_SDM_RSTB        5
-#define I2C_APLL_SDM_RSTB_MSB    6
-#define I2C_APLL_SDM_RSTB_LSB    6
-
-#define I2C_APLL_OC_DVDD        6
-#define I2C_APLL_OC_DVDD_MSB    4
-#define I2C_APLL_OC_DVDD_LSB    0
-
-#define I2C_APLL_DSDM2        7
-#define I2C_APLL_DSDM2_MSB    5
-#define I2C_APLL_DSDM2_LSB    0
-
-#define I2C_APLL_DSDM1        8
-#define I2C_APLL_DSDM1_MSB    7
-#define I2C_APLL_DSDM1_LSB    0
-
-#define I2C_APLL_DSDM0        9
-#define I2C_APLL_DSDM0_MSB    7
-#define I2C_APLL_DSDM0_LSB    0
-

components/soc/esp32s2/i2c_bbpll.h

@@ -1,184 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_apll.h
- * @brief Register definitions for digital PLL (BBPLL)
- *
- * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_clk_cpu_freq_set function in rtc_clk.c.
- */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    1
-
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        6
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_BBADC_DELAY1        9
-#define I2C_BBPLL_BBADC_DELAY1_MSB    1
-#define I2C_BBPLL_BBADC_DELAY1_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6
-

components/soc/esp32s2/i2c_ulp.h

@@ -1,39 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_ulp.h
- * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
- *
- * This file lists register fields of ULP, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_init function in rtc_init.c.
- */
-
-#define I2C_ULP 0x61
-#define I2C_ULP_HOSTID 1
-
-#define I2C_ULP_IR_RESETB 0
-#define I2C_ULP_IR_RESETB_MSB 0
-#define I2C_ULP_IR_RESETB_LSB 0
-
-#define I2C_ULP_O_DONE_FLAG 3
-#define I2C_ULP_O_DONE_FLAG_MSB 0
-#define I2C_ULP_O_DONE_FLAG_LSB 0
-
-#define I2C_ULP_BG_O_DONE_FLAG 3
-#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
-#define I2C_ULP_BG_O_DONE_FLAG_LSB 3

components/soc/esp32s2/include/soc/i2c_saradc.h

@@ -1,77 +0,0 @@
-// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_sar.h
- * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
- *
- * This file lists register fields of SAR, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * function in adc_ll.h.
- */
-
-#define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
-
-#define ADC_ANA_CONFIG2_REG  0x6000E048
-
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR1_DREF_ADDR  0x2
-#define ADC_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR2_DREF_ADDR  0x5
-#define ADC_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_SARADC_ENT_RTC_ADDR_LSB 3

components/soc/esp32s3/CMakeLists.txt

@@ -8,14 +8,8 @@ set(srcs
     "interrupts.c"
     "ledc_periph.c"
     "pcnt_periph.c"
-    "rtc_clk.c"
-    "rtc_clk_init.c"
-    "rtc_init.c"
     "rtc_io_periph.c"
     "rtc_periph.c"
-    "rtc_pm.c"
-    "rtc_sleep.c"
-    "rtc_time.c"
     "sdio_slave_periph.c"
     "sdmmc_periph.c"
     "soc_memory_layout.c"
@@ -27,8 +21,3 @@ add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
 target_include_directories(${COMPONENT_LIB} PUBLIC . include)
-
-if(NOT CMAKE_BUILD_EARLY_EXPANSION)
-    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/rtc_clk.c" PROPERTIES
-                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
-endif()

components/soc/esp32s3/i2c_bbpll.h

@@ -1,184 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_bbpll.h
- * @brief Register definitions for digital PLL (BBPLL)
- *
- * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_clk_cpu_freq_set function in rtc_clk.c.
- */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    1
-
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        6
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_OC_VCO_DBIAS        9
-#define I2C_BBPLL_OC_VCO_DBIAS_MSB    1
-#define I2C_BBPLL_OC_VCO_DBIAS_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6
-

components/soc/esp32s3/i2c_ulp.h

@@ -1,39 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_ulp.h
- * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
- *
- * This file lists register fields of ULP, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_init function in rtc_init.c.
- */
-
-#define I2C_ULP 0x61
-#define I2C_ULP_HOSTID 1
-
-#define I2C_ULP_IR_RESETB 0
-#define I2C_ULP_IR_RESETB_MSB 0
-#define I2C_ULP_IR_RESETB_LSB 0
-
-#define I2C_ULP_O_DONE_FLAG 3
-#define I2C_ULP_O_DONE_FLAG_MSB 0
-#define I2C_ULP_O_DONE_FLAG_LSB 0
-
-#define I2C_ULP_BG_O_DONE_FLAG 3
-#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
-#define I2C_ULP_BG_O_DONE_FLAG_LSB 3

components/soc/linker.lf

@@ -1,12 +1,4 @@
 [mapping:soc]
 archive: libsoc.a
 entries:
-    cpu_util (noflash_text)
-    rtc_clk (noflash)
-    rtc_init:rtc_vddsdio_set_config (noflash)
-    rtc_periph (noflash_text)
-    rtc_pm (noflash_text)
-    rtc_sleep (noflash_text)
-    rtc_time (noflash_text)
-    rtc_wdt (noflash_text)
     lldesc (noflash)

components/soc/test/CMakeLists.txt

@@ -1,5 +0,0 @@
-idf_build_get_property(soc_name IDF_TARGET)
-
-idf_component_register(SRC_DIRS "."
-                    PRIV_INCLUDE_DIRS "${include_dirs}"
-                    PRIV_REQUIRES cmock test_utils)

tools/ci/check_public_headers_exceptions.txt

@@ -108,7 +108,7 @@ components/esp_common/include/esp_compiler.h
 components/lwip/lwip/src/include/lwip/prot/nd6.h
 components/lwip/port/esp32/include/netif/dhcp_state.h
 components/soc/src/esp32/rtc_clk_common.h
-components/soc/src/esp32/i2c_rtc_clk.h
+components/esp_hw_support/port/esp32/regi2c_ctrl.h
 components/esp_rom/include/esp32/rom/sha.h
 components/esp_rom/include/esp32/rom/secure_boot.h
 components/esp_rom/include/esp32s2/rom/spi_flash.h