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Code Issues Actions 2 Packages Projects Releases Wiki Activity

1. Fix CPU switch to 160M issue;

Browse Source 
2. increase lightsleep voltage to make sure wakeup successfully;
3. add judgement code to whether wait or not when switch CPU frequency.
This commit is contained in:
chaijie 2020-12-29 16:16:12 +08:00 committed by Marius Vikhammer
parent eb788deb03
commit d505474f78
2 changed files with 22 additions and 6 deletions
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22
components/esp_hw_support/port/esp32c3/rtc_clk.c
View File

@ -311,18 +311,24 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
*/
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{
int dbias = DIG_DBIAS_80M_160M;
int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
int origin_cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
int dbias = DIG_DBIAS_80M;
int per_conf = DPORT_CPUPERIOD_SEL_80;
if (cpu_freq_mhz == 80) {
/* nothing to do */
} else if (cpu_freq_mhz == 160) {
dbias = DIG_DBIAS_160M;
per_conf = DPORT_CPUPERIOD_SEL_160;
} else {
SOC_LOGE(TAG, "invalid frequency");
abort();
}
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
wait_dig_dbias_valid(2);
if ((origin_soc_clk == DPORT_SOC_CLK_SEL_XTAL) || (origin_soc_clk == DPORT_SOC_CLK_SEL_8M)
|| (((origin_soc_clk == DPORT_SOC_CLK_SEL_PLL) && (0 == origin_cpuperiod_sel)))) {
wait_dig_dbias_valid(2);
}
REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
@ -470,6 +476,8 @@ void rtc_clk_cpu_freq_set_xtal(void)
*/
void rtc_clk_cpu_freq_to_xtal(int freq, int div)
{
int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT);
ets_update_cpu_frequency(freq);
/* lower the voltage */
if (freq <= 2) {
@ -477,7 +485,9 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
} else {
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
}
wait_dig_dbias_valid(2);
if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) && (origin_div_cnt > 0)) {
wait_dig_dbias_valid(2);
}
/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1);
@ -489,9 +499,13 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
static void rtc_clk_cpu_freq_to_8m(void)
{
int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT);
ets_update_cpu_frequency(8);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
wait_dig_dbias_valid(2);
if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) && (origin_div_cnt > 4)) {
wait_dig_dbias_valid(2);
}
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);

6
components/soc/esp32c3/include/soc/rtc.h
View File

@ -88,7 +88,9 @@ extern "C" {
*/
#define XTAL_FREQ_EST_CYCLES 10
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
@ -110,7 +112,7 @@ extern "C" {
/*
set sleep_init default param
*/
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0