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Merge branch 'feature/efuse_support_for_esp32s3' into 'master'

Browse Source 
efuse: Adds support for esp32-s3 chip

See merge request espressif/esp-idf!10491
This commit is contained in:
Angus Gratton 2020-10-22 13:53:01 +08:00
commit 57d6026f97
14 changed files with 3554 additions and 297 deletions
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7
components/bootloader_support/src/bootloader_efuse_esp32s3.c
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@ -16,6 +16,13 @@
uint8_t bootloader_common_get_chip_revision(void)
{
// should return the same value as esp_efuse_get_chip_ver()
/* No other revisions for ESP32-S3 */
return 0;
}
uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return 0;
}

1
components/bootloader_support/src/esp32s3/flash_encrypt.c
View File

@ -210,7 +210,6 @@ static esp_err_t initialise_flash_encryption(void)
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
#endif
esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
esp_err_t err = esp_efuse_batch_write_commit();

1
components/bootloader_support/src/esp32s3/secure_boot.c
View File

@ -284,7 +284,6 @@ esp_err_t esp_secure_boot_v2_permanently_enable(const esp_image_metadata_t *imag
__attribute__((unused)) static const uint8_t enable = 1;
esp_efuse_write_field_bit(ESP_EFUSE_DIS_BOOT_REMAP);
esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE

2
components/efuse/Kconfig
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@ -42,6 +42,6 @@ menu "eFuse Bit Manager"
default 256 if EFUSE_CODE_SCHEME_COMPAT_NONE
default 192 if EFUSE_CODE_SCHEME_COMPAT_3_4
default 128 if EFUSE_CODE_SCHEME_COMPAT_REPEAT
default 256 if IDF_TARGET_ESP32S2
default 256 if !IDF_TARGET_ESP32
endmenu

5
components/efuse/efuse_table_gen.py
View File

@ -353,8 +353,7 @@ class FuseDefinition(object):
if idf_target == "esp32":
if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3"]:
raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK3")
if idf_target == "esp32s2":
else:
if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3", "EFUSE_BLK4",
"EFUSE_BLK5", "EFUSE_BLK6", "EFUSE_BLK7", "EFUSE_BLK8", "EFUSE_BLK9",
"EFUSE_BLK10"]:
@ -463,7 +462,7 @@ def main():
global idf_target
parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32','esp32s2'], default='esp32')
parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3'], default='esp32')
parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
parser.add_argument('--debug', help='Create header file with debug info', default=False, action="store_false")
parser.add_argument('--info', help='Print info about range of used bits', default=False, action="store_true")

982
components/efuse/esp32s3/esp_efuse_table.c
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,3 +11,983 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License
#include "sdkconfig.h"
#include "esp_efuse.h"
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 6a29c09c943d9cb07bd874af57b5870e
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
// To show efuse_table run the command 'show_efuse_table'.
static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
{EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
};
static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = {
{EFUSE_BLK0, 1, 1}, // Write protection for DIS_RTC_RAM_BOOT,
};
static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
{EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
};
static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
{EFUSE_BLK0, 3, 1}, // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL,
};
static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
{EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
{EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
{EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
{EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2,
};
static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
{EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0,
};
static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
{EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1,
};
static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
{EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2,
};
static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
{EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3,
};
static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
{EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4,
};
static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
{EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
{EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
{EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
};
static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
{EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION,
};
static const esp_efuse_desc_t WR_DIS_BLK1[] = {
{EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS,
};
static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
{EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1,
};
static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
{EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA,
};
static const esp_efuse_desc_t WR_DIS_KEY0[] = {
{EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0,
};
static const esp_efuse_desc_t WR_DIS_KEY1[] = {
{EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1,
};
static const esp_efuse_desc_t WR_DIS_KEY2[] = {
{EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2,
};
static const esp_efuse_desc_t WR_DIS_KEY3[] = {
{EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3,
};
static const esp_efuse_desc_t WR_DIS_KEY4[] = {
{EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4,
};
static const esp_efuse_desc_t WR_DIS_KEY5[] = {
{EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5,
};
static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
{EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
};
static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
{EFUSE_BLK0, 30, 1}, // Write protection for USB_EXCHG_PINS,
};
static const esp_efuse_desc_t RD_DIS_KEY0[] = {
{EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0,
};
static const esp_efuse_desc_t RD_DIS_KEY1[] = {
{EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1,
};
static const esp_efuse_desc_t RD_DIS_KEY2[] = {
{EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2,
};
static const esp_efuse_desc_t RD_DIS_KEY3[] = {
{EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3,
};
static const esp_efuse_desc_t RD_DIS_KEY4[] = {
{EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4,
};
static const esp_efuse_desc_t RD_DIS_KEY5[] = {
{EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5,
};
static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
{EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
};
static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = {
{EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM,
};
static const esp_efuse_desc_t DIS_ICACHE[] = {
{EFUSE_BLK0, 40, 1}, // Disable Icache,
};
static const esp_efuse_desc_t DIS_DCACHE[] = {
{EFUSE_BLK0, 41, 1}, // Disable Dcace,
};
static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = {
{EFUSE_BLK0, 42, 1}, // Disable Icache in download mode include boot_mode 0 1 2 3 6 7,
};
static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = {
{EFUSE_BLK0, 43, 1}, // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7,
};
static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
{EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function,
};
static const esp_efuse_desc_t DIS_USB[] = {
{EFUSE_BLK0, 45, 1}, // Disable USB function,
};
static const esp_efuse_desc_t DIS_CAN[] = {
{EFUSE_BLK0, 46, 1}, // Disable CAN function,
};
static const esp_efuse_desc_t DIS_APP_CPU[] = {
{EFUSE_BLK0, 47, 1}, // Disables APP CPU,
};
static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
{EFUSE_BLK0, 48, 3}, // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral,
};
static const esp_efuse_desc_t HARD_DIS_JTAG[] = {
{EFUSE_BLK0, 51, 1}, // Hardware disable jtag permanently disable jtag function,
};
static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
{EFUSE_BLK0, 52, 1}, // Disable flash encrypt function,
};
static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
{EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins,
};
static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = {
{EFUSE_BLK0, 58, 1}, // Enable external PHY,
};
static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = {
{EFUSE_BLK0, 59, 2}, // Enables BTLC GPIO,
};
static const esp_efuse_desc_t VDD_SPI_XPD[] = {
{EFUSE_BLK0, 68, 1}, // VDD_SPI regulator power up,
};
static const esp_efuse_desc_t VDD_SPI_TIEH[] = {
{EFUSE_BLK0, 69, 1}, // VDD_SPI regulator tie high to vdda,
};
static const esp_efuse_desc_t VDD_SPI_FORCE[] = {
{EFUSE_BLK0, 70, 1}, // Force using eFuse configuration of VDD_SPI,
};
static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
{EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold,
};
static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
{EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable,
};
static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
{EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key,
};
static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
{EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key,
};
static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
{EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key,
};
static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
{EFUSE_BLK0, 88, 4}, // Key0 purpose,
};
static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
{EFUSE_BLK0, 92, 4}, // Key1 purpose,
};
static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
{EFUSE_BLK0, 96, 4}, // Key2 purpose,
};
static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
{EFUSE_BLK0, 100, 4}, // Key3 purpose,
};
static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
{EFUSE_BLK0, 104, 4}, // Key4 purpose,
};
static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
{EFUSE_BLK0, 108, 4}, // Key5 purpose,
};
static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
{EFUSE_BLK0, 116, 1}, // Secure boot enable,
};
static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
{EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke,
};
static const esp_efuse_desc_t FLASH_TPUW[] = {
{EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms,
};
static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
{EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7,
};
static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = {
{EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4,
};
static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = {
{EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1,
};
static const esp_efuse_desc_t FLASH_ECC_MODE[] = {
{EFUSE_BLK0, 131, 1}, // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode,
};
static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = {
{EFUSE_BLK0, 132, 1}, // Disable download through USB,
};
static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
{EFUSE_BLK0, 133, 1}, // Enable security download mode,
};
static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
{EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.,
};
static const esp_efuse_desc_t PIN_POWER_SELECTION[] = {
{EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.,
};
static const esp_efuse_desc_t FLASH_TYPE[] = {
{EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line,
};
static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
{EFUSE_BLK0, 138, 2}, // Sets the size of flash page,
};
static const esp_efuse_desc_t FLASH_ECC_EN[] = {
{EFUSE_BLK0, 140, 1}, // Enables ECC in Flash boot mode,
};
static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
{EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot,
};
static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
{EFUSE_BLK1, 24, 8}, // Factory MAC addr [2],
{EFUSE_BLK1, 16, 8}, // Factory MAC addr [3],
{EFUSE_BLK1, 8, 8}, // Factory MAC addr [4],
{EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
{EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
{EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
{EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
{EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
{EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
{EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
{EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
{EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
{EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
{EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 4}, // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version 0:No calibration 1:With calibration,
};
static const esp_efuse_desc_t SYS_DATA_PART0[] = {
{EFUSE_BLK1, 126, 66}, // System configuration,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 132, 3}, // Version of BLOCK2,
};
static const esp_efuse_desc_t USER_DATA[] = {
{EFUSE_BLK3, 0, 256}, // User data,
};
static const esp_efuse_desc_t KEY0[] = {
{EFUSE_BLK4, 0, 256}, // Key0 or user data,
};
static const esp_efuse_desc_t KEY1[] = {
{EFUSE_BLK5, 0, 256}, // Key1 or user data,
};
static const esp_efuse_desc_t KEY2[] = {
{EFUSE_BLK6, 0, 256}, // Key2 or user data,
};
static const esp_efuse_desc_t KEY3[] = {
{EFUSE_BLK7, 0, 256}, // Key3 or user data,
};
static const esp_efuse_desc_t KEY4[] = {
{EFUSE_BLK8, 0, 256}, // Key4 or user data,
};
static const esp_efuse_desc_t KEY5[] = {
{EFUSE_BLK9, 0, 256}, // Key5 or user data,
};
static const esp_efuse_desc_t SYS_DATA_PART2[] = {
{EFUSE_BLK10, 0, 256}, // System configuration,
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
&WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = {
&WR_DIS_DIS_RTC_RAM_BOOT[0], // Write protection for DIS_RTC_RAM_BOOT
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
&WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
&WR_DIS_GROUP_2[0], // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
&WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
&WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
&WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
&WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
&WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
&WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
&WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
&WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
&WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
&WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
&WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
&WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
&WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
&WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
&WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
&WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
&WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
&WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
&WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
&WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
&WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
&WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
&WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
&WR_DIS_USB_EXCHG_PINS[0], // Write protection for USB_EXCHG_PINS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
&RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
&RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
&RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
&RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
&RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
&RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
&RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = {
&DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
&DIS_ICACHE[0], // Disable Icache
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = {
&DIS_DCACHE[0], // Disable Dcace
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = {
&DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode include boot_mode 0 1 2 3 6 7
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = {
&DIS_DOWNLOAD_DCACHE[0], // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
&DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
&DIS_USB[0], // Disable USB function
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
&DIS_CAN[0], // Disable CAN function
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[] = {
&DIS_APP_CPU[0], // Disables APP CPU
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
&SOFT_DIS_JTAG[0], // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = {
&HARD_DIS_JTAG[0], // Hardware disable jtag permanently disable jtag function
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
&DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encrypt function
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
&USB_EXCHG_PINS[0], // Exchange D+ D- pins
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = {
&USB_EXT_PHY_ENABLE[0], // Enable external PHY
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = {
&BTLC_GPIO_ENABLE[0], // Enables BTLC GPIO
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = {
&VDD_SPI_XPD[0], // VDD_SPI regulator power up
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = {
&VDD_SPI_TIEH[0], // VDD_SPI regulator tie high to vdda
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = {
&VDD_SPI_FORCE[0], // Force using eFuse configuration of VDD_SPI
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
&WDT_DELAY_SEL[0], // Select RTC WDT time out threshold
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
&SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
&SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
&SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
&SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
&KEY_PURPOSE_0[0], // Key0 purpose
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
&KEY_PURPOSE_1[0], // Key1 purpose
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
&KEY_PURPOSE_2[0], // Key2 purpose
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
&KEY_PURPOSE_3[0], // Key3 purpose
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
&KEY_PURPOSE_4[0], // Key4 purpose
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
&KEY_PURPOSE_5[0], // Key5 purpose
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
&SECURE_BOOT_EN[0], // Secure boot enable
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
&SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
&FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
&DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = {
&DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = {
&UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = {
&FLASH_ECC_MODE[0], // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = {
&DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
&ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
&UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = {
&PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
&FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
&FLASH_PAGE_SIZE[0], // Sets the size of flash page
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
&FLASH_ECC_EN[0], // Enables ECC in Flash boot mode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
&FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
&SECURE_VERSION[0], // Secure version for anti-rollback
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
&MAC_FACTORY[2], // Factory MAC addr [2]
&MAC_FACTORY[3], // Factory MAC addr [3]
&MAC_FACTORY[4], // Factory MAC addr [4]
&MAC_FACTORY[5], // Factory MAC addr [5]
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
&SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
&SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
&SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
&SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
&SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
&SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
&SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
&SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
&SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
&SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
&SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version 0:A
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version 0:No calibration 1:With calibration
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = {
&SYS_DATA_PART0[0], // System configuration
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
&OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
&USER_DATA[0], // User data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
&KEY0[0], // Key0 or user data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
&KEY1[0], // Key1 or user data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
&KEY2[0], // Key2 or user data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
&KEY3[0], // Key3 or user data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
&KEY4[0], // Key4 or user data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
&KEY5[0], // Key5 or user data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
&SYS_DATA_PART2[0], // System configuration
NULL
};

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components/efuse/esp32s3/esp_efuse_table.csv
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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
# | (EFUSE_BLK0 | (0..255) | (1..256) | #
# | EFUSE_BLK1 | | | #
# | ... | | | #
# | EFUSE_BLK10)| | | #
##########################################################################
# !!!!!!!!!!! #
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# EFUSE_RD_REPEAT_DATA BLOCK #
##############################
# EFUSE_RD_WR_DIS_REG #
# EFUSE_WR_DIS [WR_DIS 0 32] #
WR_DIS_RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
WR_DIS_DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT
WR_DIS_GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS_GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
WR_DIS_SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
WR_DIS_SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
WR_DIS_SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
WR_DIS_SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
WR_DIS_KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
WR_DIS_KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
WR_DIS_KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
WR_DIS_KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
WR_DIS_KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
WR_DIS_KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
WR_DIS_SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS_GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
WR_DIS_BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
WR_DIS_SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
WR_DIS_USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
WR_DIS_KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
WR_DIS_KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
WR_DIS_KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
WR_DIS_KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
WR_DIS_KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
WR_DIS_KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
WR_DIS_SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
WR_DIS_USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS
# EFUSE_RD_REPEAT_DATA0_REG #
# [RD_DIS 0 7] #
RD_DIS_KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
RD_DIS_KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
RD_DIS_KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
RD_DIS_KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
RD_DIS_KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
RD_DIS_KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
RD_DIS_SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
DIS_APP_CPU, EFUSE_BLK0, 47, 1, Disables APP CPU
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral
HARD_DIS_JTAG, EFUSE_BLK0, 51, 1, Hardware disable jtag permanently disable jtag function
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, Enable external PHY
BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enables BTLC GPIO
# EFUSE_RD_REPEAT_DATA1_REG #
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
# EFUSE_RD_REPEAT_DATA2_REG #
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
# EFUSE_RD_REPEAT_DATA3_REG #
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1
FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line
FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Sets the size of flash page
FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
# EFUSE_RD_REPEAT_DATA4_REG #
# MAC_SPI_8M_SYS BLOCK#
#######################
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
PKG_VERSION, EFUSE_BLK1, 117, 4, Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32
BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version 0:No calibration 1:With calibration
SYS_DATA_PART0, EFUSE_BLK1, 126, 66, System configuration
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2
################
USER_DATA, EFUSE_BLK3, 0, 256, User data
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
Can't render this file because it contains an unexpected character in line 8 and column 53.

24
components/efuse/esp32s3/include/esp_efuse_table.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -16,6 +16,14 @@
extern "C" {
#endif
// md5_digest_table 6a29c09c943d9cb07bd874af57b5870e
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
// To show efuse_table run the command 'show_efuse_table'.
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
@ -59,12 +67,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[];
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[];
@ -85,12 +94,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TINY_BASIC[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
@ -105,9 +116,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];

8
components/efuse/include/esp32s3/esp_efuse.h
View File

@ -56,6 +56,14 @@ typedef enum {
EFUSE_BLK_MAX
} esp_efuse_block_t;
struct esp_efuse_desc_s;
/**
* @brief Given a key block in the range EFUSE_BLK_KEY0..EFUSE_BLK_KEY5, return
* efuse field for setting the key purpose
*/
const struct esp_efuse_desc_s **esp_efuse_get_purpose_field(esp_efuse_block_t block);
/**
* @brief Type of coding scheme
*/

92
components/efuse/src/esp32s3/esp_efuse_api.c
View File

@ -11,3 +11,95 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_efuse.h"
#include "esp_efuse_utility.h"
#include "soc/efuse_periph.h"
#include "assert.h"
#include "sdkconfig.h"
#include "esp_efuse_table.h"
const static char *TAG = "efuse";
// Sets a write protection for the whole block.
esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk)
{
if (blk == EFUSE_BLK1) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK1, 1);
} else if (blk == EFUSE_BLK2) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART1, 1);
} else if (blk == EFUSE_BLK3) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_USER_DATA, 1);
} else if (blk == EFUSE_BLK4) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY0, 1);
} else if (blk == EFUSE_BLK5) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY1, 1);
} else if (blk == EFUSE_BLK6) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY2, 1);
} else if (blk == EFUSE_BLK7) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY3, 1);
} else if (blk == EFUSE_BLK8) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY4, 1);
} else if (blk == EFUSE_BLK9) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY5, 1);
} else if (blk == EFUSE_BLK10) {
return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART2, 1);
}
return ESP_ERR_NOT_SUPPORTED;
}
// read protect for blk.
esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk)
{
if (blk == EFUSE_BLK4) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY0, 1);
} else if (blk == EFUSE_BLK5) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY1, 1);
} else if (blk == EFUSE_BLK6) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY2, 1);
} else if (blk == EFUSE_BLK7) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY3, 1);
} else if (blk == EFUSE_BLK8) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY4, 1);
} else if (blk == EFUSE_BLK9) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY5, 1);
} else if (blk == EFUSE_BLK10) {
return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_SYS_DATA_PART2, 1);
}
return ESP_ERR_NOT_SUPPORTED;
}
// get efuse coding_scheme.
esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk)
{
esp_efuse_coding_scheme_t scheme;
if (blk == EFUSE_BLK0) {
scheme = EFUSE_CODING_SCHEME_NONE;
} else {
scheme = EFUSE_CODING_SCHEME_RS;
}
ESP_EARLY_LOGD(TAG, "coding scheme %d", scheme);
return scheme;
}
const esp_efuse_desc_t **esp_efuse_get_purpose_field(esp_efuse_block_t block)
{
switch(block) {
case EFUSE_BLK_KEY0:
return ESP_EFUSE_KEY_PURPOSE_0;
case EFUSE_BLK_KEY1:
return ESP_EFUSE_KEY_PURPOSE_1;
case EFUSE_BLK_KEY2:
return ESP_EFUSE_KEY_PURPOSE_2;
case EFUSE_BLK_KEY3:
return ESP_EFUSE_KEY_PURPOSE_3;
case EFUSE_BLK_KEY4:
return ESP_EFUSE_KEY_PURPOSE_4;
case EFUSE_BLK_KEY5:
return ESP_EFUSE_KEY_PURPOSE_5;
default:
return NULL;
}
}

63
components/efuse/src/esp32s3/esp_efuse_fields.c
View File

@ -11,3 +11,66 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_efuse.h"
#include "esp_efuse_utility.h"
#include "esp_efuse_table.h"
#include "stdlib.h"
#include "esp_types.h"
#include "assert.h"
#include "esp_err.h"
#include "esp_log.h"
#include "soc/efuse_periph.h"
#include "bootloader_random.h"
#include "sys/param.h"
const static char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
// should return the same value as bootloader_common_get_chip_revision()
uint32_t chip_ver = 0;
// TODO: ESP32S2 does not have this field
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{
uint32_t pkg_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, 4);
return pkg_ver;
}
void esp_efuse_write_random_key(uint32_t blk_wdata0_reg)
{
uint32_t buf[8];
uint8_t raw[24];
bootloader_fill_random(buf, sizeof(buf));
ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg);
for (int i = 0; i < 8; i++) {
ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]);
REG_WRITE(blk_wdata0_reg + 4*i, buf[i]);
}
bzero(buf, sizeof(buf));
bzero(raw, sizeof(raw));
}
esp_err_t esp_efuse_disable_rom_download_mode(void)
{
return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
}
esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
{
if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
return ESP_ERR_INVALID_STATE;
}
return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
}

125
components/efuse/src/esp32s3/esp_efuse_utility.c
View File

@ -11,3 +11,128 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp_efuse_utility.h"
#include "soc/efuse_periph.h"
#include "esp32s3/clk.h"
#include "esp_log.h"
#include "assert.h"
#include "sdkconfig.h"
#include <sys/param.h>
#include "esp32s3/rom/efuse.h"
static const char *TAG = "efuse";
#ifdef CONFIG_EFUSE_VIRTUAL
extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK];
#endif // CONFIG_EFUSE_VIRTUAL
/*Range addresses to read blocks*/
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
{EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
};
static uint32_t write_mass_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
/*Range addresses to write blocks (it is not real regs, it is buffer) */
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
};
#ifndef CONFIG_EFUSE_VIRTUAL
// Update Efuse timing configuration
static esp_err_t esp_efuse_set_timing(void)
{
uint32_t clock_hz = esp_clk_apb_freq();
return ets_efuse_set_timing(clock_hz) ? ESP_FAIL : ESP_OK;
}
#endif // ifndef CONFIG_EFUSE_VIRTUAL
// Efuse read operation: copies data from physical efuses to efuse read registers.
void esp_efuse_utility_clear_program_registers(void)
{
ets_efuse_read();
ets_efuse_clear_program_registers();
}
// Burn values written to the efuse write registers
void esp_efuse_utility_burn_efuses(void)
{
#ifdef CONFIG_EFUSE_VIRTUAL
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
int subblock = 0;
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
}
}
#else
if (esp_efuse_set_timing() != ESP_OK) {
ESP_LOGE(TAG, "Efuse fields are not burnt");
} else {
// Permanently update values written to the efuse write registers
for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
if (REG_READ(addr_wr_block) != 0) {
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
uint8_t block_rs[12];
ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
}
int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
ets_efuse_program(num_block);
break;
}
}
}
}
#endif // CONFIG_EFUSE_VIRTUAL
esp_efuse_utility_reset();
}
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
// They will be filled during the burn operation.
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
{
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
if (REG_READ(addr_wr_block)) {
int num_reg = 0;
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
if (esp_efuse_utility_read_reg(num_block, num_reg)) {
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
return ESP_ERR_CODING;
}
}
break;
}
}
}
}
return ESP_OK;
}

16
components/efuse/test/test_efuse.c
View File

@ -19,8 +19,6 @@
#include "esp_rom_efuse.h"
#include "bootloader_common.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
static const char* TAG = "efuse_test";
static void test_read_blob(void)
@ -538,7 +536,7 @@ TEST_CASE("Test esp_efuse_read_block esp_efuse_write_block functions", "[efuse]"
printf("EFUSE_CODING_SCHEME_REPEAT\n");
count_useful_reg = 4;
}
#elif CONFIG_IDF_TARGET_ESP32S2
#else
if (coding_scheme == EFUSE_CODING_SCHEME_RS) {
printf("EFUSE_CODING_SCHEME_RS\n");
count_useful_reg = 8;
@ -601,7 +599,7 @@ TEST_CASE("Test Bits are not empty. Write operation is forbidden", "[efuse]")
printf("EFUSE_CODING_SCHEME_REPEAT\n");
count_useful_reg = 4;
}
#elif CONFIG_IDF_TARGET_ESP32S2
#else
if (coding_scheme == EFUSE_CODING_SCHEME_RS) {
printf("EFUSE_CODING_SCHEME_RS\n");
if (num_block == EFUSE_BLK1) {
@ -769,7 +767,7 @@ TEST_CASE("Test a write/read protection", "[efuse]")
test_rp(EFUSE_BLK1, ESP_EFUSE_RD_DIS_BLK1, true);
test_rp(EFUSE_BLK2, ESP_EFUSE_RD_DIS_BLK2, false);
test_rp(EFUSE_BLK3, ESP_EFUSE_RD_DIS_BLK3, false);
#elif defined(CONFIG_IDF_TARGET_ESP32S2)
#else
test_wp(EFUSE_BLK2, ESP_EFUSE_WR_DIS_SYS_DATA_PART1);
test_wp(EFUSE_BLK3, ESP_EFUSE_WR_DIS_USER_DATA);
@ -778,8 +776,6 @@ TEST_CASE("Test a write/read protection", "[efuse]")
test_rp(EFUSE_BLK4, ESP_EFUSE_RD_DIS_KEY0, true);
test_rp(EFUSE_BLK5, ESP_EFUSE_RD_DIS_KEY1, false);
test_rp(EFUSE_BLK6, ESP_EFUSE_RD_DIS_KEY2, false);
#else
#error New chip not supported!
#endif
esp_efuse_utility_debug_dump_blocks();
@ -811,7 +807,7 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]")
TEST_ASSERT_EQUAL_HEX8_ARRAY(new_mac, mac, sizeof(new_mac));
esp_efuse_utility_debug_dump_blocks();
}
#ifdef CONFIG_IDF_TARGET_ESP32S2
#ifndef CONFIG_IDF_TARGET_ESP32
ESP_LOGI(TAG, "2. Write KEY3");
uint8_t key[32] = {0};
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
@ -834,7 +830,7 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]")
TEST_ASSERT_EQUAL_INT(0, key[i]);
}
esp_efuse_utility_debug_dump_blocks();
#endif // CONFIG_IDF_TARGET_ESP32S2
#endif // not CONFIG_IDF_TARGET_ESP32
ESP_LOGI(TAG, "4. Write SECURE_VERSION");
int max_bits = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION);
size_t read_sec_version;
@ -860,5 +856,3 @@ TEST_CASE("Test chip_revision APIs return the same value", "[efuse]")
esp_efuse_utility_update_virt_blocks();
TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision());
}
#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)

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components/soc/soc/esp32s3/include/soc/efuse_reg.h
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