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513 Commits

Author SHA1 Message Date
Jiang Jiang Jian
2bc5d58807 Merge branch 'feature/support_sleep_for_esp32c2' into 'master' 
esp32c2: support power management

Closes IDF-4440 and IDF-4617

See merge request espressif/esp-idf!18174
 2022-05-30 17:57:18 +08:00
jingli
93a5087e58 add PM related soc caps about power down rtc slow/fast mem 
Supporting rtc slow/fast mem does not mean supporting
rtc slow/fast mem power down.
 2022-05-30 15:26:50 +08:00
Jiang Jiang Jian
0e94779b2e Merge branch 'feature/support_esp32c2_wifi_new' into 'master' 
Bringup ESP32C2 Wi-Fi

Closes IDF-3905

See merge request espressif/esp-idf!18136
 2022-05-29 18:25:24 +08:00
Jiang Jiang Jian
f3922f1b7f Merge branch 'feature/flash_mmap_refactor' into 'master' 
flash mmap: abstract R/W of MMU table instead of reg access

See merge request espressif/esp-idf!16882
 2022-05-29 13:56:37 +08:00
Jessy Chen
7b9b448041 esp_wifi: optimize wifi kconfig 2022-05-28 08:52:55 +00:00
jingli
ae127b04cd fix ld err since esp32c2 do not suport config gpio of spi flash via efuse 2022-05-27 19:29:38 +08:00
Song Ruo Jing
cf32e49aeb Merge branch 'refactor/cleanup_rtc_h' into 'master' 
clk_tree: Prework2 of introducing clock subsystem control

Closes IDF-4934

See merge request espressif/esp-idf!17861
 2022-05-26 09:16:47 +08:00
songruojing
74c99a8a07 rtc_clk: Add alias for the clock tree related enum and macros for backwards compatibility 2022-05-24 22:59:51 +08:00
songruojing
729d70129a clk_tree: add initial docs for clock tree 2022-05-24 22:59:51 +08:00
morris
b26cd91537 doc: added clk_tree definitions to doc 2022-05-24 22:59:51 +08:00
songruojing
a5b09cf015 rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in 
soc/clk_tree_defs.h
 2022-05-24 22:59:41 +08:00
laokaiyao
a5f651ad71 i2s: Update FIFO direct access reg on ESP32 according to the TRM 
Closes: https://www.github.com/espressif/esp-idf/issues/8862
 2022-05-23 16:28:42 +08:00
jiangguangming
42bc0b0643 soc: remove unused MMU related macros 2022-05-20 16:46:28 +08:00
jiangguangming
9c6afee12f flash mmap: abstract R/W MMU table instead of reg access 2022-05-20 16:46:27 +08:00
Michael (XIAO Xufeng)
adcdcbaa0e Merge branch 'feat/pm_dbias_refactoring' into 'master' 
pm: refactoring dbias related code

See merge request espressif/esp-idf!17994
 2022-05-17 14:42:16 +08:00
Michael (XIAO Xufeng)
6f507d527c rtc: fixed 8MD256 can't be used as RTC slow src on ESP32 
Sync configuration from other chips

Closes: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089
 2022-05-14 22:35:41 +08:00
Michael (XIAO Xufeng)
234628b3ea pm: putting dbias and pd_cur code into same function 2022-05-14 02:35:11 +08:00
Jing Li
ac0d16cdc8 Merge branch 'bugfix/fix_cannot_lslp_again_after_ulp_wakeup' into 'master' 
sleep: fix cannot lightsleep again after a wakeup from ULP

Closes IDFGH-4396

See merge request espressif/esp-idf!17970
 2022-05-13 22:25:23 +08:00
jingli
abb6bb1181 esp_hw_support/sleep: fix cannot enable sleep reject in some cases 
When enable sleep reject before this fix, we have two limitations:
1. it must be light sleep
2. RTC GPIO wakeup source must be set

We require light sleep because `esp_deep_sleep_start` function has
been declared with "noreturn" attribute, So developers don't expect
that this function may return (due to an error or a sleep reject).
But the requirement for RTC GPIO wakeup source is not reasonable for
all chips. This requirement exists because ESP32 only supports RTC GPIO
and SDIO sleep reject sources. But later chips support all sleep reject
sources.

This fix brings the following changes:
for ESP32: RTC GPIO and SDIO sleep reject sources can be enabled
           when corresponding wakeup source is set.

for later chips: all sleep reject sources can be enabled when
                 corresponding wakeup source is set.
 2022-05-12 19:09:57 +08:00
Marius Vikhammer
c8617fe965 docs: fix all doxygen warnings 
Doxygen warnings would previously not result in a failed pipeline.
Fixed this as well as all current warnings.
 2022-05-12 14:50:03 +08:00
Michael (XIAO Xufeng)
2905cbbe03 pm: fixed RTC8M domain power issues 
introduced in e44ead5356

1. The int8M power domain config by default is PD. While LEDC is using
RTC8M as clock source, this power domain will be kept on.

But when 8MD256 is used as RTC clock source, the power domain should
also be kept on.

On ESP32, there was protection for it, but broken by commit
e44ead5356. Currently the power domain
will be forced on when LEDC is using RTC8M as clock source &&
!int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise
the power domain will be powered off, regardless of RTC clock source.

In other words, int8M domain will be forced off (even when 8MD256
used as RTC clock source) if LEDC not using RTC8M as clock source, user
doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep.

On later chips, there's no such protection, so 8MD256 could't be used as
RTC clock source in sleep modes.

This commit adds protection of 8MD256 clock to other chips. Fixes the
incorrect protection logic overriding on ESP32. Now the power domain
will be determiend by the logic below (order by priority):

    1. When RTC clock source uses 8MD256, power up
    2. When LEDC uses RTC8M clock source, power up
    3. In deepsleep, power down
    4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M,
       power down by default. (This is preferred to have highest
       priority, but it's kept as is because of current code structure.)

2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the
protection above may force the int8m PU. This may cause the inconsistent
of dbias and the int8m PU status.

This commit lifts the logic of pd int8m/xtal fpu logic to upper layer
(sleep_modes.c).

Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089

temp
 2022-05-11 11:30:47 +08:00
morris
523c51818c Merge branch 'feature/c2_soc_hwsupport_code' into 'master' 
ESP32-C2 (729) RTC update (Clock, PM)

Closes IDF-3833 and IDF-4874

See merge request espressif/esp-idf!17311
 2022-05-11 11:23:57 +08:00
zlq
6336f8191e C2 rtc code 2022-05-09 17:50:54 +08:00
morris
722fde218d uart: add default source clock for all targets 2022-05-09 11:26:30 +08:00
Armando
49747bb486 adc: create common adc hal layer 2022-05-07 19:20:44 +08:00
Armando (Dou Yiwen)
76be0c2624 Merge branch 'bugfix/fix_esp32_mmu_init_issue' into 'master' 
mmu: add ll functions for mmu unmap

Closes OCD-526 and IDF-4962

See merge request espressif/esp-idf!17868
 2022-05-05 22:21:18 +08:00
Armando
b748a4fe5e mmu: improve vaddr range check 2022-04-27 11:35:07 +08:00
Armando
e09787d851 mmu: fix macro MMU_ENTRY_NUM and add new macro MMU_MAX_PADDR_PAGE_NUM 2022-04-27 11:35:07 +08:00
Armando
2764cd5682 mmu: simplify mmu_hal_init 2022-04-27 11:35:07 +08:00
jiangguangming
63ac5e4a99 mmu: add ll func used to invalidate the mmu entry 2022-04-27 11:35:07 +08:00
Cao Sen Miao
4418a855ba spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2 2022-04-26 15:22:37 +08:00
Marius Vikhammer
45c1d1cba2 Merge branch 'feature/move_target_kconfig_2' into 'master' 
system: move kconfig options out of target component

See merge request espressif/esp-idf!17321
 2022-04-24 13:29:43 +08:00
morris
4280164be4 rmt: add more clock source caps 2022-04-21 13:59:47 +00:00
Marius Vikhammer
d2872095f9 soc: moved kconfig options out of the target component. 
Moved the following kconfig options out of the target component:
 * CONFIG_ESP*_DEFAULT_CPU_FREQ* -> esp_system
 * ESP*_REV_MIN -> esp_hw_support
 * ESP*_TIME_SYSCALL -> newlib
 * ESP*_RTC_* -> esp_hw_support

Where applicable these target specific konfig names were merged into
a single common config, e.g;
CONFIG_ESP*_DEFAULT_CPU_FREQ -> CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
 2022-04-21 12:09:43 +08:00
morris
373d9b3dbc Merge branch 'feature/default_clk_for_gptimer' into 'master' 
clk_tree: added default clock source for peripherals (GPTimer, RMT, LCD, TempSensor)

Closes IDF-4894

See merge request espressif/esp-idf!17759
 2022-04-19 18:02:40 +08:00
songruojing
534346f4bb ledc: Provide support for esp32c2 and esp32h2 
LEDC examples, unit test, and programming guide are all updated.
 2022-04-14 08:15:14 +00:00
morris
f32a89826c clk_tree: added default clock source for peripheral 2022-04-14 15:44:56 +08:00
songruo
60bb5c913d clk_tree: prework of introducing clk subsystem control 
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
   upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
   Modify the NGed drivers to adopt new clock ids
 2022-04-11 12:09:06 +08:00
Mahavir Jain
74005ed2f5 soc: add capability macros for security features 
- Security features covers "secure boot", "flash encryption" etc.
- ECO revision specific modifications still need to be handled
through kconfig itself, as soc_caps.h is processed before ECO revision
selection
- This will simplify addition of security features for newer chips by
using these SOC capability macros
 2022-04-01 09:38:34 +00:00
Armando
fe9c6cde4f spi: support spi on h2 2022-03-29 11:54:08 +08:00
Kevin (Lao Kaiyao)
ba9d3fe819 Merge branch 'refactor/i2s_major_refactoring_for_ng' into 'master' 
🔨i2s: Major refactoring for driver-NG

Closes IDF-4781 and IDF-4779

See merge request espressif/esp-idf!17484
 2022-03-23 15:32:46 +08:00
laokaiyao
f17edba20b i2s: extract std/pdm/tdm modes 
Type structures of these modes are defined. Driver and HAL layer are modified to fit these concepts.
 2022-03-22 10:14:45 +08:00
Mahavir Jain
bcc4883c25 soc: add capability macros for crypto peripherals 
Closes IDF-4790
 2022-03-22 02:06:30 +00:00
Armando (Dou Yiwen)
36457b1346 Merge branch 'refactor/adc_unify_adc_unit' into 'master' 
adc: adc single driver NG pre-step - unify adc_ll_num_t and adc_unit_t

See merge request espressif/esp-idf!17408
 2022-03-18 20:29:36 +08:00
Armando
386363cafd adc: unify adc_ll_num_t and adc_unit_t 2022-03-18 11:36:50 +08:00
Jiang Jiang Jian
10f3aba770 Merge branch 'feature/final_h2' into 'master' 
Add support in Nimble for ESP32H2

See merge request espressif/esp-idf!16329
 2022-03-15 16:03:24 +08:00
Rahul Tank
f376bb5d05 Add support in Nimble for ESP32H2 2022-03-14 11:57:53 +05:30
morris
9422fe077a lcd: support I2S1 LCD mode on esp32 2022-03-14 13:55:01 +08:00
Michael (XIAO Xufeng)
aab535fe4a Merge branch 'bugfix/regi2c_ctrl_spinlock_s2' into 'master' 
hw_support: fixed regi2c not protected by lock on ESP32S2

See merge request espressif/esp-idf!16653
 2022-03-13 02:47:53 +08:00
Michael (XIAO Xufeng)
d5bdf95580 hw_support: fixed regi2c not protected by lock on ESP32S2 2022-03-13 00:24:08 +08:00
Armando (Dou Yiwen)
6ed3ffbbf1 Merge branch 'refactor/remove_redundant_rom_cache_dependency' into 'master' 
cache: remove redundant rom cache dependency in bootloader

Closes IDF-4523

See merge request espressif/esp-idf!17077
 2022-03-12 10:11:39 +08:00
Armando
c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
Dai Zi Yan
1462367eeb Merge branch 'docs/translate_coexist' into 'master' 
docs/ translate coexist

Closes DOC-2479

See merge request espressif/esp-idf!16830
 2022-03-10 10:59:18 +08:00
morris
9f55712c03 rmt: document and improve LL driver 2022-03-09 10:58:12 +08:00
xiongweichao
6514f9e94c docs: translate coexist from CN to EN 2022-03-09 02:50:00 +00:00
morris
ec8defaa96 pulse_cnt: new driver for PCNT peripheral 2022-03-03 22:38:32 +08:00
Michael (XIAO Xufeng)
78165c541e Merge branch 'bugfix/bootloader_uart_custom_gpio' into 'master' 
bootloader: fixed the issue custom_uart_gpio doesn't take effect

Closes IDF-4606

See merge request espressif/esp-idf!16910
 2022-03-02 02:35:14 +08:00
songruojing
d4334cc109 uart: fixed incorrect channel number on ESP32S2, S3 and C3 2022-03-01 18:21:27 +08:00
KonstantinKondrashov
7d097511fa soc: Fix efuse_hal_get_chip_revision for esp32 2022-03-01 16:55:43 +08:00
Kevin (Lao Kaiyao)
cc1d89ebba Merge branch 'feature/i2c_support_on_esp8684_esp32h2' into 'master' 
i2c: support i2c on esp32c2 and esp32h2

Closes IDF-3918

See merge request espressif/esp-idf!16444
 2022-02-28 13:59:02 +08:00
Konstantin Kondrashov
44e5ac2c59 Merge branch 'feature/efuse_hal' into 'master' 
hal: Adds efuse hal layer

See merge request espressif/esp-idf!16354
 2022-02-28 13:38:43 +08:00
KonstantinKondrashov
9605f3eb1a soc: Adds efuse hal 
Replaced eFuse ROM funcs with hal layer
 2022-02-24 22:20:09 +08:00
laokaiyao
7da023ceae i2c: support esp32c2 2022-02-23 15:19:37 +08:00
morris
116197040f i2s: update copyright 2022-02-21 21:28:48 +08:00
Zim Kalinowski
67f51a4ce5 Merge branch 'bugfix/riscv_i2c_description' into 'master' 
i2c: fix the controller count in the header description

Closes IDFGH-6476

See merge request espressif/esp-idf!16718
 2022-01-26 03:13:07 +00:00
Omar Chebib
bb730292d4 i2c: fix the controller count in the header description 
Closes https://github.com/espressif/esp-idf/issues/8133
 2022-01-13 18:25:41 +08:00
Armando
6a74cb695d spi: support spi on 8684 2022-01-12 11:30:29 +08:00
morris
24acdf23ee soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
morris
8cdcb4e291 rmt: move RMT item definition from soc to driver 2022-01-06 21:43:12 +08:00
laokaiyao
4f28b33bbc apll: add lock for apll 2021-12-29 10:13:13 +08:00
laokaiyao
af4e448928 i2s: impove the clock division calculation 
Reported from: https://esp32.com/viewtopic.php?f=25&t=24542&p=87595#p87595
 2021-12-29 10:13:13 +08:00
morris
b170aba93a timer: fix wrong kconfig soc caps 2021-12-23 11:39:32 +08:00
Marius Vikhammer
82325f6037 docs: update docs to be able to build with esp8684 2021-12-20 10:32:49 +08:00
Armando
4dc0d6b2fe adc: support adc dma driver on all chips 2021-12-16 00:19:15 +00:00
Cao Sen Miao
e81841318f CI: Enable ESP8684 build stage CI on master 2021-12-13 19:18:47 +08:00
Marius Vikhammer
c6d60615c6 build-system: include soc_caps defines into kconfig 
Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into
a format that can be included in kconfig.
 2021-12-06 12:37:07 +08:00
Cao Sen Miao
ce1ee3d8ae psram: add ESP32-D0WD-R2-V3 support 2021-11-12 13:52:24 +08:00
Omar Chebib
aa2ca7dd94 LEDC: improved support for ESP32-C3 and refactored divisor calculation 
As ESP32C3 does not have support for REF_TICK source clock, it is now not
possible to select it anymore.
Auto cfg clock has been improved for all boards.
 2021-11-11 12:21:15 +08:00
morris
83d16aa00c gdma: support IRAM interrupt 2021-11-08 16:14:51 +08:00
Cao Sen Miao
36f6d16b8d ESP8684: add soc, riscv, newlib support 2021-11-06 17:33:44 +08:00
Wei Tian Hua
347e04cf73 Merge branch 'doc/make_classic_bt_API_ref_only_for_esp32' into 'master' 
Doc/Make Classic BT related document links only visible for ESP32

Closes IDFGH-5008, IDFGH-6022, and AUD-3378

See merge request espressif/esp-idf!15635
 2021-10-29 02:27:24 +00:00
weitianhua
0ea06fa336 Remove dummy defines of Classic BT 2021-10-28 19:26:46 +08:00
weitianhua
64aa94d823 Make Classic BT related document links only visible for ESP32 2021-10-27 15:28:47 +08:00
Alexey Gerenkov
111ba5bbe6 trax: Adds ESP32-S3 support 2021-10-22 23:36:28 +03:00
morris
e2275b1f63 gptimer: clean up hal and ll for driver-ng 2021-10-20 18:40:08 +08:00
laokaiyao
f4705f8eb4 touch sensor: update copyright notice 2021-10-08 11:45:57 +08:00
laokaiyao
a1cadba191 touch_sensor: apply general check 2021-10-08 11:32:12 +08:00
fuzhibo
589646a31e update touch with review advice 2021-10-08 10:39:46 +08:00
fuzhibo
057b9d61b5 driver(touch): support touch sensor for esp32s3 platform 2021-10-08 10:39:46 +08:00
Jiang Jiang Jian
f5ae8b0533 Merge branch 'feature/ledc_use_rtc8m_or_xtal_lightsleep' into 'master' 
support RTC8M and XTAL power domain in light sleep mode

Closes IDF-3419

See merge request espressif/esp-idf!15152
 2021-09-27 04:02:29 +00:00
Li Shuai
f5b39a7cde esp_hw_support: No voltage drop during light sleep to ensure stable output clock of rtc8m oscillator 2021-09-16 14:40:46 +08:00
Armando
c45c6f52f1 adc: support adc efuse-based calibration on esp32s3 2021-09-14 11:42:50 +08:00
Li Shuai
e44ead5356 Power Management: add RTC8M power domain to control whether internal 8m oscillator is powered down during sleep 2021-09-13 17:36:54 +08:00
morris
9d97d01679 Merge branch 'bugfix/mcpwm_cpp_reserved_word' into 'master' 
bugfix/mcpwm: rename invalid keyword 'operator'

Closes IDFGH-5840

See merge request espressif/esp-idf!15159
 2021-09-13 03:10:04 +00:00
SalimTerryLi
d9f4ae02f1
mcpwm: rename keyword 'operator' which is not valid in cpp 
Closes https://github.com/espressif/esp-idf/issues/7542
 2021-09-10 12:41:42 +08:00
baohongde
006a10b050 components/doc: Update doc about high-level interrupt 
some bugfix.
 2021-09-09 20:40:09 +08:00
baohongde
6d63fe06fa components/os: add config option to choose system check intterupt level. 2021-09-09 11:29:12 +08:00
baohongde
d1db2df316 components/bt: High level interrupt in bluetooth 
components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt

components/os: high level interrupt(5)

components/os: hli_api: meta queue: fix out of bounds access, check for overflow

components/os: hli: don't spill registers, instead save them to a separate region

Level 4 interrupt has a chance of preempting a window overflow or underflow exception.
Therefore it is not possible to use standard context save functions,
as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4).

Instead, mask window overflows and save the entire general purpose register file,
plus some of the special registers.
Then clear WindowStart, allowing the C handler to execute without spilling the old windows.
On exit from the interrupt handler, do everything in reverse.

components/bt: using high level interrupt in lc

components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory`

components/bt: optimize code structure

components/os: Modify the BT assert process to adapt to coredump and HLI

components/os: Disable exception mode after saving special registers

To store some registers first, avoid stuck due to live lock after disabling exception mode

components/os: using dport instead of AHB in BT to fix live lock

components/bt: Fix hli queue send error

components/bt: Fix CI fail

# Conflicts:
#	components/bt/CMakeLists.txt
#	components/bt/component.mk
#	components/bt/controller/bt.c
#	components/bt/controller/lib
#	components/esp_common/src/int_wdt.c
#	components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S
#	components/soc/esp32/include/soc/soc.h
 2021-09-09 11:29:06 +08:00
laokaiyao
c5afd7ce34 i2s: fix write failure on ESP32 in 32bit slave mode 2021-09-03 17:36:44 +08:00
SalimTerryLi
874a720286
soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one 
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
 2021-08-30 13:50:58 +08:00
Michael (XIAO Xufeng)
375145ecdb Merge branch 'feature/mcpwm_bldc_hall_example' into 'master' 
mcpwm: bldc hall example

Closes IDF-3648

See merge request espressif/esp-idf!14578
 2021-08-26 08:28:27 +00:00
Song Ruo Jing
fe5c87cb3c Merge branch 'bugfix/enable_gpio_20' into 'master' 
gpio: Enable IO20 on ESP32

Closes IDFGH-5140

See merge request espressif/esp-idf!14881
 2021-08-25 07:25:37 +00:00
morris
3bfd8f5d5f mcpwm: update register file according to TRM 2021-08-24 15:38:46 +08:00
Alberto García Hierro
6deaefde69 Enable IO20 on ESP32 
Some newer ESP32 variants (like ESP32-PICO-V3 and ESP32-PICO-MINI-02)
do implement this pin and it can be used as a normal GPIO.

Fixes #6016
Fixes #6837

Closes https://github.com/espressif/esp-idf/pull/6918
 2021-08-20 14:05:38 +08:00
morris
bb87fd8f08 Merge branch 'refactor/pcnt_driver_esp32s3' into 'master' 
pcnt: soc update and hal refactor

See merge request espressif/esp-idf!14698
 2021-08-20 04:23:15 +00:00
morris
1656cee69d i2s: correct soc info 
1. remove non-exist I2S instance
2. update soc_caps.h, i2s_ll.h
 2021-08-10 21:06:59 +08:00
suda-morris
9920271c21 pcnt: update pcnt soc data for all targets 2021-08-10 17:19:21 +08:00
Wang Meng Yang
8652b1d576 Merge branch 'bugfix/btdm_esp32_ble_white_list_connection_fail' into 'master' 
Fixed ESP32 BLE can't resolve the peer address when enable white list

See merge request espressif/esp-idf!14348
 2021-08-09 06:46:08 +00:00
Michael (XIAO Xufeng)
947980ecac Merge branch 'bugfix/uart_set_pin_use_iomux' into 'master' 
uart: uart_set_pin function will now use IOMUX whenever possible

Closes IDF-3183

See merge request espressif/esp-idf!14318
 2021-08-05 04:17:29 +00:00
xiewenxiang
1cc0f6aac5 Fixed ESP32 BLE can't resolve the peer address when enable white list 2021-08-04 22:00:38 +08:00
Omar Chebib
779e7400b0 uart: uart_set_pin function will now use IOMUX whenever possible 
By using IOMUX instead of GPIO Matrix for UART, it is now possible
on ESP32 boards to use the UART as a wake up source even if it is
not used as a console.
For other boards where this issue was not present, using IOMUX has
the advantage to be faster than using GPIO matrix, so a highest
baudrate can be used
 2021-08-04 12:48:30 +08:00
laokaiyao
d51b85989b doc/i2s: update i2s programming guide on s3 & c3 2021-08-04 10:20:03 +08:00
houwenxiang
2f1247e1c4 driver: support I2S on ESP32-S3 & ESP32-C3 
1. refactor I2S driver.
  2. support TDM mode for esp2s3 & esp32c3.
 2021-08-04 10:20:03 +08:00
Konstantin Kondrashov
4972605b16 esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt 2021-08-03 14:35:29 +08:00
morris
88c87bfe56 mcpwm: update hal and soc naming 2021-07-26 22:32:45 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Angus Gratton
0f1b24891b Merge branch 'bugfix/esp32_u4wdh_quad_io' into 'master' 
bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip

Closes IDFGH-4353

See merge request espressif/esp-idf!13111
 2021-06-07 04:50:54 +00:00
Angus Gratton
dc6b950257 doc: Add performance guides for execuion speed, binary size, RAM usage 
Closes https://github.com/espressif/esp-idf/issues/7007
Closes https://github.com/espressif/esp-idf/issues/6715
Closes https://github.com/espressif/esp-idf/issues/3781
Closes https://github.com/espressif/esp-idf/issues/2566
 2021-06-03 13:55:34 +10:00
Ivan Grokhotkov
17c65dad27 soc: add esp32s3 sdmmc support 
* sync the latest struct header file from ESP32
* add soc_caps.h macros to distinguish between IO MUX and GPIO Matrix
  support in SDMMC on different chips.
* store GPIO matrix signal numbers in sdmmc_slot_info_t
 2021-05-10 23:21:27 +02:00
Cao Sen Miao
0d81edb174 spi_flash: refactoring flash encryption into new api 2021-04-25 17:09:25 +08:00
Ivan Grokhotkov
ea7d020f20 Merge branch 'feature/ubsan' into 'master' 
system: add option to enable undefined behavior sanitizer (UBSAN)

Closes IDF-166 and IDF-1824

See merge request espressif/esp-idf!11318
 2021-04-23 09:27:42 +00:00
Ivan Grokhotkov
da90775d98 hal: mpu: fix signed overflow error 2021-04-22 23:33:47 +02:00
Darian Leung
54eb152a96 TWAI: Simply caps and remove unused caps 2021-04-16 18:36:18 +08:00
Angus Gratton
268b23db96 bootloader: Fix selection of Quad I/O modes on ESP32-U4WDH chip 
Closes https://github.com/espressif/esp-idf/issues/6191
 2021-04-12 18:49:17 +10:00
morris
75dfd970b4 dac: added DAC support macro 
Remove DAC support on ESP32-S3
 2021-04-12 12:04:46 +08:00
Armando
9b9ea71ff9 spi: remove HSPI macro on esp32c3 and esp32s3 2021-04-06 13:42:49 +08:00
Michael (XIAO Xufeng)
3a90d51831 Merge branch 'refactor/using_isr_callback_in_timer_example' into 'master' 
TIMG: clean up timer example and add example test

Closes IDF-2722, IDF-2766, and IDF-2347

See merge request espressif/esp-idf!12218
 2021-03-22 06:36:32 +00:00
morris
f5ca47c0fc mcpwm: rename macros related to soc capbility 2021-03-16 21:53:59 +08:00
morris
5a520cacf1 timer_group: correct timer_ll_set_divider 2021-03-16 17:56:37 +08:00
Angus Gratton
fd164b82b6 Merge branch 'refactor/move_from_xtensa' into 'master' 
Movements from xtensa

Closes IDF-2164

See merge request espressif/esp-idf!10556
 2021-03-11 00:24:25 +00:00
Renz Bagaporo
1efdcd69d9 xtensa: move out trax 2021-02-26 19:45:48 +08:00
Xia Xiaotian
f53c0c5b87 esp_wifi: store PHY digital registers before disabling PHY and load 
them after enabling PHY
 2021-02-26 11:29:50 +08:00
morris
7b37158ede rmt: distinguish group and channel in HAL layer 2021-02-25 12:42:23 +08:00
morris
6dc7f95342 mcpwm: fix wrong meta information 2021-02-22 20:23:35 +08:00
Angus Gratton
2ec04b57de soc esp32: Removes parentheses from RTC_MEM_xyz macros that expand directly to single numbers 
Not necessary in these cases, and prevents parens from expanding into the
assembly code such as added in 562ab01046  -
a pattern which is accepted by GCC assembler but illegal syntax for LLVM assembler.

As reported https://github.com/espressif/llvm-project/issues/35#issuecomment-726853574
 2021-02-08 10:08:01 +11:00
Michael (XIAO Xufeng)
d7d1dee208 system: reset dma when soft reset 2021-01-25 04:51:40 +00:00
Angus Gratton
fe8a891de9 Merge branch 'feature/support_esp32c3_master_cmake_secure_boot' into 'master' 
bootloader/esp32c3: Support secure boot

Closes IDF-2115

See merge request espressif/esp-idf!11797
 2021-01-21 08:42:49 +08:00
KonstantinKondrashov
88c5fe49b8 soc: Adds a soc_caps define for all chips to define the number of boot key digests 2021-01-19 20:51:13 +08:00
Li Shuai
aa7fd175b9 light sleep: light sleep support for esp32c3 2021-01-19 14:50:58 +08:00
ninh
27aa6c289f components/pm: Add slp gpio configure workaround 2021-01-15 15:34:45 +08:00
morris
e6d23a35ec gdma: dynamic alloc DMA channels 2021-01-13 10:52:27 +08:00
ninh
dc7bdb9857 adjust lightsleep overhead time and cali slowclk 2021-01-06 03:40:28 +00:00
Marius Vikhammer
eb788deb03 esp_hw_support: merge C3 changes to master 
Merge RTC related C3 changes to master
 2020-12-30 12:20:41 +08:00
Angus Gratton
c3ba995f2c Merge branch 'ci/ccomp_performance_tests' into 'master' 
unit_test: Refactor all performance tests that rely on cache compensated timer

See merge request espressif/esp-idf!11709
 2020-12-24 13:44:52 +08:00
Angus Gratton
fa892eb017 soc: Explain units for rtc_clk_cal() function, fix typo 2020-12-23 09:53:24 +11:00
Cao Sen Miao
e338a2e3df rtc: add function to en/disable the rtc clock 2020-12-23 09:53:24 +11:00
Marius Vikhammer
0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer 
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
 2020-12-22 18:56:24 +11:00
Cao Sen Miao
0736c91d68 soc: Remove cache constants from soc.h 2020-12-17 15:34:13 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer 
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
 2020-12-10 09:04:47 +00:00
Angus Gratton
c29d93986d soc: Add initial ESP32-C3 support 
From internal commit 7761d6e8
 2020-11-30 11:12:56 +11:00