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mcpwm: rename macros related to soc capbility
This commit is contained in:
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be30289364
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f5ca47c0fc
@ -86,7 +86,7 @@ typedef enum {
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MCPWM_UNIT_MAX, /*!<Num of MCPWM units on ESP32*/
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} mcpwm_unit_t;
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_Static_assert(MCPWM_UNIT_MAX == SOC_MCPWM_PERIPH_NUM, "MCPWM unit number not equal to chip capabilities");
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_Static_assert(MCPWM_UNIT_MAX == SOC_MCPWM_GROUPS, "MCPWM unit number not equal to chip capabilities");
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/**
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* @brief Select MCPWM timer
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@ -47,13 +47,14 @@ static const char *MCPWM_TAG = "MCPWM";
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}
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#define MCPWM_DRIVER_INIT_ERROR "MCPWM DRIVER NOT INITIALIZED"
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#define MCPWM_UNIT_NUM_ERROR "MCPWM UNIT NUM ERROR"
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#define MCPWM_GROUP_NUM_ERROR "MCPWM GROUP NUM ERROR"
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#define MCPWM_TIMER_ERROR "MCPWM TIMER NUM ERROR"
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#define MCPWM_CAPTURE_ERROR "MCPWM CAPTURE NUM ERROR"
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#define MCPWM_PARAM_ADDR_ERROR "MCPWM PARAM ADDR ERROR"
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#define MCPWM_DUTY_TYPE_ERROR "MCPWM DUTY TYPE ERROR"
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#define MCPWM_GPIO_ERROR "MCPWM GPIO NUM ERROR"
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#define MCPWM_GEN_ERROR "MCPWM GENERATOR ERROR"
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#define MCPWM_DB_ERROR "MCPWM DEADTIME TYPE ERROR"
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#define MCPWM_DT_ERROR "MCPWM DEADTIME TYPE ERROR"
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#define MCPWM_CLK_PRESCL 15 //MCPWM clock prescale
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#define TIMER_CLK_PRESCALE 9 //MCPWM timer prescales
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@ -62,13 +63,13 @@ static const char *MCPWM_TAG = "MCPWM";
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#define OFFSET_FOR_GPIO_IDX_1 6
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#define OFFSET_FOR_GPIO_IDX_2 75
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_Static_assert(SOC_MCPWM_OP_NUM >= SOC_MCPWM_TIMER_NUM, "This driver assumes the timer num equals to the operator num.");
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_Static_assert(SOC_MCPWM_COMPARATOR_NUM >= SOC_MCPWM_GENERATOR_NUM, "This driver assumes the generator num equals to the generator num.");
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_Static_assert(SOC_MCPWM_GENERATOR_NUM == 2, "This driver assumes the generator num equals to 2.");
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_Static_assert(SOC_MCPWM_OPERATORS_PER_GROUP >= SOC_MCPWM_TIMERS_PER_GROUP, "This driver assumes the timer num equals to the operator num.");
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_Static_assert(SOC_MCPWM_COMPARATORS_PER_OPERATOR >= SOC_MCPWM_GENERATORS_PER_OPERATOR, "This driver assumes the generator num equals to the generator num.");
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_Static_assert(SOC_MCPWM_GENERATORS_PER_OPERATOR == 2, "This driver assumes the generator num equals to 2.");
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#define MCPWM_TIMER_ID_CHECK(mcpwm_num, timer_num) do {\
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MCPWM_CHECK((mcpwm_num) < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG); \
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MCPWM_CHECK((timer_num) < SOC_MCPWM_TIMER_NUM, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG); \
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MCPWM_CHECK((mcpwm_num) < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG); \
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MCPWM_CHECK((timer_num) < SOC_MCPWM_TIMERS_PER_GROUP, MCPWM_TIMER_ERROR, ESP_ERR_INVALID_ARG); \
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} while(0)
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#define MCPWM_TIMER_CHECK(mcpwm_num, timer_num) do{\
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@ -82,7 +83,7 @@ _Static_assert(SOC_MCPWM_GENERATOR_NUM == 2, "This driver assumes the generator
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} while(0)
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static mcpwm_context_t context[SOC_MCPWM_PERIPH_NUM] = {
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static mcpwm_context_t context[SOC_MCPWM_GROUPS] = {
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CONTEXT_INITIALIZER(),
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CONTEXT_INITIALIZER(),
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};
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@ -105,7 +106,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
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return ESP_OK;
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}
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK((GPIO_IS_VALID_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
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periph_module_enable(PERIPH_PWM0_MODULE + mcpwm_num);
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@ -138,7 +139,7 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
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esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_gpio_init(mcpwm_num, MCPWM0A, mcpwm_pin->mcpwm0a_out_num); //MCPWM0A
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mcpwm_gpio_init(mcpwm_num, MCPWM0B, mcpwm_pin->mcpwm0b_out_num); //MCPWM0B
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mcpwm_gpio_init(mcpwm_num, MCPWM1A, mcpwm_pin->mcpwm1a_out_num); //MCPWM1A
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@ -274,7 +275,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
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//update the comparer to keep the same duty rate
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mcpwm_hal_operator_update_basic(hal, op);
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for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) {
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for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
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hal->op[op].gen[gen] = (mcpwm_hal_generator_config_t) {
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.comparator = gen, //the driver currently always use the comparator A for PWMxA output, and comparator B for PWMxB output
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.duty_type = mcpwm_conf->duty_mode,
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@ -447,7 +448,7 @@ esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
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//the driver currently always use the timer x for operator x
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const int op = timer_num;
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MCPWM_TIMER_CHECK(mcpwm_num, timer_num);
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MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DB_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(dt_mode < MCPWM_DEADTIME_TYPE_MAX, MCPWM_DT_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
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mcpwm_hal_deadzone_conf_t deadzone = {
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.red = red,
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@ -477,7 +478,7 @@ esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num
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esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_critical_enter(mcpwm_num);
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mcpwm_hal_fault_init(&context[mcpwm_num].hal, fault_sig, intput_level);
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@ -487,7 +488,7 @@ esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t int
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esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_critical_enter(mcpwm_num);
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mcpwm_hal_fault_disable(&context[mcpwm_num].hal, fault_sig);
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@ -533,7 +534,7 @@ esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t tim
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esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
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uint32_t num_of_pulse)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_hal_init_config_t init_config = {
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.host_id = mcpwm_num,
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};
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@ -555,7 +556,7 @@ esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t ca
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esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_critical_enter(mcpwm_num);
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mcpwm_hal_capture_disable(&context[mcpwm_num].hal, cap_sig);
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@ -565,7 +566,7 @@ esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t c
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uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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uint32_t captured_value;
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mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, &captured_value, NULL);
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@ -574,7 +575,7 @@ uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_si
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uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig)
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{
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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mcpwm_capture_on_edge_t edge;
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mcpwm_hal_capture_get_result(&context[mcpwm_num].hal, cap_sig, NULL, &edge);
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return (edge == MCPWM_NEG_EDGE ? 2 : 1);
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@ -609,7 +610,7 @@ esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num)
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esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle)
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{
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esp_err_t ret;
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_PERIPH_NUM, MCPWM_UNIT_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(mcpwm_num < SOC_MCPWM_GROUPS, MCPWM_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
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MCPWM_CHECK(fn != NULL, MCPWM_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
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ret = esp_intr_alloc((ETS_PWM0_INTR_SOURCE + mcpwm_num), intr_alloc_flags, fn, arg, handle);
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return ret;
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@ -87,8 +87,8 @@ typedef struct {
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/// Configuration of each operator
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typedef struct {
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mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATOR_NUM]; ///< Configuration of the generators
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float duty[SOC_MCPWM_COMPARATOR_NUM]; ///< Duty rate for each comparator, 10 means 10%.
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mcpwm_hal_generator_config_t gen[SOC_MCPWM_GENERATORS_PER_OPERATOR]; ///< Configuration of the generators
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float duty[SOC_MCPWM_COMPARATORS_PER_OPERATOR]; ///< Duty rate for each comparator, 10 means 10%.
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int timer; ///< The timer this operator is using
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} mcpwm_hal_operator_config_t;
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@ -102,8 +102,8 @@ typedef struct {
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typedef struct {
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mcpwm_dev_t *dev; ///< Beginning address of the MCPWM peripheral registers. Call `mcpwm_hal_init` to initialize it.
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uint32_t prescale; ///< Prescale from the 160M clock to MCPWM main clock.
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mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMER_NUM]; ///< Configuration of the timers
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mcpwm_hal_operator_config_t op[SOC_MCPWM_OP_NUM]; ///< Configuration of the operators
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mcpwm_hal_timer_config_t timer[SOC_MCPWM_TIMERS_PER_GROUP]; ///< Configuration of the timers
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mcpwm_hal_operator_config_t op[SOC_MCPWM_OPERATORS_PER_GROUP]; ///< Configuration of the operators
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} mcpwm_hal_context_t;
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/// Configuration of the carrier
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@ -125,7 +125,7 @@ typedef struct {
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typedef struct {
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uint32_t cbc_enabled_mask; ///< Whether the cycle-by-cycle fault handling is enabled on each fault signal. BIT(n) stands for signal n.
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uint32_t ost_enabled_mask; ///< Whether the oneshot fault handling is enabled on each on each fault signal. BIT(n) stands for signal n.
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mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATOR_NUM]; ///< Action to perform on each generator when any one of the fault signal triggers.
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mcpwm_output_action_t action_on_fault[SOC_MCPWM_GENERATORS_PER_OPERATOR]; ///< Action to perform on each generator when any one of the fault signal triggers.
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} mcpwm_hal_fault_conf_t;
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/// Configuration of the synchronization of each clock
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@ -43,11 +43,11 @@ void mcpwm_hal_timer_update_basic(mcpwm_hal_context_t *hal, int timer)
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mcpwm_ll_timer_set_prescale(hal->dev, timer, hal->timer[timer].timer_prescale);
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uint32_t period = MCPWM_BASE_CLK / (hal->timer[timer].freq *
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(hal->prescale +1) * (hal->timer[timer].timer_prescale + 1));
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(hal->prescale + 1) * (hal->timer[timer].timer_prescale + 1));
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mcpwm_ll_timer_set_period(hal->dev, timer, period);
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//write back the actual value to the context
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hal->timer[timer].freq = MCPWM_BASE_CLK / (period *
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(hal->prescale +1) * (hal->timer[timer].timer_prescale + 1));
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(hal->prescale + 1) * (hal->timer[timer].timer_prescale + 1));
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mcpwm_ll_timer_set_count_mode(hal->dev, timer, hal->timer[timer].count_mode);
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}
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@ -70,10 +70,10 @@ void mcpwm_hal_operator_update_basic(mcpwm_hal_context_t *hal, int op)
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{
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mcpwm_hal_operator_config_t *op_conf = &hal->op[op];
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mcpwm_ll_operator_select_timer(hal->dev, op, op_conf->timer);
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for (int cmp = 0; cmp < SOC_MCPWM_COMPARATOR_NUM; cmp++) {
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for (int cmp = 0; cmp < SOC_MCPWM_COMPARATORS_PER_OPERATOR; cmp++) {
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mcpwm_hal_operator_update_comparator(hal, op, cmp);
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}
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for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) {
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for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
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mcpwm_hal_operator_update_generator(hal, op, gen);
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}
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}
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@ -88,7 +88,7 @@ void mcpwm_hal_operator_update_comparator(mcpwm_hal_context_t *hal, int op, int
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void mcpwm_hal_operator_update_generator(mcpwm_hal_context_t *hal, int op, int gen_num)
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{
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mcpwm_hal_generator_config_t* gen_config = &(hal->op[op].gen[gen_num]);
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mcpwm_hal_generator_config_t *gen_config = &(hal->op[op].gen[gen_num]);
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if (gen_config->duty_type == MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH) {
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mcpwm_ll_gen_set_zero_action(hal->dev, op, gen_num, MCPWM_ACTION_FORCE_HIGH);
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mcpwm_ll_gen_set_period_action(hal->dev, op, gen_num, MCPWM_ACTION_FORCE_HIGH);
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@ -166,21 +166,21 @@ void mcpwm_hal_fault_init(mcpwm_hal_context_t *hal, int fault_sig, bool level)
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void mcpwm_hal_operator_update_fault(mcpwm_hal_context_t *hal, int op, const mcpwm_hal_fault_conf_t *fault_conf)
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{
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for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_SIG_NUM; fault_sig++) {
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for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_DETECTORS_PER_GROUP; fault_sig++) {
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bool enabled = (fault_conf->cbc_enabled_mask & BIT(fault_sig)) ? true : false;
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mcpwm_ll_fault_cbc_enable_signal(hal->dev, op, fault_sig, enabled);
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}
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for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_SIG_NUM; fault_sig++) {
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for (int fault_sig = 0; fault_sig < SOC_MCPWM_FAULT_DETECTORS_PER_GROUP; fault_sig++) {
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bool enabled = (fault_conf->ost_enabled_mask & BIT(fault_sig)) ? true : false;
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mcpwm_ll_fault_oneshot_enable_signal(hal->dev, op, fault_sig, enabled);
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}
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if (fault_conf->cbc_enabled_mask) {
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for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) {
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for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
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mcpwm_ll_fault_set_cyc_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]);
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}
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}
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if (fault_conf->ost_enabled_mask) {
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for (int gen = 0; gen < SOC_MCPWM_GENERATOR_NUM; gen++) {
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for (int gen = 0; gen < SOC_MCPWM_GENERATORS_PER_OPERATOR; gen++) {
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mcpwm_ll_fault_set_oneshot_action(hal->dev, op, gen, fault_conf->action_on_fault[gen], fault_conf->action_on_fault[gen]);
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}
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}
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@ -193,7 +193,7 @@ void mcpwm_hal_fault_oneshot_clear(mcpwm_hal_context_t *hal, int op)
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void mcpwm_hal_fault_disable(mcpwm_hal_context_t *hal, int fault_sig)
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{
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for (int op = 0; op < SOC_MCPWM_OP_NUM; op++) {
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for (int op = 0; op < SOC_MCPWM_OPERATORS_PER_GROUP; op++) {
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if (mcpwm_ll_fault_oneshot_signal_enabled(hal->dev, op, fault_sig)) {
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mcpwm_ll_fault_clear_ost(hal->dev, op);
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}
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@ -150,12 +150,16 @@
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#define SOC_LEDC_TIMER_BIT_WIDE_NUM (20)
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/*-------------------------- MCPWM CAPS --------------------------------------*/
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#define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number
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#define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has
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#define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has
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#define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has
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#define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has
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#define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has
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#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
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#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
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#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
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#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
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#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
|
||||
#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
|
||||
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
|
||||
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
|
||||
#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
|
||||
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
|
||||
|
||||
/*-------------------------- MPU CAPS ----------------------------------------*/
|
||||
//TODO: correct the caller and remove unsupported lines
|
||||
|
@ -10,6 +10,7 @@
|
||||
#define SOC_TWAI_SUPPORTED 1
|
||||
#define SOC_GDMA_SUPPORTED 1
|
||||
#define SOC_I80_LCD_SUPPORTED 1
|
||||
#define SOC_MCPWM_SUPPORTED 1
|
||||
#define SOC_DEDICATED_GPIO_SUPPORTED 1
|
||||
#define SOC_CPU_CORES_NUM 2
|
||||
#define SOC_CACHE_SUPPORT_WRAP 1
|
||||
@ -52,6 +53,18 @@
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#include "ledc_caps.h"
|
||||
|
||||
/*-------------------------- MCPWM CAPS --------------------------------------*/
|
||||
#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
|
||||
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
|
||||
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
|
||||
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
|
||||
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
|
||||
#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
|
||||
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
|
||||
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
|
||||
#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
|
||||
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
|
||||
|
||||
/*-------------------------- MPU CAPS ----------------------------------------*/
|
||||
#include "mpu_caps.h"
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user