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Merge branch 'bugfix/bootloader_uart_custom_gpio' into 'master'

Browse Source 
bootloader: fixed the issue custom_uart_gpio doesn't take effect

Closes IDF-4606

See merge request espressif/esp-idf!16910
This commit is contained in:
Michael (XIAO Xufeng) 2022-03-02 02:35:14 +08:00
commit 78165c541e
9 changed files with 95 additions and 166 deletions
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2
components/bootloader_support/src/bootloader_console.c
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@ -76,10 +76,12 @@ void bootloader_console_init(void)
// Route GPIO signals to/from pins
const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX);
const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[uart_rx_gpio], PIN_FUNC_GPIO);
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[uart_rx_gpio]);
esp_rom_gpio_pad_pullup_only(uart_rx_gpio);
esp_rom_gpio_connect_out_signal(uart_tx_gpio, tx_idx, 0, 0);
esp_rom_gpio_connect_in_signal(uart_rx_gpio, rx_idx, 0);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[uart_tx_gpio], PIN_FUNC_GPIO);
// Enable the peripheral
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + uart_num);
}

12
components/hal/esp32s3/include/hal/uart_ll.h
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@ -55,6 +55,18 @@ typedef enum {
UART_INTR_WAKEUP = (0x1 << 19),
} uart_intr_t;
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
hw->clk_conf.rst_core = core_rst_en;
}
/**
* @brief Set the UART source clock.

18
components/soc/esp32/include/soc/uart_channel.h
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@ -1,16 +1,10 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H

64
components/soc/esp32c3/include/soc/uart_channel.h
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@ -1,61 +1,21 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 20
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
#define UART_TXD_GPIO21_DIRECT_CHANNEL UART_GPIO21_DIRECT_CHANNEL
#define UART_RXD_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
#endif

78
components/soc/esp32s2/include/soc/uart_channel.h
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@ -1,61 +1,41 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32S2.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
#define UART_GPIO43_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 43
#define UART_GPIO44_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 44
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 16
#define UART_GPIO15_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 15
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
#define UART_TXD_GPIO43_DIRECT_CHANNEL UART_GPIO43_DIRECT_CHANNEL
#define UART_RXD_GPIO44_DIRECT_CHANNEL UART_GPIO44_DIRECT_CHANNEL
#define UART_CTS_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_RTS_GPIO15_DIRECT_CHANNEL UART_GPIO15_DIRECT_CHANNEL
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO18_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 18
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 20
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 19
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
#define UART_RXD_GPIO18_DIRECT_CHANNEL UART_GPIO18_DIRECT_CHANNEL
#define UART_CTS_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
#define UART_RTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#endif

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -699,6 +699,10 @@ config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
config SOC_USB_PERIPH_NUM
bool
default y

1
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -274,6 +274,7 @@
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_REQUIRE_CORE_RESET (1)
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_PERIPH_NUM 1

78
components/soc/esp32s3/include/soc/uart_channel.h
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@ -1,58 +1,38 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32S3.
#pragma once
//UART channels
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
#define UART_GPIO43_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 43
#define UART_GPIO44_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 44
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 16
#define UART_GPIO15_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 15
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
#define UART_TXD_GPIO43_DIRECT_CHANNEL UART_GPIO43_DIRECT_CHANNEL
#define UART_RXD_GPIO44_DIRECT_CHANNEL UART_GPIO44_DIRECT_CHANNEL
#define UART_CTS_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_RTS_GPIO15_DIRECT_CHANNEL UART_GPIO15_DIRECT_CHANNEL
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 17
#define UART_GPIO18_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 18
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 20
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 19
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
#define UART_RXD_GPIO18_DIRECT_CHANNEL UART_GPIO18_DIRECT_CHANNEL
#define UART_CTS_GPIO20_DIRECT_CHANNEL UART_GPIO20_DIRECT_CHANNEL
#define UART_RTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL

4
tools/ci/check_copyright_ignore.txt
View File

@ -1385,7 +1385,6 @@ components/soc/esp32/include/soc/syscon_reg.h
components/soc/esp32/include/soc/syscon_struct.h
components/soc/esp32/include/soc/touch_sensor_channel.h
components/soc/esp32/include/soc/twai_struct.h
components/soc/esp32/include/soc/uart_channel.h
components/soc/esp32/include/soc/uart_pins.h
components/soc/esp32/include/soc/uart_reg.h
components/soc/esp32/include/soc/uart_struct.h
@ -1454,7 +1453,6 @@ components/soc/esp32c3/include/soc/system_struct.h
components/soc/esp32c3/include/soc/systimer_reg.h
components/soc/esp32c3/include/soc/systimer_struct.h
components/soc/esp32c3/include/soc/twai_struct.h
components/soc/esp32c3/include/soc/uart_channel.h
components/soc/esp32c3/include/soc/uart_pins.h
components/soc/esp32c3/include/soc/uart_reg.h
components/soc/esp32c3/include/soc/uart_struct.h
@ -1586,7 +1584,6 @@ components/soc/esp32s2/include/soc/systimer_struct.h
components/soc/esp32s2/include/soc/touch_sensor_channel.h
components/soc/esp32s2/include/soc/touch_sensor_pins.h
components/soc/esp32s2/include/soc/twai_struct.h
components/soc/esp32s2/include/soc/uart_channel.h
components/soc/esp32s2/include/soc/uart_pins.h
components/soc/esp32s2/include/soc/uart_reg.h
components/soc/esp32s2/include/soc/uart_struct.h
@ -1688,7 +1685,6 @@ components/soc/esp32s3/include/soc/touch_sensor_caps.h
components/soc/esp32s3/include/soc/twai_caps.h
components/soc/esp32s3/include/soc/twai_struct.h
components/soc/esp32s3/include/soc/uart_caps.h
components/soc/esp32s3/include/soc/uart_channel.h
components/soc/esp32s3/include/soc/uart_pins.h
components/soc/esp32s3/include/soc/uart_reg.h
components/soc/esp32s3/include/soc/uart_struct.h