1. Concurrency might cause ESP_ERR_TIMEOUT when calling uart_wait_tx_done
2. Concurrency might cause RTS line being de-assreted during tx transmission for rs485 mode
1. add check in the gdma driver, to prevent multiple channels connecting
to the same peripheral
2. memory copy DMA ID will occupy the peripheral's DMA ID on some ESP
targets (e.g. esp32c3/s3). We should search for a free one when
install async memcpy driver.
Closes https://github.com/espressif/esp-idf/issues/10575
1. Fix deep sleep wakeup IOs can not be unhold issue
2. Correct hold related APIs' description
3. Fix gpio_force_hold_all API
docs: Add GPIO wakeup source to sleep_modes doc for ESP32C3 and C2
Following the file renaming to use the "usb_dwc" prefix, this commit
updates the symbol names of those files to use the "usb_dwc" as well.
Some LL functions were also renamed so that the register name is
mentioned.
This commit updates the DWC_OTG based struct/ll/hal file names to
use the prefix "usb_dwc". This naming scheme reduces ambiguity if
another USB controller implementation is added.
As a result, "hcd.c" has been renamed to "hcd_dwc.c"
In previous gpio default isr, interrupt status bits get cleared at the exit of the isr.
However, for edge-triggered interrupt type, the interrupt status bit should be cleared before entering the per-pin handlers to avoid any potential interrupt lost.
Closes https://github.com/espressif/esp-idf/pull/6853
essl_spi: fix wrong dummy cycle under quad spi mode ant add a test to verify spi quad mod
Closes IDF-5182 and IDF-5181
See merge request espressif/esp-idf!18680
This commit gives basic mmu driver framework. Now it is able to maintain
mmu virtual address usage on esp32, esp32s2 and esp32s3. Usage to
external virtual address should rely on mmu functions to know which
address range is available, instead of hardcoded.
This commit also improves psram memory that is added to the heap
allocator. Now it's added to the heap, according to the memory
alignment.
Closes https://github.com/espressif/esp-idf/issues/8295
1.The dummy_bits is set to 4 in ESP32C3/C2, therefore, the data transmission started too early.This commit fix this issue by changing dummy_bits to 8.
2.Put the spi command the spi defintion in spi_types.h
3.Put the function which get spi command or dummy bits in spi_ll.h
uart: update console docs about frequency for ESP32-C2, move frequency of clock sources out of HAL
Closes IDF-5424 and IDF-4332
See merge request espressif/esp-idf!19274
Prior to this commit, adc ulp is disabled by setting
adc_oneshot_unit_init_cfg_t::ulp_mode to false.
After this commit, a new enum `ADC_ULP_MODE_DISABLE` is added. So
setting `ulp_mode` to `ADC_ULP_MODE_DISABLE`, instead of `false`, to
disable the ulp mode.
Closes: https://github.com/espressif/esp-idf/issues/9208
When I2S is configured into different modes, the slot sequence varies.
This commit updates slot sequence tables and corresponding descriptions
in (both code and programming guide).
All gpio hal and ll functions input arguments gpio_num_t are changed to uint32_t type.
Validation of gpio num should be guaranteed from the driver layer.
When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick
frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always
assumed that systimer tick frequency is integer (and 1 MHz * power of
two, above that!).
This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV.
It should be set in such a way that:
1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the
actual systimer tick frequency,
2. and SYSTIMER_LL_TICKS_PER_US is integer.
For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and
SYSTIMER_LL_TICKS_PER_US_DIV = 5.
This introduced two possible issues:
1. Overflow when multiplying systimer counter by 5
- Should not be an issue, since systimer counter is 52-bit, so
counter * 5 is no more than 55-bit.
2. The code needs to perform:
- divide by 5: when converting from microseconds to ticks
- divide by 52: when converting from ticks to microseconds
The latter potentially introduces a performance issue for the
esp_timer_get_time function.
This commit makes changes to cpu_ll.h, cpu_hal.h, and interrupt_controller_hal.h:
- Moved to esp_hw_support in order to be deprecated in the future
- HAL/LL API now route their calls to esp_cpu.h functions instead
Also updated soc_hal.h as follows:
- Removed __SOC_HAL_..._OTHER_CORES() macros as they dependend on cpu_hal.h
- Made soc_hal.h and soc_ll.h interfaces always inline, and removed soc_hal.c.
This commit also updates the XCHAL_ERRATUM_572 workaround by
- Removing it's HAL function and invoking the workaround it directly the bootloader
- Added missing workaround for the ESP32-S3
This commit fixes the systimer_counter_value_t by adding a resreved field so that the
type fills 64-bits.
Without the reserved field, when compiling with -O0 optimization, the unoccupied high
bits would not be initalized by the compiler, leading to systimer_hal_get_counter_value()
returning a garbage value.
Since ulp wakeup signal are connected to ulp int raw(except esp32), we
need to clear ulp int raw before sleep when ulp wakeup enabled. Otherwise,
if the ulp int raw is already set, chip will not sleep properly.
Closes https://github.com/espressif/esp-idf/issues/6229
The legacy driver can't handle the breaking change between esp chips
very well.
And it's not elegant to extend new feature like DMA, ETM.
The new driver can return a opaque handle for each RMT channel.
An obvious transaction concept was also introduced.
TX and RX functionalities are splited out.
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
Modify the NGed drivers to adopt new clock ids
Prior to this change, `spi_flash_hal_supports_direct_write` and
`spi_flash_hal_supports_direct_read` will check the buffer pointer
place, which should be done in driver layer, instead of HAL layer.
temperature_sensor: Refactor temperature sensor to new APIs (follow rule of driverNG) and support esp32s3
Closes IDF-3665, IDF-3367, and IDF-1793
See merge request espressif/esp-idf!16787
Hub Driver is refactored as follows:
This commit update and refactors the Hub Driver as follows:
- Refactored enumeration state machine and stage functions
- Enumeration stage is now incremented
- Combined transfer stages of enumeration into common functions
- Comments updated
- Fixed usbh_hal_disable_debounce_lock() that would cause root_port_handle_events()
to fail the HCD_PORT_CMD_RESET call because the previous port connection interrupt
was not cleared.
The following features were added to the Hub Driver
- Enumeration config descriptor is now fetched in two separate stages
- Header is fetched first to determine the wTotalLength of the descriptor
- Fetching the full descriptor will request exactly wTotalLength bytes
- This works around some non-compliant devices that will babble/return zero
when requesting a length > wTotalLength
- Closes https://github.com/espressif/esp-idf/issues/7799
- Enumeration now stores string descriptors
- The Manufacturer, Product, and Serial Number string descriptors are
now read and stored during enumeration
- String descriptors are now part of usb_device_info_t
- Added unit test to test enumeration
This commit updates the USB Host stack to use the USB PHY driver. The
USB PHY and the OTG Controller should now both be setup/deleted using
usb_new_phy() and usb_del_phy() respectively.
- The hcd_install() now expects the USB PHY and OTG Contorller to be
already setup before it is called
- usb_host_install() now has an option to skip calling usb_del_phy() if
the user wants to setup their own USB PHY (e.g., in the case of using
and external PHY).
- CDC-ACM and MSC examples/test updated to use internal PHY
Closes https://github.com/espressif/esp-idf/issues/8061
As ESP32C3 does not have support for REF_TICK source clock, it is now not
possible to select it anymore.
Auto cfg clock has been improved for all boards.
This commit fixes how the USB Host HCD handles sudden disconnections.
Bugs:
- HW channels remain active when the port suddenly disconnects, and
previously the channel would be disabled by setting the disabled bit,
then waiting for a disabled interrupt. However, ISOC channels do not
generate the disabled interrupt when the port is invalid, thus leading
to tasks getting indefinitely blocked in hcd_pipe_command().
Fix:
On a sudden disconnection, forcibly treat all channels as halted even
if their HCCHAR.ChEna bit is still set. We do a soft reset after a port
error anyways, so the channels will eventually be reset.
Closes https://github.com/espressif/esp-idf/issues/7505
This commit addes the 8/16 bit register field access workarounds to
the DWC_OTG peripheral. This workaround was applied to all other
peripherals in commit 874a720286.
