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rtcio: support rtcio on c6

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This commit is contained in:
laokaiyao 2022-12-13 17:27:04 +08:00
parent cfef24863f
commit 7a002ab7a6
22 changed files with 594 additions and 107 deletions
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3
components/driver/gpio/rtc_io.c
View File

@ -194,7 +194,6 @@ esp_err_t rtc_gpio_force_hold_dis_all(void)
return ESP_OK;
}
#endif // SOC_RTCIO_HOLD_SUPPORTED
#if SOC_RTCIO_WAKE_SUPPORTED
@ -226,8 +225,6 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
{
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027
return (gpio_num >= 0 && gpio_num < 8);
#else
return false;
#endif

32
components/driver/test_apps/gpio/main/test_rtcio.c
View File

@ -24,6 +24,8 @@
static const char *TAG = "rtcio_test";
#ifdef CONFIG_IDF_TARGET_ESP32
// The input-only rtcio pins do not have pull-up/down resistors (not support pull-up/down)
#define RTCIO_SUPPORT_PU_PD(num) (rtc_io_desc[num].pullup != 0)
#define TEST_GPIO_PIN_COUNT 16
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
@ -46,6 +48,8 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_39, //GPIO39
};
#elif defined CONFIG_IDF_TARGET_ESP32S2
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 20
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
@ -72,6 +76,8 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_21, //GPIO21
};
#elif defined CONFIG_IDF_TARGET_ESP32S3
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 21
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
// GPIO_NUM_0, //GPIO0 // Workaround: GPIO0 is strap pin, can not be used pullup/pulldown test.
@ -97,6 +103,20 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#elif CONFIG_IDF_TARGET_ESP32C6
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#endif
/*
@ -153,7 +173,7 @@ TEST_CASE("RTCIO_pullup/pulldown_test", "[rtcio]")
// init rtcio
for (int i = 0; i < TEST_GPIO_PIN_COUNT; i++) {
int num = rtc_io_number_get(s_test_map[i]);
if (rtc_gpio_is_valid_gpio(s_test_map[i]) && num > 0 && rtc_io_desc[num].pullup != 0) {
if (rtc_gpio_is_valid_gpio(s_test_map[i]) && num > 0 && RTCIO_SUPPORT_PU_PD(num)) {
RTCIO_CHECK( rtc_gpio_init(s_test_map[i]) );
RTCIO_CHECK( rtc_gpio_set_direction(s_test_map[i], RTC_GPIO_MODE_INPUT_ONLY) );
RTCIO_CHECK( rtc_gpio_pullup_dis(s_test_map[i]) );
@ -167,7 +187,7 @@ TEST_CASE("RTCIO_pullup/pulldown_test", "[rtcio]")
ESP_LOGI(TAG, "RTCIO pull level %d", level);
for (int i = 0; i < TEST_GPIO_PIN_COUNT; i++) {
int num = rtc_io_number_get(s_test_map[i]);
if (rtc_gpio_is_valid_gpio(s_test_map[i]) && num > 0 && rtc_io_desc[num].pullup != 0) {
if (rtc_gpio_is_valid_gpio(s_test_map[i]) && num > 0 && RTCIO_SUPPORT_PU_PD(num)) {
if (level) {
RTCIO_CHECK( rtc_gpio_pulldown_dis(s_test_map[i]) );
RTCIO_CHECK( rtc_gpio_pullup_en(s_test_map[i]) );
@ -188,7 +208,7 @@ TEST_CASE("RTCIO_pullup/pulldown_test", "[rtcio]")
// Deinit rtcio
for (int i = 0; i < TEST_GPIO_PIN_COUNT; i++) {
int num = rtc_io_number_get(s_test_map[i]);
if (rtc_gpio_is_valid_gpio(s_test_map[i]) && num > 0 && rtc_io_desc[num].pullup != 0) {
if (rtc_gpio_is_valid_gpio(s_test_map[i]) && num > 0 && RTCIO_SUPPORT_PU_PD(num)) {
RTCIO_CHECK( rtc_gpio_deinit(s_test_map[i]) );
}
}
@ -238,6 +258,7 @@ TEST_CASE("RTCIO_output_OD_test", "[rtcio]")
ESP_LOGI(TAG, "RTCIO output OD test over");
}
#if SOC_RTCIO_HOLD_SUPPORTED
/*
* Test rtcio hold function.
*/
@ -305,6 +326,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
ESP_LOGI(TAG, "RTCIO hold test over");
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6) // TODO: IDF-5349 Remove when deep sleep is supported on ESP32C6
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6) these pads' default configuration is low level
@ -348,8 +370,10 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
* Test rtcio hold function during deep sleep.
* This test case can only check the hold state after waking up from deep sleep
* If you want to check that the rtcio hold function works properly during deep sleep,
* please use logic analyzer or oscillscope
* please use logic analyzer or oscilloscope
*/
TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
rtcio_deep_sleep_hold_test_first_stage,
rtcio_deep_sleep_hold_test_second_stage)
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
#endif // #if SOC_RTCIO_HOLD_SUPPORTED

2
components/esp_hw_support/sleep_modes.c
View File

@ -1001,7 +1001,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
{
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027 C6 IO0-7 meet both conditions here
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
return RTC_GPIO_IS_VALID_GPIO(gpio_num);
#else
return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);

12
components/hal/esp32/include/hal/rtc_io_ll.h
View File

@ -300,7 +300,7 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
@ -312,7 +312,7 @@ static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
}
@ -322,7 +322,7 @@ static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_disable_input(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
}
@ -347,6 +347,12 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
}
/**
* Set specific logic level on an RTC IO pin as a wakeup trigger.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param level Logic level (0)
*/
static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
{
REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num);

392
components/hal/esp32c6/include/hal/rtc_io_ll.h Normal file
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@ -0,0 +1,392 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdlib.h>
#include "soc/rtc_periph.h"
#include "soc/pcr_struct.h"
#include "soc/rtc_io_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#include "hal/gpio_types.h"
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_PIN_MASK_ALL ((1 << SOC_RTCIO_PIN_COUNT) - 1)
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
} rtcio_ll_func_t;
typedef enum {
RTCIO_WAKEUP_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_WAKEUP_LOW_LEVEL = 0x4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_WAKEUP_HIGH_LEVEL = 0x5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_wake_type_t;
typedef enum {
RTCIO_OUTPUT_NORMAL = 0, /*!< RTCIO output mode is normal. */
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Select the rtcio function.
*
* @note The RTC function must be selected before the pad analog function is enabled.
* @note The clock gating 'PCR.iomux_conf.iomux_clk_en' is the gate of both 'lp_io' and 'etm_gpio'
* And it's default to be turned on, so we don't need to operate this clock gate here additionally
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Select pin function.
*/
static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
//0:RTC FUNCTION 1,2,3:Reserved
LP_IO.gpio[rtcio_num].mcu_sel = RTCIO_LL_PIN_FUNC;
} else if (func == RTCIO_FUNC_DIGITAL) {
// Clear the bit to use digital GPIO module
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
}
}
/**
* Enable rtcio output.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_output_enable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1ts, enable_w1ts, BIT(rtcio_num));
}
/**
* Disable rtcio output.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_output_disable(int rtcio_num)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1tc, enable_w1tc, BIT(rtcio_num));
}
/**
* Set RTCIO output level.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param level 0: output low; ~0: output high.
*/
static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
{
if (level) {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num));
}
}
/**
* Enable rtcio input.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_input_enable(int rtcio_num)
{
LP_IO.gpio[rtcio_num].fun_ie = 1;
}
/**
* Disable rtcio input.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_input_disable(int rtcio_num)
{
LP_IO.gpio[rtcio_num].fun_ie = 0;
}
/**
* Get RTCIO input level.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @return 0: input low; ~0: input high.
*/
static inline uint32_t rtcio_ll_get_level(int rtcio_num)
{
return (uint32_t)(LP_IO.in.in_data_next >> rtcio_num) & 0x1;
}
/**
* @brief Set RTC GPIO pad drive capability
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param strength Drive capability of the pad. Range: 0 ~ 3.
*/
static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength)
{
LP_IO.gpio[rtcio_num].fun_drv = strength;
}
/**
* @brief Get RTC GPIO pad drive capability.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @return Drive capability of the pad. Range: 0 ~ 3.
*/
static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num)
{
return LP_IO.gpio[rtcio_num].fun_drv;
}
/**
* @brief Set RTC GPIO pad output mode.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @return mode Output mode.
*/
static inline void rtcio_ll_output_mode_set(int rtcio_num, rtcio_ll_out_mode_t mode)
{
LP_IO.pin[rtcio_num].pad_driver = mode;
}
/**
* RTC GPIO pullup enable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pullup_enable(int rtcio_num)
{
/* Enable internal weak pull-up */
LP_IO.gpio[rtcio_num].fun_wpu = 1;
}
/**
* RTC GPIO pullup disable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pullup_disable(int rtcio_num)
{
/* Disable internal weak pull-up */
LP_IO.gpio[rtcio_num].fun_wpu = 0;
}
/**
* RTC GPIO pulldown enable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pulldown_enable(int rtcio_num)
{
/* Enable internal weak pull-down */
LP_IO.gpio[rtcio_num].fun_wpd = 1;
}
/**
* RTC GPIO pulldown disable.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_pulldown_disable(int rtcio_num)
{
/* Enable internal weak pull-down */
LP_IO.gpio[rtcio_num].fun_wpd = 0;
}
/**
* Enable force hold function for an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_force_hold_enable(int rtcio_num)
{
LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num);
}
/**
* Disable hold function on an RTC IO pad
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_force_hold_disable(int rtcio_num)
{
LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num);
}
/**
* @brief Enable all LP IO pads hold function during Deep-sleep
*/
static inline void rtcio_ll_deep_sleep_hold_en_all(void)
{
PMU.imm_pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
* @brief Disable all LP IO pads hold function during Deep-sleep
*/
static inline void rtcio_ll_deep_sleep_hold_dis_all(void)
{
PMU.imm_pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**
* Enable force hold function for all RTC IO pads
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
* This function is useful when going into light or deep sleep mode to prevent
* the pin configuration from changing.
*/
static inline void rtcio_ll_force_hold_all(void)
{
// No such a 'hold_all' bit on C6, use bit hold instead
LP_AON.gpio_hold0.gpio_hold0 |= RTCIO_LL_PIN_MASK_ALL;
}
/**
* Disable hold function fon all RTC IO pads
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
*/
static inline void rtcio_ll_force_unhold_all(void)
{
// No such a 'hold_all' bit on C6, use bit hold instead
LP_AON.gpio_hold0.gpio_hold0 &= ~RTCIO_LL_PIN_MASK_ALL;
}
/**
* Enable wakeup function and set wakeup type from light sleep or deep sleep for rtcio.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param type Wakeup on high level or low level.
*/
static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t type)
{
LP_IO.pin[rtcio_num].wakeup_enable = 0x1;
LP_IO.pin[rtcio_num].int_type = type;
}
/**
* Disable wakeup function from light sleep or deep sleep for rtcio.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_wakeup_disable(int rtcio_num)
{
LP_IO.pin[rtcio_num].wakeup_enable = 0;
LP_IO.pin[rtcio_num].int_type = RTCIO_WAKEUP_DISABLE;
}
/**
* Enable rtc io output in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
{
LP_IO.gpio[gpio_num].mcu_oe = 1;
}
/**
* Disable rtc io output in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
{
LP_IO.gpio[gpio_num].mcu_oe = 0;
}
/**
* Enable rtc io input in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
{
LP_IO.gpio[gpio_num].mcu_ie = 1;
}
/**
* Disable rtc io input in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
{
LP_IO.gpio[gpio_num].mcu_ie = 0;
}
/**
* Enable rtc io keep another setting in deep sleep.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_enable_sleep_setting(gpio_num_t gpio_num)
{
LP_IO.gpio[gpio_num].slp_sel = 1;
}
/**
* Disable rtc io keep another setting in deep sleep. (Default)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
{
LP_IO.gpio[gpio_num].slp_sel = 0;
}
/**
* Set specific logic level on an RTC IO pin as a wakeup trigger.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param level Logic level (0)
*/
static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
{
uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
wakeup_sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
if (level) {
wakeup_level_mask |= BIT(rtcio_num);
} else {
wakeup_level_mask &= ~BIT(rtcio_num);
}
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
}
#ifdef __cplusplus
}
#endif

12
components/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@ -303,7 +303,7 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
@ -315,7 +315,7 @@ static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
}
@ -325,7 +325,7 @@ static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_disable_input(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
}
@ -350,6 +350,12 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
}
/**
* Set specific logic level on an RTC IO pin as a wakeup trigger.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param level Logic level (0)
*/
static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
{
REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num);

12
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@ -318,7 +318,7 @@ static inline void rtcio_ll_enable_output_in_sleep(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_output_in_sleep(gpio_num_t gpio_num)
{
if (rtc_io_desc[gpio_num].slpoe) {
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpoe);
@ -330,7 +330,7 @@ static inline void rtcio_ll_in_sleep_disable_output(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num)
static inline void rtcio_ll_enable_input_in_sleep(gpio_num_t gpio_num)
{
SET_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
}
@ -340,7 +340,7 @@ static inline void rtcio_ll_in_sleep_enable_input(gpio_num_t gpio_num)
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_in_sleep_disable_input(gpio_num_t gpio_num)
static inline void rtcio_ll_disable_input_in_sleep(gpio_num_t gpio_num)
{
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpie);
}
@ -365,6 +365,12 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel);
}
/**
* Set specific logic level on an RTC IO pin as a wakeup trigger.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param level Logic level (0)
*/
static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
{
REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num);

2
components/hal/include/hal/rtc_io_hal.h
View File

@ -17,8 +17,8 @@
#include <esp_err.h>
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#include "soc/soc_caps.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#include "hal/rtc_io_ll.h"
#include "hal/rtc_io_types.h"
#endif

30
components/hal/rtc_io_hal.c
View File

@ -1,16 +1,8 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for RTC IO (common part)
@ -70,23 +62,23 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode)
{
switch (mode) {
case RTC_GPIO_MODE_INPUT_ONLY:
rtcio_ll_in_sleep_enable_input(rtcio_num);
rtcio_ll_in_sleep_disable_output(rtcio_num);
rtcio_ll_enable_input_in_sleep(rtcio_num);
rtcio_ll_disable_output_in_sleep(rtcio_num);
rtcio_ll_enable_sleep_setting(rtcio_num);
break;
case RTC_GPIO_MODE_OUTPUT_ONLY:
rtcio_ll_enable_output_in_sleep(rtcio_num);
rtcio_ll_in_sleep_disable_input(rtcio_num);
rtcio_ll_disable_input_in_sleep(rtcio_num);
rtcio_ll_enable_sleep_setting(rtcio_num);
break;
case RTC_GPIO_MODE_INPUT_OUTPUT:
rtcio_ll_in_sleep_enable_input(rtcio_num);
rtcio_ll_enable_input_in_sleep(rtcio_num);
rtcio_ll_enable_output_in_sleep(rtcio_num);
rtcio_ll_enable_sleep_setting(rtcio_num);
break;
case RTC_GPIO_MODE_DISABLED:
rtcio_ll_in_sleep_disable_input(rtcio_num);
rtcio_ll_in_sleep_disable_output(rtcio_num);
rtcio_ll_disable_input_in_sleep(rtcio_num);
rtcio_ll_disable_output_in_sleep(rtcio_num);
rtcio_ll_disable_sleep_setting(rtcio_num);
break;
default:

20
components/soc/esp32/include/soc/rtc_io_channel.h
View File

@ -1,22 +1,12 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_IO_CHANNEL_H
#define _SOC_RTC_IO_CHANNEL_H
#define RTC_GPIO_NUMBER 18
//RTC GPIO channels
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 36

1
components/soc/esp32c6/CMakeLists.txt
View File

@ -3,6 +3,7 @@ set(srcs
"dedic_gpio_periph.c"
"gdma_periph.c"
"gpio_periph.c"
"rtc_io_periph.c"
"sdm_periph.c"
"interrupts.c"
"spi_periph.c"

16
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -323,6 +323,18 @@ config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 8
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
@ -587,10 +599,6 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RTCIO_PIN_COUNT
int
default 0
config SOC_RSA_MAX_BIT_LEN
int
default 3072

32
components/soc/esp32c6/include/soc/rtc_io_channel.h Normal file
View File

@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7

8
components/soc/esp32c6/include/soc/rtc_io_reg.h Normal file
View File

@ -0,0 +1,8 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/lp_io_reg.h"

19
components/soc/esp32c6/include/soc/rtc_io_struct.h Normal file
View File

@ -0,0 +1,19 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/lp_io_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef lp_io_dev_t rtc_io_dev_t;
#define RTCIO LP_IO
#ifdef __cplusplus
}
#endif

14
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -178,11 +178,10 @@
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// TODO: IDF-6027
// #define SOC_RTCIO_PIN_COUNT 8
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
// #define SOC_RTCIO_HOLD_SUPPORTED 1 (does not have force_hold_all feature, but has deep_sleep_hold_all feature)
// #define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_PIN_COUNT 8
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_HOLD_SUPPORTED 1
// #define SOC_RTCIO_WAKE_SUPPORTED 1 // TODO: IDF-5645
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
@ -280,11 +279,6 @@
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C6. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT (0U)
// TODO: IDF-5359 (Copy from esp32c3, need check)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)

41
components/soc/esp32c6/rtc_io_periph.c Normal file
View File

@ -0,0 +1,41 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/rtc_periph.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
RTCIO_GPIO1_CHANNEL, //GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
RTCIO_GPIO3_CHANNEL, //GPIO3
RTCIO_GPIO4_CHANNEL, //GPIO4
RTCIO_GPIO5_CHANNEL, //GPIO5
RTCIO_GPIO6_CHANNEL, //GPIO6
RTCIO_GPIO7_CHANNEL, //GPIO7
-1,//GPIO8
-1,//GPIO9
-1,//GPIO10
-1,//GPIO11
-1,//GPIO12
-1,//GPIO13
-1,//GPIO14
-1,//GPIO15
-1,//GPIO16
-1,//GPIO17
-1,//GPIO18
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
-1,//GPIO25
-1,//GPIO26
-1,//GPIO27
-1,//GPIO28
-1,//GPIO29
-1,//GPIO30
};

7
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -159,13 +159,6 @@
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// TODO: IDF-6027
// #define SOC_RTCIO_PIN_COUNT 8
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
// #define SOC_RTCIO_HOLD_SUPPORTED 1 (does not have force_hold_all feature, but has deep_sleep_hold_all feature)
// #define SOC_RTCIO_WAKE_SUPPORTED 1
// TODO: IDF-6241
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */

20
components/soc/esp32s2/include/soc/rtc_io_channel.h
View File

@ -1,22 +1,12 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_RTC_GPIO_CHANNEL_H
#define _SOC_RTC_GPIO_CHANNEL_H
#define RTC_GPIO_NUMBER 22
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0

20
components/soc/esp32s3/include/soc/rtc_io_channel.h
View File

@ -1,21 +1,11 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define RTC_GPIO_NUMBER 22
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0

2
components/soc/include/soc/rtc_cntl_periph.h
View File

@ -6,6 +6,8 @@
#pragma once
#include "sdkconfig.h"
// TODO: IDF-5645
#if CONFIG_IDF_TARGET_ESP32C6
#include "soc/lp_aon_reg.h"

4
tools/ci/check_copyright_ignore.txt
View File

@ -693,7 +693,6 @@ components/hal/include/hal/usb_hal.h
components/hal/include/hal/usb_types_private.h
components/hal/include/hal/wdt_types.h
components/hal/mpu_hal.c
components/hal/rtc_io_hal.c
components/hal/sha_hal.c
components/hal/spi_flash_encrypt_hal_iram.c
components/hal/spi_flash_hal_gpspi.c
@ -864,7 +863,6 @@ components/soc/esp32/include/soc/pid.h
components/soc/esp32/include/soc/reset_reasons.h
components/soc/esp32/include/soc/rtc_cntl_struct.h
components/soc/esp32/include/soc/rtc_i2c_reg.h
components/soc/esp32/include/soc/rtc_io_channel.h
components/soc/esp32/include/soc/rtc_io_reg.h
components/soc/esp32/include/soc/rtc_io_struct.h
components/soc/esp32/include/soc/sdio_slave_pins.h
@ -955,7 +953,6 @@ components/soc/esp32s2/include/soc/memprot_defs.h
components/soc/esp32s2/include/soc/nrx_reg.h
components/soc/esp32s2/include/soc/rtc_cntl_struct.h
components/soc/esp32s2/include/soc/rtc_i2c_reg.h
components/soc/esp32s2/include/soc/rtc_io_channel.h
components/soc/esp32s2/include/soc/rtc_io_reg.h
components/soc/esp32s2/include/soc/sdio_slave_pins.h
components/soc/esp32s2/include/soc/sdmmc_pins.h
@ -1018,7 +1015,6 @@ components/soc/esp32s3/include/soc/peri_backup_struct.h
components/soc/esp32s3/include/soc/reset_reasons.h
components/soc/esp32s3/include/soc/rtc_i2c_reg.h
components/soc/esp32s3/include/soc/rtc_i2c_struct.h
components/soc/esp32s3/include/soc/rtc_io_channel.h
components/soc/esp32s3/include/soc/rtc_io_reg.h
components/soc/esp32s3/include/soc/rtc_io_struct.h
components/soc/esp32s3/include/soc/sdio_slave_pins.h