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https://github.com/espressif/esp-idf.git
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usb: Fix LL 8/16 bit register field access
This commit addes the 8/16 bit register field access workarounds to
the DWC_OTG peripheral. This workaround was applied to all other
peripherals in commit 874a720286.
This commit is contained in:
Darian Leung
parent
13ab2cd9f9
commit
0159c37cf2
@ -1,16 +1,8 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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@ -23,6 +15,8 @@ extern "C" {
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#include "soc/usbh_struct.h"
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#include "soc/usb_wrap_struct.h"
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#include "hal/usb_types_private.h"
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#include "hal/misc.h"
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/* -----------------------------------------------------------------------------
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------------------------------- Global Registers -------------------------------
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@ -328,7 +322,7 @@ static inline void usb_ll_dis_intrs(usbh_dev_t *hw, uint32_t intr_mask)
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static inline void usb_ll_set_rx_fifo_size(usbh_dev_t *hw, uint32_t num_lines)
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{
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//Set size in words
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hw->grxfsiz_reg.rxfdep = num_lines;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines);
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}
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// -------------------------- GNPTXFSIZ Register -------------------------------
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@ -337,8 +331,8 @@ static inline void usb_ll_set_nptx_fifo_size(usbh_dev_t *hw, uint32_t addr, uint
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{
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usb_gnptxfsiz_reg_t gnptxfsiz;
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gnptxfsiz.val = hw->gnptxfsiz_reg.val;
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gnptxfsiz.nptxfstaddr = addr;
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gnptxfsiz.nptxfdep = num_lines;
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HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfstaddr, addr);
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HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfdep, num_lines);
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hw->gnptxfsiz_reg.val = gnptxfsiz.val;
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}
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@ -373,8 +367,8 @@ static inline void usbh_ll_set_ptx_fifo_size(usbh_dev_t *hw, uint32_t addr, uint
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{
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usb_hptxfsiz_reg_t hptxfsiz;
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hptxfsiz.val = hw->hptxfsiz_reg.val;
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hptxfsiz.ptxfstaddr = addr;
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hptxfsiz.ptxfsize = num_lines;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfstaddr, addr);
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HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfsize, num_lines);
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hw->hptxfsiz_reg.val = hptxfsiz.val;
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}
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@ -473,7 +467,7 @@ static inline void usbh_ll_hfir_set_defaults(usbh_dev_t *hw, usb_priv_speed_t sp
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static inline uint32_t usbh_ll_get_frm_time_rem(usbh_dev_t *hw)
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{
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return hw->hfnum_reg.frrem;
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return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem);
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}
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static inline uint32_t usbh_ll_get_frm_num(usbh_dev_t *hw)
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@ -485,7 +479,7 @@ static inline uint32_t usbh_ll_get_frm_num(usbh_dev_t *hw)
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static inline uint32_t usbh_ll_get_p_tx_queue_top(usbh_dev_t *hw)
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{
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return hw->hptxsts_reg.ptxqtop;
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return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop);
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}
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static inline uint32_t usbh_ll_get_p_tx_queue_space_avail(usbh_dev_t *hw)
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@ -495,20 +489,21 @@ static inline uint32_t usbh_ll_get_p_tx_queue_space_avail(usbh_dev_t *hw)
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static inline uint32_t usbh_ll_get_p_tx_fifo_space_avail(usbh_dev_t *hw)
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{
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return hw->hptxsts_reg.ptxfspcavail;
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return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail);
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}
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// ----------------------------- HAINT Register --------------------------------
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static inline uint32_t usbh_ll_get_chan_intrs_msk(usbh_dev_t *hw)
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{
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return hw->haint_reg.haint;
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return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint);
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}
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// --------------------------- HAINTMSK Register -------------------------------
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static inline void usbh_ll_haintmsk_en_chan_intr(usbh_dev_t *hw, uint32_t mask)
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{
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hw->haintmsk_reg.val |= mask;
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}
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@ -817,31 +812,6 @@ static inline void usbh_ll_chan_set_dma_addr_non_iso(volatile usb_host_chan_regs
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chan->hcdma_reg.non_iso.ctd = qtd_idx;
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}
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static inline void usbh_ll_chan_set_dma_addr_iso(volatile usb_host_chan_regs_t *chan,
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void *dmaaddr,
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uint32_t ntd)
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{
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int n;
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if (ntd == 2) {
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n = 4;
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} else if (ntd == 4) {
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n = 5;
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} else if (ntd == 8) {
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n = 6;
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} else if (ntd == 16) {
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n = 7;
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} else if (ntd == 32) {
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n = 8;
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} else { //ntd == 64
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n = 9;
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}
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//Set HCTSIZi
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chan->hctsiz_reg.ntd = ntd -1;
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chan->hctsiz_reg.sched_info = 0xFF; //Always set to 0xFF for FS
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//Set HCDMAi
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chan->hcdma_reg.iso.dmaaddr_ctd = (((uint32_t)dmaaddr) & 0x1FF) << (n-3); //ctd is set to 0
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}
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static inline int usbh_ll_chan_get_ctd(usb_host_chan_regs_t *chan)
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{
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return chan->hcdma_reg.non_iso.ctd;
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@ -850,12 +820,12 @@ static inline int usbh_ll_chan_get_ctd(usb_host_chan_regs_t *chan)
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static inline void usbh_ll_chan_hctsiz_init(volatile usb_host_chan_regs_t *chan)
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{
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chan->hctsiz_reg.dopng = 0; //Don't do ping
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chan->hctsiz_reg.sched_info = 0xFF; //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels
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HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, sched_info, 0xFF); //Schedinfo is always 0xFF for fullspeed. Not used in Bulk/Ctrl channels
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}
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static inline void usbh_ll_chan_set_qtd_list_len(volatile usb_host_chan_regs_t *chan, int qtd_list_len)
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{
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chan->hctsiz_reg.ntd = qtd_list_len - 1; //Set the length of the descriptor list
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HAL_FORCE_MODIFY_U32_REG_FIELD(chan->hctsiz_reg, ntd, qtd_list_len - 1); //Set the length of the descriptor list
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}
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// ---------------------------- HCDMABi Register -------------------------------
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@ -1415,7 +1415,6 @@ components/hal/include/hal/uhci_types.h
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components/hal/include/hal/usb_hal.h
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components/hal/include/hal/usb_types_private.h
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components/hal/include/hal/usbh_hal.h
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components/hal/include/hal/usbh_ll.h
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components/hal/include/hal/wdt_hal.h
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components/hal/include/hal/wdt_types.h
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components/hal/interrupt_controller_hal.c
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