alex/esp-idf
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37,049 Commits 20 Branches 148 Tags 384 MiB
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245 Commits

Author SHA1 Message Date
wuzhenghui
6b64b76d2a
fix(esp_system): increase 26Mhz esp32c2 slow clock calibration timeout watchdog threshold 2024-04-28 14:40:11 +08:00
wuzhenghui
f3d963a93b
fix(esp_system): update power domain configuration with slow clock source selection 2024-04-17 15:45:52 +08:00
Mahavir Jain
bf63862c4a Merge branch 'fix/enable_crypto_periphs_before_rom_exec' into 'master' 
fix(esp_system): enable crypto periphs before rom execution

See merge request espressif/esp-idf!30116
 2024-04-13 00:14:16 +08:00
harshal.patil
6ec486e351
fix(esp_system): Enable crpyto peripherals related clocks for specific ESP32-P4 ECOs 2024-04-12 14:56:53 +05:30
wuzhenghui
e7046e2abf
fix(esp_hw_support): fix bad logic in esp_perip_clk_init 2024-04-12 14:08:07 +08:00
Lou Tianhao
3fb4909483 feat(example): support esp32c5 timer/gpio/uart wakeup 2024-04-10 11:45:04 +08:00
Darian Leung
023eae4f0b
feat(hal/usb): Update USB WRAP and USJ LL, add missing ESP32-P4 LL 
This commit updates updates the LLs of USB WRAP and USJ as follows:

- Added missing 'usb_wrap_ll.h' and 'usb_serial_jtag_ll.h' for the ESP32-P4
- Added LL cap macros to distinguish feature differences between the LLs of
  different targets:
    - '..._LL_EXT_PHY_SUPPORTED' indicates whether the USB WRAP/USJ supports
      routing to an external FSLS PHY.
    - '..._LL_SWAP_PHY_SUPPORTED' indicates whether the USB WRAP/USJ supports
      swapping between multiple internal FSLS PHYs.
- Tidied up some RCC LL functions and their callers.
- Added 'usb_wrap_types.h' and 'usb_serial_jtag_types.h' to provide types used
  in LLs.
- Fixed some spelling/naming issues as part of code-spell pre-commit
 2024-04-04 02:47:00 +08:00
morris
1ed64afddd Merge branch 'refactor/remove_unused_periph_module_enable' into 'master' 
remove orphaned clk_gate_ll.h on esp32p4

Closes IDF-8094

See merge request espressif/esp-idf!29906
 2024-03-29 14:50:34 +08:00
morris
8e64a59fac refactor(periph_ctrl): remove orphaned clk_gate_ll.h 
and deprecate the legacy periph_module_xxx functions for new targets
 2024-03-29 10:53:05 +08:00
wuzhenghui
4a64d2fe2c change(hal): control PAU bus clock by hal layer 2024-03-29 00:36:46 +08:00
Marius Vikhammer
1c73c657c9 Merge branch 'ci/console_test_coverage' into 'master' 
ci(console): improve esp-system console test-coverage

Closes IDFCI-1856, IDF-9576, and IDF-9577

See merge request espressif/esp-idf!29748
 2024-03-28 11:14:57 +08:00
wuzhenghui
621effce5b
fix(esp_system): workaround for CI pass 
1. workaround esp32p4 rev0 wrong deepsleep wakeup cause

2. workaround esp32p4 lightsleep stuck issue with PSRAM enabled
 2024-03-27 13:59:37 +08:00
wuzhenghui
ccaae61fee
feat(esp_hw_support): support esp32p4 deepsleep 2024-03-27 13:59:36 +08:00
Marius Vikhammer
42fc463c81 fix(console): fixed CONSOLE_NONE not working on C2/C3 2024-03-26 13:39:10 +08:00
Mahavir Jain
cdc1a2551b Merge branch 'feature/enable_rsa_support_for_c5' into 'master' 
feat: enable RSA support for c5

See merge request espressif/esp-idf!29189
 2024-03-22 10:10:47 +08:00
wanlei
a611e91b2f feat(esp32c61): new chip add system and esp_timer support 2024-03-21 11:31:15 +08:00
Darian
53e3833f44 Merge branch 'refactor/usb_fsls_phy_hal' into 'master' 
refactor(hal/usb): Update USB PHY related HAL/LL API

See merge request espressif/esp-idf!29659
 2024-03-20 06:07:29 +08:00
nilesh.kale
b11f286555 feat(esp_system/esp32c5): revised cypto clock to be used 
This commit updated crypto clock to use 160M SPLL clock
 2024-03-19 13:47:04 +05:30
Darian Leung
a77e5cc718
refactor(hal/usb): Remove usb_fsls_phy_ll.h 
For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.

This commit does the following:

- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
 2024-03-18 19:23:43 +08:00
laokaiyao
24d6dcb829 feat(esp32c5mp): add system related components 2024-03-18 17:34:56 +08:00
Wu Zheng Hui
5a682c3bbb Merge branch 'feature/optimize_chips_active_power' into 'master' 
feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
 2024-03-14 12:08:33 +08:00
Konstantin Kondrashov
3f89072af1 feat(all): Use PRIx macro in all logs 2024-03-12 11:15:53 +02:00
wuzhenghui
9e8e20227f
feat(system): disable RNG module clock by default for save power 2024-03-12 10:10:41 +08:00
wuzhenghui
2a251982fc
feat(system): add option to allow user disable assist_debug module to save power 2024-03-12 10:10:40 +08:00
wuzhenghui
b0fa4565a1
feat(system): add option to allow user disable USJ module to save power 2024-03-12 10:10:36 +08:00
wuzhenghui
85b246ac88
feat(system): gate the debug clock source by default for esp32c6 and esp32h2 2024-03-07 19:26:39 +08:00
wuzhenghui
f5707c6ab8
feat(system): gate the REF_TICK clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
wuzhenghui
60e985e7af
feat(system): gate the LP peripheral clock by default for esp32c6 and esp32h2 2024-03-07 19:26:38 +08:00
wuzhenghui
0528c8b4f4
feat(system): gate the HP peripheral clock by default for esp32c6 and esp32h2 2024-03-07 19:26:37 +08:00
nilesh.kale
f6a7fb13cd feat: re enables tests on p4 
This commit re-enables mbedtls and hal/crypto testapos on p4.
 2024-03-05 17:48:05 +08:00
Wan Lei
3459db1bbb Merge branch 'feat/c6lite_c61_introduce_step1_target' into 'master' 
feat(esp32c61): introduce target esp32c61 (1/8) 🌱

See merge request espressif/esp-idf!29238
 2024-03-05 11:36:17 +08:00
Konstantin Kondrashov
43c604f145 Merge branch 'feature/move_efuse_related_inits_into_component' into 'master' 
feat(efuse): Move efuse-related init steps into the component

Closes IDF-8759 and IDF-8761

See merge request espressif/esp-idf!28422
 2024-03-04 17:34:44 +08:00
KonstantinKondrashov
f9800e0726 feat(efuse): Move efuse-related init steps into the component 2024-03-01 21:07:03 +02:00
wanlei
ee02b71f1c feat(esp32c61): introduce target esp32c61 2024-03-01 21:12:25 +08:00
Marius Vikhammer
c3ecd6d1f7 Merge branch 'bugfix/reset_reasons' into 'master' 
Update reset reasons for C6, H2, P4 and C5

Closes IDF-5719 and IDF-8660

See merge request espressif/esp-idf!28999
 2024-02-22 11:02:29 +08:00
Marius Vikhammer
4ce4af61ad fix(system): update reset reasons for P4 and C5 2024-02-21 11:59:28 +08:00
Marius Vikhammer
c0a2043562 fix(system): update reset reasons for C6 and H2 2024-02-20 12:27:09 +08:00
fl0wl0w
90d1dcfd76 feat(freertos): Introduced new Kconfig option CONFIG_FREERTOS_NUMBER_OF_CORES 
This commit replaces the use of portNUM_PROCESSORS and configNUM_CORES
macros in all of ESP-IDF. These macros are needed to realize an SMP
scenario by fetching the number of active cores FreeRTOS is running on.
Instead, a new Kconfig option, CONFIG_FREERTOS_NUMBER_OF_CORES, has been
added as a proxy for the FreeRTOS config option, configNUMBER_OF_CORES.
This new commit is now used to realize an SMP scenario in various places
in ESP-IDF.

[Sudeep Mohanty: Added new Kconfig option CONFIG_FREERTOS_NUMBER_OF_CORES]

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2024-02-09 09:11:28 +01:00
Song Ruo Jing
d556fee5c4 Merge branch 'feature/esp32c5_clock_preliminary_support' into 'master' 
Feature/esp32c5 clock preliminary support

See merge request espressif/esp-idf!28808
 2024-02-08 11:54:35 +08:00
Song Ruo Jing
95133c179f feat(clk): preliminary clock tree support for ESP32C5 2024-02-07 14:38:15 +08:00
liuning
3fa9c578f9 fix(clk): clear all lpclk source at clk init 2024-02-07 13:49:18 +08:00
laokaiyao
c0c6af99e9 fix(esp32c5): fixed the lack of crosscore ll on c5 2024-02-05 12:39:35 +08:00
Marius Vikhammer
06850e0e1e refactor(system): removed esp_system from astyle ignore list and reformated it 2024-01-30 15:17:15 +08:00
Song Ruo Jing
cf93777077 refactor(rtc): move soc/rtc.h from soc to esp_hw_support component 
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
 2024-01-25 19:15:33 +08:00
Darian Leung
f50d83413e refactor(tools): Tidy up core component files copyright ignore 
Some files that should have their copyrights checked are still placed on the
copyright ignore list.

- These entries have been tidied up
- Copyrights of those files have been updated.
 2024-01-22 18:07:35 +08:00
Darian Leung
06952431a0 refactor(esp_system): Remove intr.c from the esp_system component 
This file is empty and not used anywhere, thus can be removed.
 2024-01-22 18:01:25 +08:00
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
Cao Sen Miao
6768805d20 fix(uart,usj...): Fix wrong serial number that has been parsed to rom functions, 
Closes https://github.com/espressif/esp-idf/issues/12958
 2024-01-18 10:51:51 +08:00
laokaiyao
a48f4760d2 feat(esp32c5): add system related supports 2024-01-02 11:17:11 +08:00
Song Ruo Jing
7f2b85b82b feat(clk): add basic clock support for esp32p4 
- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration
 2023-12-29 00:37:26 +08:00