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fix(system): update reset reasons for P4 and C5

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This commit is contained in:
Marius Vikhammer 2024-02-08 18:17:15 +08:00
parent c0a2043562
commit 4ce4af61ad
7 changed files with 111 additions and 89 deletions
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4
components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
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@ -64,8 +64,8 @@ static void bootloader_check_wdt_reset(void)
{
int wdt_rst = 0;
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if (rst_reason == RESET_REASON_SYS_HP_WDT || rst_reason == RESET_REASON_SYS_LP_WDT || rst_reason == RESET_REASON_CORE_HP_WDT ||
rst_reason == RESET_REASON_CORE_LP_WDT || rst_reason == RESET_REASON_CHIP_LP_WDT) {
if (rst_reason == RESET_REASON_CPU_MWDT || rst_reason == RESET_REASON_CPU_RWDT || rst_reason == RESET_REASON_CORE_MWDT ||
rst_reason == RESET_REASON_CORE_RWDT || rst_reason == RESET_REASON_SYS_RWDT) {
ESP_LOGW(TAG, "CPU has been reset by WDT.");
wdt_rst = 1;
}

76
components/esp_rom/include/esp32c5/rom/rtc.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -75,46 +75,48 @@ typedef enum {
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core (hp system)*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core (hp system)*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core (hp system)*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core (hp system)*/
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core (hp system)*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Power on reset*/
RTC_SW_HPSYS_RESET = 3, /**<3, Software reset hp system*/
SLEEP_WAKEUP = 5, /**<5, Deep Sleep reset hp system*/
TG0_WDT_HPSYS_RESET = 7, /**<7, Timer Group0 Watch dog reset hp system*/
TG1_WDT_HPSYS_RESET = 8, /**<8, Timer Group1 Watch dog reset hp system*/
RTC_WDT_HPSYS_RESET = 9, /**<9, RTC Watch dog Reset hp system*/
TG0_WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTC_WDT_CPU_RESET = 13, /**<13, RTC Watch dog reset CPU*/
RTC_BOD_SYS_RESET = 15, /**<15, System reset when the vdd voltage is not stable*/
RTC_WDT_SYS_RESET = 16, /**<16, RTC Watch dog reset system*/
TG1_WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
RTC_SWDT_SYS_RESET = 18, /**<18, super watchdog reset system*/
EFUSE_HPSYS_RESET = 20, /**<20, efuse reset hp system*/
USB_UART_HPSYS_RESET = 21, /**<21, usb uart reset hp system*/
USB_JTAG_HPSYS_RESET = 22, /**<22, usb jtag reset hp system*/
JTAG_CPU_RESET = 24, /**<24, jtag reset CPU*/
RTC_PWR_GLITCH_RESET = 25, /**<25, RTC power glitch reset system*/
CPU_LOCKUP_RESET = 26, /**<26, cpu lockup reset*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)SDIO_RESET == RESET_REASON_CORE_SDIO, "SDIO_RESET != RESET_REASON_CORE_SDIO");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_HPSYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_HPSYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)SLEEP_WAKEUP == RESET_REASON_CORE_DEEP_SLEEP, "SLEEP_WAKEUP != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0_WDT_HPSYS_RESET == RESET_REASON_CORE_MWDT0, "TG0_WDT_HPSYS_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1_WDT_HPSYS_RESET == RESET_REASON_CORE_MWDT1, "TG1_WDT_HPSYS_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_HPSYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTC_WDT_HPSYS_RESET != RESET_REASON_CORE_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0_WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0_WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTC_WDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_BOD_SYS_RESET == RESET_REASON_SYS_BROWN_OUT, "RTC_BOD_SYS_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_SYS_RESET == RESET_REASON_SYS_RTC_WDT, "RTC_WDT_SYS_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1_WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1_WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SWDT_SYS_RESET == RESET_REASON_SYS_SUPER_WDT, "RTC_SWDT_SYS_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_HPSYS_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_HPSYS_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_HPSYS_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_HPSYS_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_HPSYS_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_HPSYS_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_CPU_RESET == RESET_REASON_CPU0_JTAG, "JTAG_CPU_RESET != RESET_REASON_CPU0_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_PWR_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "RTC_PWR_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU0_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU0_LOCKUP");
typedef enum {
NO_SLEEP = 0,

41
components/esp_rom/include/esp32p4/rom/rtc.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -75,41 +75,42 @@ typedef enum {
POWERON_RESET = 1, /**<1, Vbat power on reset*/
SW_SYS_RESET = 3, /**<3, Software reset digital core*/
PMU_SYS_PWR_DOWN_RESET = 5, /**<5, PMU HP system power down reset*/
PMU_CPU_PWR_DOWN_RESET = 6, /**<6, PMU HP CPU power down reset*/
HP_SYS_HP_WDT_RESET = 7, /**<7, HP system reset from HP watchdog*/
HP_SYS_LP_WDT_RESET = 9, /**<9, HP system reset from LP watchdog*/
HP_CORE_HP_WDT_RESET = 11, /**<11, HP core reset from HP watchdog*/
HP_CORE_SYS_RESET = 12, /**<12, HP core software reset*/
HP_CORE_LP_SYS_RESET = 13, /**<13, HP core reset from LP watchdog*/
SW_CPU_RESET = 12, /**<12, software reset cpu*/
HP_CORE_LP_WDT_RESET = 13, /**<13, HP core reset from LP watchdog*/
BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
LP_WDT_CHIP_RESET = 16, /**<16, Reset chip when LP watchdog trigger*/
CHIP_LP_WDT_RESET = 16, /**<16, LP watchdog chip reset*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset*/
EFUSE_CRC_ERR_RESET = 20, /**<20, efuse ecc error reset*/
HP_SDIO_RESET = 21, /**<21, hp sdio chip reset*/
HP_USB_JTAG_RESET = 22, /**<22, hp usb jtag reset*/
HP_USB_UART_RESET = 23, /**<23, hp usb uart reset*/
CHIP_USB_JTAG_RESET = 22, /**<22, HP usb jtag chip reset*/
CHIP_USB_UART_RESET = 23, /**<23, HP usb uart chip reset*/
JTAG_RESET = 24, /**<24, jtag reset*/
CPU_LOCKUP_RESET = 26, /**<26, cpu lockup reset*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_SYS_RESET == RESET_REASON_CORE_SW, "SW_SYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_SYS_PMU_PWR_DOWN, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_CPU_PWR_DOWN_RESET == RESET_REASON_CPU_PMU_PWR_DOWN, "PMU_CPU_PWR_DOWN_RESET != RESET_REASON_CORE_SDIO");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT_RESET == RESET_REASON_SYS_HP_WDT, "HP_SYS_HP_WDT_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_LP_WDT_RESET == RESET_REASON_SYS_LP_WDT, "HP_SYS_LP_WDT_RESET != RESET_REASON_SYS_LP_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_HP_WDT_RESET == RESET_REASON_CORE_HP_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_HP_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_SYS_RESET == RESET_REASON_CPU0_SW, "HP_CORE_SYS_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_LP_SYS_RESET == RESET_REASON_CORE_LP_WDT, "HP_CORE_LP_SYS_RESET != RESET_REASON_CORE_LP_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_CORE_PMU_PWR_DOWN, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_PMU_PWR_DOWN");
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_CORE_DEEP_SLEEP, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT_RESET == RESET_REASON_CORE_MWDT, "HP_SYS_HP_WDT_RESET != RESET_REASON_CORE_MWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_LP_WDT_RESET == RESET_REASON_CORE_RWDT, "HP_SYS_LP_WDT_RESET != RESET_REASON_CORE_RWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_HP_WDT_RESET == RESET_REASON_CPU_MWDT, "HP_CORE_HP_WDT_RESET != RESET_REASON_CPU_MWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU_SW, "SW_CPU_RESET != RESET_REASON_CPU_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_LP_WDT_RESET == RESET_REASON_CPU_RWDT, "HP_CORE_LP_WDT_RESET != RESET_REASON_CPU_RWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)LP_WDT_CHIP_RESET == RESET_REASON_CHIP_LP_WDT, "LP_WDT_CHIP_RESET != RESET_REASON_CHIP_LP_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_CRC_ERR_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_LP_WDT_RESET == RESET_REASON_SYS_RWDT, "CHIP_LP_WDT_RESET != RESET_REASON_SYS_RWDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_USB_JTAG_RESET == RESET_REASON_CORE_USB_JTAG, "HP_USB_JTAG_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_USB_UART_RESET == RESET_REASON_CORE_USB_UART, "HP_USB_UART_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_CORE_PWR_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_CORE_PWR_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_CRC_ERR_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_USB_JTAG_RESET == RESET_REASON_CORE_USB_JTAG, "CHIP_USB_JTAG_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_USB_UART_RESET == RESET_REASON_CORE_USB_UART, "CHIP_USB_UART_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU_JTAG, "JTAG_RESET != RESET_REASON_CPU_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU_LOCKUP");
typedef enum {

14
components/esp_system/port/soc/esp32c5/reset_reason.c
View File

@ -14,8 +14,6 @@ static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
// TODO: [ESP32C5] IDF-8660
static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{
switch (rtc_reset_reason) {
@ -56,6 +54,18 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CORE_USB_JTAG:
return ESP_RST_USB;
case RESET_REASON_CPU0_JTAG:
return ESP_RST_JTAG;
case RESET_REASON_CPU0_LOCKUP:
return ESP_RST_CPU_LOCKUP;
case RESET_REASON_CORE_EFUSE_CRC:
return ESP_RST_EFUSE;
case RESET_REASON_CORE_PWR_GLITCH:
return ESP_RST_PWR_GLITCH;
default:
return ESP_RST_UNKNOWN;
}

22
components/esp_system/port/soc/esp32p4/reset_reason.c
View File

@ -30,17 +30,16 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
}
return ESP_RST_SW;
case RESET_REASON_SYS_PMU_PWR_DOWN:
case RESET_REASON_CPU_PMU_PWR_DOWN:
case RESET_REASON_CORE_PMU_PWR_DOWN:
/* Check when doing sleep bringup TODO IDF-7529 */
return ESP_RST_DEEPSLEEP;
case RESET_REASON_SYS_HP_WDT:
case RESET_REASON_SYS_LP_WDT:
case RESET_REASON_CPU_MWDT:
case RESET_REASON_CPU_RWDT:
case RESET_REASON_SYS_SUPER_WDT:
case RESET_REASON_CHIP_LP_WDT:
case RESET_REASON_CORE_HP_WDT:
case RESET_REASON_CORE_LP_WDT:
case RESET_REASON_SYS_RWDT:
case RESET_REASON_CORE_MWDT:
case RESET_REASON_CORE_RWDT:
/* Code is the same for INT vs Task WDT */
return ESP_RST_WDT;
@ -54,6 +53,15 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU_JTAG:
return ESP_RST_JTAG;
case RESET_REASON_CPU_LOCKUP:
return ESP_RST_CPU_LOCKUP;
case RESET_REASON_CORE_EFUSE_CRC:
return ESP_RST_EFUSE;
case RESET_REASON_CORE_PWR_GLITCH:
return ESP_RST_PWR_GLITCH;
default:
return ESP_RST_UNKNOWN;
}

4
components/soc/esp32c5/include/soc/reset_reasons.h
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@ -23,7 +23,6 @@ extern "C" {
#endif
// TODO: [ESP32C5] IDF-8660 (inherit from C6)
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
@ -33,7 +32,6 @@ typedef enum {
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core (hp system)
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system)
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system)
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system)
@ -48,6 +46,8 @@ typedef enum {
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system)
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system)
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
RESET_REASON_CORE_PWR_GLITCH = 0x19, // Glitch on power resets the digital core and rtc module
RESET_REASON_CPU0_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
} soc_reset_reason_t;

39
components/soc/esp32p4/include/soc/reset_reasons.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -27,24 +27,25 @@ extern "C" {
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529
RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset
RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset
RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system
RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system
RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0
RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core
RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup TODO IDF-7529
RESET_REASON_CORE_PMU_PWR_DOWN = 0x05, // PMU HP power down core reset
RESET_REASON_CORE_MWDT = 0x07, // MWDT core reset
RESET_REASON_CORE_RWDT = 0x09, // RWDT core reset
RESET_REASON_CPU_MWDT = 0x0B, // MWDT HP CPU 0/1 reset
RESET_REASON_CPU_SW = 0x0C, // Software resets HP CPU 0/1
RESET_REASON_CPU0_SW = 0x0C, // Software resets HP CPU 0, kept to be compatible with older chips
RESET_REASON_CPU_RWDT = 0x0D, // RWDT resets digital core
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RWDT = 0x10, // RWDT system reset
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_CORE_PWR_GLITCH = 0x13, // Glitch on power resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core
RESET_REASON_CPU_JTAG = 0x18, // Triggered when a reset command from JTAG is received
RESET_REASON_CPU_LOCKUP = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
} soc_reset_reason_t;