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feat(system): gate the debug clock source by default for esp32c6 and esp32h2

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This commit is contained in:
wuzhenghui 2023-12-14 18:12:09 +08:00
parent f5707c6ab8
commit 85b246ac88
No known key found for this signature in database
GPG Key ID: 3EFEDECDEBA39BB9
9 changed files with 55 additions and 1 deletions
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9
components/esp_hw_support/esp_clock_output.c
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@ -13,6 +13,7 @@
#include "esp_rom_gpio.h"
#include "clkout_channel.h"
#include "hal/gpio_hal.h"
#include "hal/clk_tree_ll.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
@ -89,6 +90,9 @@ static clkout_channel_handle_t* clkout_channel_alloc(soc_clkout_sig_id_t clk_sig
if (allocated_channel->ref_cnt == 1) {
portENTER_CRITICAL(&s_clkout_lock);
#if SOC_CLOCKOUT_HAS_SOURCE_GATE
clk_ll_enable_clkout_source(clk_sig, true);
#endif
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(allocated_channel->channel_id), CLKOUT_CHANNEL_SHIFT(allocated_channel->channel_id));
portEXIT_CRITICAL(&s_clkout_lock);
}
@ -142,10 +146,13 @@ static void clkout_channel_free(clkout_channel_handle_t *channel_hdl)
{
portENTER_CRITICAL(&channel_hdl->clkout_channel_lock);
if (--channel_hdl->ref_cnt == 0) {
channel_hdl->mapped_clock = CLKOUT_SIG_INVALID;
portENTER_CRITICAL(&s_clkout_lock);
#if SOC_CLOCKOUT_HAS_SOURCE_GATE
clk_ll_enable_clkout_source(channel_hdl->mapped_clock, false);
#endif
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_hdl->channel_id), CLKOUT_CHANNEL_SHIFT(channel_hdl->channel_id));
portEXIT_CRITICAL(&s_clkout_lock);
channel_hdl->mapped_clock = CLKOUT_SIG_INVALID;
channel_hdl->is_mapped = false;
}
portEXIT_CRITICAL(&channel_hdl->clkout_channel_lock);

3
components/esp_system/port/soc/esp32c6/clk.c
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@ -19,6 +19,7 @@
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "esp_cpu.h"
#include "hal/wdt_hal.h"
#include "hal/uart_ll.h"
@ -271,6 +272,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
}
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
@ -283,5 +285,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
}
}

3
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -21,6 +21,7 @@
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/pcr_reg.h"
#include "hal/wdt_hal.h"
#include "hal/uart_ll.h"
@ -261,6 +262,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
}
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
@ -269,5 +271,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
}
}

21
components/hal/esp32c6/include/hal/clk_tree_ll.h
View File

@ -814,6 +814,27 @@ static inline void clk_ll_rc_fast_tick_conf(void)
}
/*
* Enable/Disable the clock gate for clock output signal source
*/
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
{
switch (clk_src)
{
case CLKOUT_SIG_PLL:
PCR.ctrl_clk_out_en.clk160_oen = en;
break;
case CLKOUT_SIG_PLL_F80M:
PCR.ctrl_clk_out_en.clk80_oen = en;
break;
case CLKOUT_SIG_XTAL:
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
break;
default:
break;
}
}
#ifdef __cplusplus
}
#endif

10
components/hal/esp32h2/include/hal/clk_tree_ll.h
View File

@ -749,6 +749,16 @@ static inline void clk_ll_rc_fast_tick_conf(void)
PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
}
/*
* Enable/Disable the clock gate for clock output signal source
*/
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
{
if (clk_src == CLKOUT_SIG_XTAL) {
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
}
}
#ifdef __cplusplus
}
#endif

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -503,6 +503,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 8

1
components/soc/esp32c6/include/soc/soc_caps.h
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@ -210,6 +210,7 @@
// The Clock Out singnal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 8

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -507,6 +507,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
config SOC_CLOCKOUT_HAS_SOURCE_GATE
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 8

1
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -213,6 +213,7 @@
// The Clock Out singnal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported