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refactor(system): removed esp_system from astyle ignore list and reformated it

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This commit is contained in:
Marius Vikhammer 2024-01-30 09:40:10 +08:00
parent da1d587667
commit 06850e0e1e
88 changed files with 734 additions and 808 deletions
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29
components/esp_system/crosscore_int.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,7 +25,6 @@
#define REASON_GDB_CALL BIT(3)
#define REASON_TWDT_ABORT BIT(4)
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t reason[portNUM_PROCESSORS];
@ -38,18 +37,19 @@ static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
portYIELD_FROM_ISR();
}
static void IRAM_ATTR esp_crosscore_isr(void *arg) {
static void IRAM_ATTR esp_crosscore_isr(void *arg)
{
uint32_t my_reason_val;
//A pointer to the correct reason array item is passed to this ISR.
volatile uint32_t *my_reason=arg;
volatile uint32_t *my_reason = arg;
//Clear the interrupt first.
crosscore_int_ll_clear_interrupt(esp_cpu_get_core_id());
//Grab the reason and clear it.
portENTER_CRITICAL_ISR(&reason_spinlock);
my_reason_val=*my_reason;
*my_reason=0;
my_reason_val = *my_reason;
*my_reason = 0;
portEXIT_CRITICAL_ISR(&reason_spinlock);
//Check what we need to do.
@ -72,8 +72,6 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
esp_backtrace_print(100);
}
#if CONFIG_ESP_TASK_WDT_EN
if (my_reason_val & REASON_TWDT_ABORT) {
extern void task_wdt_timeout_abort(bool);
@ -87,13 +85,14 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
//Initialize the crosscore interrupt on this core. Call this once
//on each active core.
void esp_crosscore_int_init(void) {
void esp_crosscore_int_init(void)
{
portENTER_CRITICAL(&reason_spinlock);
reason[esp_cpu_get_core_id()]=0;
reason[esp_cpu_get_core_id()] = 0;
portEXIT_CRITICAL(&reason_spinlock);
esp_err_t err __attribute__((unused)) = ESP_OK;
#if portNUM_PROCESSORS > 1
if (esp_cpu_get_core_id()==0) {
if (esp_cpu_get_core_id() == 0) {
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
} else {
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
@ -104,8 +103,9 @@ void esp_crosscore_int_init(void) {
ESP_ERROR_CHECK(err);
}
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
assert(core_id<portNUM_PROCESSORS);
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
{
assert(core_id < portNUM_PROCESSORS);
//Mark the reason we interrupt the other CPU
portENTER_CRITICAL_ISR(&reason_spinlock);
reason[core_id] |= reason_mask;
@ -135,7 +135,8 @@ void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
}
#if CONFIG_ESP_TASK_WDT_EN
void IRAM_ATTR esp_crosscore_int_send_twdt_abort(int core_id) {
void IRAM_ATTR esp_crosscore_int_send_twdt_abort(int core_id)
{
esp_crosscore_int_send(core_id, REASON_TWDT_ABORT);
}
#endif // CONFIG_ESP_TASK_WDT_EN

4
components/esp_system/debug_stubs.c
View File

@ -27,7 +27,7 @@ const static char *TAG = "esp_dbg_stubs";
#define ESP_DBG_STUBS_CODE_BUF_SIZE 32
#define ESP_DBG_STUBS_STACK_MIN_SIZE 2048
#define DBG_STUB_TRAMP_ATTR IRAM_ATTR
#define DBG_STUB_TRAMP_ATTR IRAM_ATTR
static struct {
uint32_t tramp_addr;
@ -46,7 +46,7 @@ extern void esp_dbg_stubs_ll_init(void *stub_table_addr);
static void * esp_dbg_stubs_data_alloc(uint32_t size)
{
ESP_LOGV(TAG, "%s %"PRIu32, __func__, size);
void *p = malloc(size);
void *p = malloc(size);
ESP_LOGV(TAG, "%s EXIT %p", __func__, p);
return p;
}

351
components/esp_system/eh_frame_parser.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,7 +25,7 @@
#include "esp_private/eh_frame_parser.h"
#if UNW_UNKNOWN_TARGET
#error "Unsupported architecture for unwinding"
#error "Unsupported architecture for unwinding"
#endif
/**
@ -41,15 +41,15 @@
* are encoded.
*/
/* DWARF Exception Exception Header value format. */
#define DW_EH_PE_omit 0xff /*!< No value is present */
#define DW_EH_PE_omit 0xff /*!< No value is present */
#define DW_EH_PE_uleb128 0x01 /*!< Unsigned value encoded in LEB128 (Little Endian Base 128). */
#define DW_EH_PE_udata2 0x02 /*!< Unsigned 16-bit value. */
#define DW_EH_PE_udata4 0x03 /*!< Unsigned 32-bit value. */
#define DW_EH_PE_udata8 0x04 /*!< Unsigned 64-bit value. */
#define DW_EH_PE_udata2 0x02 /*!< Unsigned 16-bit value. */
#define DW_EH_PE_udata4 0x03 /*!< Unsigned 32-bit value. */
#define DW_EH_PE_udata8 0x04 /*!< Unsigned 64-bit value. */
#define DW_EH_PE_sleb128 0x09 /*!< Signed value encoded in LEB128 (Little Endian Base 128). */
#define DW_EH_PE_sdata2 0x0A /*!< Signed 16-bit value. */
#define DW_EH_PE_sdata4 0x0B /*!< Signed 32-bit value. */
#define DW_EH_PE_sdata8 0x0C /*!< Signed 64-bit value. */
#define DW_EH_PE_sdata2 0x0A /*!< Signed 16-bit value. */
#define DW_EH_PE_sdata4 0x0B /*!< Signed 32-bit value. */
#define DW_EH_PE_sdata8 0x0C /*!< Signed 64-bit value. */
/* DWARF Exception Exception Header value application.
* These values are in fact represented in the high nibble of a given data.
@ -188,7 +188,7 @@ typedef struct {
* DW_CFA_REMEMBER_STATE and DW_CFA_RESTORE_STATE instructions.
*/
#if EXECUTION_FRAME_MAX_REGS > 255
#error "Too many registers defined for the target ExecutionFrame"
#error "Too many registers defined for the target ExecutionFrame"
#endif
#define ESP_EH_FRAME_CFA_REG_VALID(reg) (reg < EXECUTION_FRAME_MAX_REGS)
#define ESP_EH_FRAME_CFA_OFF_VALID(off) (((off) >> 24) == 0)
@ -200,7 +200,6 @@ typedef struct {
#define ESP_EH_FRAME_GET_CFA_REG(value) ((value) & 0xff)
#define ESP_EH_FRAME_GET_CFA_OFF(value) ((value) >> 8)
/**
* @brief Unsupported opcode value to return when exeucting 0-opcode type instructions.
*/
@ -250,7 +249,6 @@ typedef struct {
#define DW_LEB128_SIGN_BIT(byte) (((byte) >> 6) & 1)
#define DW_LEB128_MAX_SHIFT (31)
/**
* @brief Symbols defined by the linker.
* Retrieve the addresses of both .eh_frame_hdr and .eh_frame sections.
@ -274,12 +272,13 @@ static uint32_t decode_leb128(const uint8_t* bytes, bool is_signed, uint32_t* le
uint32_t size = 0;
uint8_t byte = 0;
while(1) {
while (1) {
byte = bytes[size++];
res |= (byte & 0x7f) << shf;
shf += 7;
if (DW_LEB128_HIGHEST_BIT(byte) == 0)
if (DW_LEB128_HIGHEST_BIT(byte) == 0) {
break;
}
}
if (is_signed && shf <= DW_LEB128_MAX_SHIFT && DW_LEB128_SIGN_BIT(byte)) {
@ -319,43 +318,43 @@ static uint32_t esp_eh_frame_get_encoded(void* data, uint8_t encoding, uint32_t*
}
switch (low) {
case DW_EH_PE_udata2:
size = 2;
uvalue = *((uint16_t*) data);
break;
case DW_EH_PE_udata4:
size = 4;
uvalue = *((uint32_t*) data);
break;
case DW_EH_PE_sdata2:
size = 2;
svalue = *((int16_t*) data);
break;
case DW_EH_PE_sdata4:
size = 4;
svalue = *((int32_t*) data);
break;
default:
/* Unsupported yet. */
assert(false);
break;
case DW_EH_PE_udata2:
size = 2;
uvalue = *((uint16_t*) data);
break;
case DW_EH_PE_udata4:
size = 4;
uvalue = *((uint32_t*) data);
break;
case DW_EH_PE_sdata2:
size = 2;
svalue = *((int16_t*) data);
break;
case DW_EH_PE_sdata4:
size = 4;
svalue = *((int32_t*) data);
break;
default:
/* Unsupported yet. */
assert(false);
break;
}
switch (high) {
case DW_EH_PE_absptr:
/* Do not change the values, as one of them will be 0, fvalue will
* contain the data no matter whether it is signed or unsigned. */
fvalue = svalue + uvalue;
break;
case DW_EH_PE_pcrel:
/* Relative to the address of the data.
* svalue has been casted to an 32-bit value, so even if it was a
* 2-byte signed value, fvalue will be calculated correctly here. */
fvalue = (uint32_t) data + svalue + uvalue;
break;
case DW_EH_PE_datarel:
fvalue = (uint32_t) EH_FRAME_HDR_ADDR + svalue + uvalue;
break;
case DW_EH_PE_absptr:
/* Do not change the values, as one of them will be 0, fvalue will
* contain the data no matter whether it is signed or unsigned. */
fvalue = svalue + uvalue;
break;
case DW_EH_PE_pcrel:
/* Relative to the address of the data.
* svalue has been casted to an 32-bit value, so even if it was a
* 2-byte signed value, fvalue will be calculated correctly here. */
fvalue = (uint32_t) data + svalue + uvalue;
break;
case DW_EH_PE_datarel:
fvalue = (uint32_t) EH_FRAME_HDR_ADDR + svalue + uvalue;
break;
}
*psize = size;
@ -428,29 +427,31 @@ static const table_entry* esp_eh_frame_find_entry(const table_entry* sorted_tabl
const uint32_t nxt_addr = sorted_table[middle + 1].fun_addr;
if (pc_relative) {
ra = return_address - (uint32_t) (sorted_table + middle);
ra = return_address - (uint32_t)(sorted_table + middle);
}
if (is_signed) {
/* Signed comparisons. */
const int32_t sfun_addr = (int32_t) fun_addr;
const int32_t snxt_addr = (int32_t) nxt_addr;
if (sfun_addr <= ra && snxt_addr > ra)
if (sfun_addr <= ra && snxt_addr > ra) {
found = true;
else if (snxt_addr <= ra)
} else if (snxt_addr <= ra) {
begin = middle + 1;
else
} else {
end = middle;
}
} else {
/* Unsigned comparisons. */
const uint32_t ura = (uint32_t) ra;
if (fun_addr <= ura && nxt_addr > ura)
if (fun_addr <= ura && nxt_addr > ura) {
found = true;
else if (nxt_addr <= ura)
} else if (nxt_addr <= ura) {
begin = middle + 1;
else
} else {
end = middle;
}
}
middle = (end + begin) / 2;
@ -476,12 +477,13 @@ static inline uint32_t* esp_eh_frame_decode_address(const uint32_t* addr,
{
uint32_t* decoded = 0;
if (ESP_ENCODING_FRAME_HDR_REL(encoding))
decoded = (uint32_t*) (*addr + (uint32_t) EH_FRAME_HDR_ADDR);
else if (ESP_ENCODING_PC_REL(encoding))
decoded = (uint32_t*) (*addr + (uint32_t) addr);
else
decoded = (uint32_t*) (*addr);
if (ESP_ENCODING_FRAME_HDR_REL(encoding)) {
decoded = (uint32_t*)(*addr + (uint32_t) EH_FRAME_HDR_ADDR);
} else if (ESP_ENCODING_PC_REL(encoding)) {
decoded = (uint32_t*)(*addr + (uint32_t) addr);
} else {
decoded = (uint32_t*)(*addr);
}
return decoded;
}
@ -503,81 +505,80 @@ static inline uint32_t esp_eh_frame_execute_opcode_0(const uint32_t opcode, cons
uint32_t operand2 = 0;
uint32_t used_operands2 = 0;
switch(opcode) {
case DW_CFA_NOP:
break;
case DW_CFA_ADVANCE_LOC1:
/* Advance location with a 1-byte delta. */
used_operands = 1;
state->location += *operands;
break;
case DW_CFA_ADVANCE_LOC2:
/* Advance location with a 2-byte delta. */
used_operands = 2;
state->location += *((const uint16_t*) operands);
break;
case DW_CFA_ADVANCE_LOC4:
/* Advance location with a 4-byte delta. */
used_operands = 4;
state->location += *((const uint32_t*) operands);
break;
case DW_CFA_REMEMBER_STATE:
assert(state->offset_idx == 0);
memcpy(state->regs_offset[1], state->regs_offset[0],
EXECUTION_FRAME_MAX_REGS * sizeof(uint32_t));
state->offset_idx++;
break;
case DW_CFA_RESTORE_STATE:
assert(state->offset_idx == 1);
/* Drop the saved state. */
state->offset_idx--;
break;
case DW_CFA_DEF_CFA:
/* CFA changes according to a register and an offset.
* This instruction appears when the assembly code saves the
* SP in the middle of a routine, before modifying it.
* For example (on RISC-V):
* addi s0, sp, 80
* addi sp, sp, -10
* ... */
/* Operand1 is the register containing the CFA value. */
operand1 = decode_leb128(operands, false, &used_operands);
/* Offset for the register's value. */
operand2 = decode_leb128(operands + used_operands, false, &used_operands2);
/* Calculate the number of bytes */
used_operands += used_operands2;
/* Assert that the register and the offset are valid. */
assert(ESP_EH_FRAME_CFA_REG_VALID(operand1));
assert(ESP_EH_FRAME_CFA_OFF_VALID(operand2));
ESP_EH_FRAME_CFA(state) = ESP_EH_FRAME_NEW_CFA(operand1, operand2);
break;
case DW_CFA_DEF_CFA_REGISTER:
/* Define the register of the current frame address (CFA).
* Its operand is in the next bytes, its type is ULEB128. */
operand1 = decode_leb128(operands, false, &used_operands);
/* Check whether the value is valid or not. */
assert(ESP_EH_FRAME_CFA_OFF_VALID(operand1));
/* Offset will be unchanged, only register changes. */
ESP_EH_FRAME_CFA(state) = ESP_EH_FRAME_SET_CFA_REG(ESP_EH_FRAME_CFA(state), operand1);
break;
case DW_CFA_DEF_CFA_OFFSET:
/* Same as above but for the offset. The register of CFA remains unchanged. */
operand1 = decode_leb128(operands, false, &used_operands);
assert(ESP_EH_FRAME_CFA_OFF_VALID(operand1));
ESP_EH_FRAME_CFA(state) = ESP_EH_FRAME_SET_CFA_OFF(ESP_EH_FRAME_CFA(state), operand1);
break;
default:
panic_print_str("\r\nUnsupported DWARF opcode 0: 0x");
panic_print_hex(opcode);
panic_print_str("\r\n");
used_operands = ESP_EH_FRAME_UNSUPPORTED_OPCODE;
break;
switch (opcode) {
case DW_CFA_NOP:
break;
case DW_CFA_ADVANCE_LOC1:
/* Advance location with a 1-byte delta. */
used_operands = 1;
state->location += *operands;
break;
case DW_CFA_ADVANCE_LOC2:
/* Advance location with a 2-byte delta. */
used_operands = 2;
state->location += *((const uint16_t*) operands);
break;
case DW_CFA_ADVANCE_LOC4:
/* Advance location with a 4-byte delta. */
used_operands = 4;
state->location += *((const uint32_t*) operands);
break;
case DW_CFA_REMEMBER_STATE:
assert(state->offset_idx == 0);
memcpy(state->regs_offset[1], state->regs_offset[0],
EXECUTION_FRAME_MAX_REGS * sizeof(uint32_t));
state->offset_idx++;
break;
case DW_CFA_RESTORE_STATE:
assert(state->offset_idx == 1);
/* Drop the saved state. */
state->offset_idx--;
break;
case DW_CFA_DEF_CFA:
/* CFA changes according to a register and an offset.
* This instruction appears when the assembly code saves the
* SP in the middle of a routine, before modifying it.
* For example (on RISC-V):
* addi s0, sp, 80
* addi sp, sp, -10
* ... */
/* Operand1 is the register containing the CFA value. */
operand1 = decode_leb128(operands, false, &used_operands);
/* Offset for the register's value. */
operand2 = decode_leb128(operands + used_operands, false, &used_operands2);
/* Calculate the number of bytes */
used_operands += used_operands2;
/* Assert that the register and the offset are valid. */
assert(ESP_EH_FRAME_CFA_REG_VALID(operand1));
assert(ESP_EH_FRAME_CFA_OFF_VALID(operand2));
ESP_EH_FRAME_CFA(state) = ESP_EH_FRAME_NEW_CFA(operand1, operand2);
break;
case DW_CFA_DEF_CFA_REGISTER:
/* Define the register of the current frame address (CFA).
* Its operand is in the next bytes, its type is ULEB128. */
operand1 = decode_leb128(operands, false, &used_operands);
/* Check whether the value is valid or not. */
assert(ESP_EH_FRAME_CFA_OFF_VALID(operand1));
/* Offset will be unchanged, only register changes. */
ESP_EH_FRAME_CFA(state) = ESP_EH_FRAME_SET_CFA_REG(ESP_EH_FRAME_CFA(state), operand1);
break;
case DW_CFA_DEF_CFA_OFFSET:
/* Same as above but for the offset. The register of CFA remains unchanged. */
operand1 = decode_leb128(operands, false, &used_operands);
assert(ESP_EH_FRAME_CFA_OFF_VALID(operand1));
ESP_EH_FRAME_CFA(state) = ESP_EH_FRAME_SET_CFA_OFF(ESP_EH_FRAME_CFA(state), operand1);
break;
default:
panic_print_str("\r\nUnsupported DWARF opcode 0: 0x");
panic_print_hex(opcode);
panic_print_str("\r\n");
used_operands = ESP_EH_FRAME_UNSUPPORTED_OPCODE;
break;
}
return used_operands;
}
/**
* @brief Execute DWARF instructions.
*
@ -603,42 +604,43 @@ static bool esp_eh_frame_execute(const uint8_t* instructions, const uint32_t ins
/* Decode the instructions. According to DWARF documentation, there are three
* types of Call Frame Instructions. The upper 2 bits defines the type. */
switch (DW_GET_OPCODE(instr)) {
case DW_CFA_0_OPCODE:
used_operands = esp_eh_frame_execute_opcode_0(param, &instructions[i + 1], state);
/* Exit the function if an unsupported opcode was met. */
if (used_operands == ESP_EH_FRAME_UNSUPPORTED_OPCODE) {
return false;
}
i += used_operands;
break;
case DW_CFA_ADVANCE_LOC:
/* Move the location forward. This instruction will mark when to stop:
* once we reach the instruction where the PC left, we can break out of the loop
* The delta is part of the lowest 6 bits.
*/
state->location += param;
break;
case DW_CFA_OFFSET:
operand1 = decode_leb128(&instructions[i + 1], false, &size);
assert(ESP_EH_FRAME_CFA_OFFSET_VALID(operand1));
state->regs_offset[state->offset_idx][param] = ESP_EH_FRAME_SET_REG_OFFSET(operand1);
i += size;
break;
case DW_CFA_0_OPCODE:
used_operands = esp_eh_frame_execute_opcode_0(param, &instructions[i + 1], state);
/* Exit the function if an unsupported opcode was met. */
if (used_operands == ESP_EH_FRAME_UNSUPPORTED_OPCODE) {
return false;
}
i += used_operands;
break;
case DW_CFA_ADVANCE_LOC:
/* Move the location forward. This instruction will mark when to stop:
* once we reach the instruction where the PC left, we can break out of the loop
* The delta is part of the lowest 6 bits.
*/
state->location += param;
break;
case DW_CFA_OFFSET:
operand1 = decode_leb128(&instructions[i + 1], false, &size);
assert(ESP_EH_FRAME_CFA_OFFSET_VALID(operand1));
state->regs_offset[state->offset_idx][param] = ESP_EH_FRAME_SET_REG_OFFSET(operand1);
i += size;
break;
case DW_CFA_RESTORE:
state->regs_offset[state->offset_idx][param] = ESP_EH_FRAME_REG_SAME;
break;
default:
/* Illegal opcode */
assert(false);
break;
case DW_CFA_RESTORE:
state->regs_offset[state->offset_idx][param] = ESP_EH_FRAME_REG_SAME;
break;
default:
/* Illegal opcode */
assert(false);
break;
}
/* As the state->location can also be modified by 0-opcode instructions (in the function)
* and also because we need to break the loop (and not only the switch), let's put this
* check here, after the execution of the instruction, outside of the switch block. */
if (state->location >= EXECUTION_FRAME_PC(*frame))
if (state->location >= EXECUTION_FRAME_PC(*frame)) {
break;
}
}
/* Everything went fine, no unsupported opcode was met, return true. */
@ -674,7 +676,7 @@ static uint32_t esp_eh_frame_initialize_state(const uint8_t* cie, ExecutionFrame
uint8_t* cie_data = (uint8_t*) cie + ESP_CIE_VARIABLE_FIELDS_IDX;
/* Next field is a null-terminated UTF-8 string. Ignore it, look for the end. */
while((c = *cie_data++) != 0);
while ((c = *cie_data++) != 0);
/* Field alignment factor shall be 1. It is encoded in ULEB128. */
const uint32_t code_align = decode_leb128(cie_data, false, &size);
@ -739,15 +741,15 @@ static uint32_t esp_eh_frame_restore_caller_state(const uint32_t* fde,
* we have to compute:
* fun_addr = &fde[IDX] +/- fde[IDX]
*/
const uint8_t* cie = (uint8_t*) ((uint32_t) &fde[ESP_FDE_CIE_IDX] - fde[ESP_FDE_CIE_IDX]);
const uint8_t* cie = (uint8_t*)((uint32_t) &fde[ESP_FDE_CIE_IDX] - fde[ESP_FDE_CIE_IDX]);
const uint32_t initial_location = ((uint32_t) &fde[ESP_FDE_INITLOC_IDX] + fde[ESP_FDE_INITLOC_IDX]);
const uint32_t range_length = fde[ESP_FDE_RANGELEN_IDX];
const uint8_t augmentation = *((uint8_t*) (fde + ESP_FDE_AUGMENTATION_IDX));
const uint8_t augmentation = *((uint8_t*)(fde + ESP_FDE_AUGMENTATION_IDX));
/* The length, in byte, of the instructions is the size of the FDE header minus
* the above fields' length. */
const uint32_t instructions_length = length - 3 * sizeof(uint32_t) - sizeof(uint8_t);
const uint8_t* instructions = ((uint8_t*) (fde + ESP_FDE_AUGMENTATION_IDX)) + 1;
const uint8_t* instructions = ((uint8_t*)(fde + ESP_FDE_AUGMENTATION_IDX)) + 1;
/* Make sure this FDE is the correct one for the PC given. */
assert(initial_location <= EXECUTION_FRAME_PC(*frame) &&
@ -817,7 +819,8 @@ static uint32_t esp_eh_frame_restore_caller_state(const uint32_t* fde,
*
* @return true is DWARF information are missing, false else.
*/
static bool esp_eh_frame_missing_info(const uint32_t* fde, uint32_t pc) {
static bool esp_eh_frame_missing_info(const uint32_t* fde, uint32_t pc)
{
if (fde == NULL) {
return true;
}
@ -871,7 +874,7 @@ void esp_eh_frame_print_backtrace(const void *frame_or)
/* Make enc_values point to the end of the structure, where the encoded
* values start. */
enc_values = (uint8_t*) (header + 1);
enc_values = (uint8_t*)(header + 1);
/* Retrieve the encoded value eh_frame_ptr. Get the size of the data also. */
const uint32_t eh_frame_ptr = esp_eh_frame_get_encoded(enc_values, header->eh_frame_ptr_enc, &size);
@ -938,7 +941,8 @@ void esp_eh_frame_print_backtrace(const void *frame_or)
* Check the header libunwind.h for more information
*/
int unw_init_local(unw_cursor_t* c, unw_context_t* ctxt) {
int unw_init_local(unw_cursor_t* c, unw_context_t* ctxt)
{
/* In our implementation, a context and a cursor is the same, so we simply need
* to copy a structure inside another one */
_Static_assert(sizeof(unw_cursor_t) >= sizeof(unw_context_t), "unw_cursor_t size must be greater or equal to unw_context_t's");
@ -950,7 +954,8 @@ int unw_init_local(unw_cursor_t* c, unw_context_t* ctxt) {
return ret;
}
int unw_step(unw_cursor_t* cp) {
int unw_step(unw_cursor_t* cp)
{
static dwarf_regs state = { 0 };
ExecutionFrame* frame = (ExecutionFrame*) cp;
uint32_t size = 0;
@ -964,7 +969,7 @@ int unw_step(unw_cursor_t* cp) {
/* Make enc_values point to the end of the structure, where the encoded
* values start. */
enc_values = (uint8_t*) (header + 1);
enc_values = (uint8_t*)(header + 1);
/* Retrieve the encoded value eh_frame_ptr. Get the size of the data also. */
const uint32_t eh_frame_ptr = esp_eh_frame_get_encoded(enc_values, header->eh_frame_ptr_enc, &size);
@ -978,7 +983,7 @@ int unw_step(unw_cursor_t* cp) {
/* enc_values points now at the beginning of the sorted table. */
/* Only support 4-byte entries. */
const uint32_t table_enc = header->table_enc;
if ( ((table_enc >> 4) != 0x3) && ((table_enc >> 4) != 0xB) ) {
if (((table_enc >> 4) != 0x3) && ((table_enc >> 4) != 0xB)) {
goto badversion;
}
@ -1020,7 +1025,8 @@ stopunwind:
return 0;
}
int unw_get_reg(unw_cursor_t* cp, unw_regnum_t reg, unw_word_t* valp) {
int unw_get_reg(unw_cursor_t* cp, unw_regnum_t reg, unw_word_t* valp)
{
if (cp == NULL || valp == NULL) {
goto invalid;
}
@ -1036,7 +1042,8 @@ badreg:
return -UNW_EBADREG;
}
int unw_set_reg(unw_cursor_t* cp, unw_regnum_t reg, unw_word_t val) {
int unw_set_reg(unw_cursor_t* cp, unw_regnum_t reg, unw_word_t val)
{
if (cp == NULL) {
goto invalid;
}

16
components/esp_system/esp_err.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -14,14 +14,14 @@
#include "esp_rom_sys.h"
#ifndef CONFIG_IDF_TARGET_LINUX
#include "esp_cpu.h"
#include "esp_cpu.h"
#else
/* esp_cpu.h isn't available when building for Linux */
static intptr_t esp_cpu_get_call_addr(intptr_t return_address)
{
/* on x86, there is no hope to get the address of the previous instruction */
return return_address;
}
/* esp_cpu.h isn't available when building for Linux */
static intptr_t esp_cpu_get_call_addr(intptr_t return_address)
{
/* on x86, there is no hope to get the address of the previous instruction */
return return_address;
}
#endif
static void esp_error_check_failed_print(const char *msg, esp_err_t rc, const char *file, int line, const char *function, const char *expression, intptr_t addr)

2
components/esp_system/esp_ipc.c
View File

@ -119,7 +119,7 @@ static void esp_ipc_init(void)
s_ipc_mutex[i] = xSemaphoreCreateMutexStatic(&s_ipc_mutex_buffer[i]);
s_ipc_ack[i] = xSemaphoreCreateBinaryStatic(&s_ipc_ack_buffer[i]);
BaseType_t res = xTaskCreatePinnedToCore(ipc_task, task_name, IPC_STACK_SIZE, (void*) i,
configMAX_PRIORITIES - 1, &s_ipc_task_handle[i], i);
configMAX_PRIORITIES - 1, &s_ipc_task_handle[i], i);
assert(res == pdTRUE);
(void)res;
}

1
components/esp_system/esp_system.c
View File

@ -44,7 +44,6 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
return ESP_ERR_INVALID_STATE;
}
void esp_restart(void)
{
for (int i = SHUTDOWN_HANDLERS_NO - 1; i >= 0; i--) {

50
components/esp_system/freertos_hooks.c
View File

@ -1,10 +1,9 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
@ -25,15 +24,15 @@
#define MAX_HOOKS 8
static portMUX_TYPE hooks_spinlock = portMUX_INITIALIZER_UNLOCKED;
static esp_freertos_idle_cb_t idle_cb[portNUM_PROCESSORS][MAX_HOOKS]={0};
static esp_freertos_tick_cb_t tick_cb[portNUM_PROCESSORS][MAX_HOOKS]={0};
static esp_freertos_idle_cb_t idle_cb[portNUM_PROCESSORS][MAX_HOOKS] = {0};
static esp_freertos_tick_cb_t tick_cb[portNUM_PROCESSORS][MAX_HOOKS] = {0};
void IRAM_ATTR esp_vApplicationTickHook(void)
{
int n;
int core = xPortGetCoreID();
for (n=0; n<MAX_HOOKS; n++) {
if (tick_cb[core][n]!=NULL) {
for (n = 0; n < MAX_HOOKS; n++) {
if (tick_cb[core][n] != NULL) {
tick_cb[core][n]();
}
}
@ -41,7 +40,7 @@ void IRAM_ATTR esp_vApplicationTickHook(void)
void esp_vApplicationIdleHook(void)
{
bool can_go_idle=true;
bool can_go_idle = true;
int core = xPortGetCoreID();
for (int n = 0; n < MAX_HOOKS; n++) {
if (idle_cb[core][n] != NULL && !idle_cb[core][n]()) {
@ -59,18 +58,17 @@ void esp_vApplicationIdleHook(void)
esp_cpu_wait_for_intr();
#endif
}
esp_err_t esp_register_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t new_idle_cb, UBaseType_t cpuid)
{
if(cpuid >= portNUM_PROCESSORS){
if (cpuid >= portNUM_PROCESSORS) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&hooks_spinlock);
for(int n = 0; n < MAX_HOOKS; n++){
if (idle_cb[cpuid][n]==NULL) {
idle_cb[cpuid][n]=new_idle_cb;
for (int n = 0; n < MAX_HOOKS; n++) {
if (idle_cb[cpuid][n] == NULL) {
idle_cb[cpuid][n] = new_idle_cb;
portEXIT_CRITICAL(&hooks_spinlock);
return ESP_OK;
}
@ -86,13 +84,13 @@ esp_err_t esp_register_freertos_idle_hook(esp_freertos_idle_cb_t new_idle_cb)
esp_err_t esp_register_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t new_tick_cb, UBaseType_t cpuid)
{
if(cpuid >= portNUM_PROCESSORS){
if (cpuid >= portNUM_PROCESSORS) {
return ESP_ERR_INVALID_ARG;
}
portENTER_CRITICAL(&hooks_spinlock);
for(int n = 0; n < MAX_HOOKS; n++){
if (tick_cb[cpuid][n]==NULL) {
tick_cb[cpuid][n]=new_tick_cb;
for (int n = 0; n < MAX_HOOKS; n++) {
if (tick_cb[cpuid][n] == NULL) {
tick_cb[cpuid][n] = new_tick_cb;
portEXIT_CRITICAL(&hooks_spinlock);
return ESP_OK;
}
@ -108,12 +106,14 @@ esp_err_t esp_register_freertos_tick_hook(esp_freertos_tick_cb_t new_tick_cb)
void esp_deregister_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t old_idle_cb, UBaseType_t cpuid)
{
if(cpuid >= portNUM_PROCESSORS){
if (cpuid >= portNUM_PROCESSORS) {
return;
}
portENTER_CRITICAL(&hooks_spinlock);
for(int n = 0; n < MAX_HOOKS; n++){
if(idle_cb[cpuid][n] == old_idle_cb) idle_cb[cpuid][n] = NULL;
for (int n = 0; n < MAX_HOOKS; n++) {
if (idle_cb[cpuid][n] == old_idle_cb) {
idle_cb[cpuid][n] = NULL;
}
}
portEXIT_CRITICAL(&hooks_spinlock);
}
@ -121,7 +121,7 @@ void esp_deregister_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t old_idle_c
void esp_deregister_freertos_idle_hook(esp_freertos_idle_cb_t old_idle_cb)
{
portENTER_CRITICAL(&hooks_spinlock);
for(int m = 0; m < portNUM_PROCESSORS; m++) {
for (int m = 0; m < portNUM_PROCESSORS; m++) {
esp_deregister_freertos_idle_hook_for_cpu(old_idle_cb, m);
}
portEXIT_CRITICAL(&hooks_spinlock);
@ -129,12 +129,14 @@ void esp_deregister_freertos_idle_hook(esp_freertos_idle_cb_t old_idle_cb)
void esp_deregister_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t old_tick_cb, UBaseType_t cpuid)
{
if(cpuid >= portNUM_PROCESSORS){
if (cpuid >= portNUM_PROCESSORS) {
return;
}
portENTER_CRITICAL(&hooks_spinlock);
for(int n = 0; n < MAX_HOOKS; n++){
if(tick_cb[cpuid][n] == old_tick_cb) tick_cb[cpuid][n] = NULL;
for (int n = 0; n < MAX_HOOKS; n++) {
if (tick_cb[cpuid][n] == old_tick_cb) {
tick_cb[cpuid][n] = NULL;
}
}
portEXIT_CRITICAL(&hooks_spinlock);
}
@ -142,7 +144,7 @@ void esp_deregister_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t old_tick_c
void esp_deregister_freertos_tick_hook(esp_freertos_tick_cb_t old_tick_cb)
{
portENTER_CRITICAL(&hooks_spinlock);
for(int m = 0; m < portNUM_PROCESSORS; m++){
for (int m = 0; m < portNUM_PROCESSORS; m++) {
esp_deregister_freertos_tick_hook_for_cpu(old_tick_cb, m);
}
portEXIT_CRITICAL(&hooks_spinlock);

1
components/esp_system/hw_stack_guard.c
View File

@ -47,7 +47,6 @@ ESP_SYSTEM_INIT_FN(esp_hw_stack_guard_init, SECONDARY, ESP_SYSTEM_INIT_ALL_CORES
return ESP_OK;
}
/* The functions below are designed to be used in interrupt/panic handler
* In case using them in user's code put them into critical section */

7
components/esp_system/include/esp_expression_with_stack.h
View File

@ -45,10 +45,9 @@ typedef void (*shared_stack_function)(void);
* be called using the current stack.
*/
void esp_execute_shared_stack_function(SemaphoreHandle_t lock,
void *stack,
size_t stack_size,
shared_stack_function function);
void *stack,
size_t stack_size,
shared_stack_function function);
#ifdef __cplusplus
}

1
components/esp_system/include/esp_ipc.h
View File

@ -52,7 +52,6 @@ typedef void (*esp_ipc_func_t)(void* arg);
*/
esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
/**
* @brief Execute a callback on a given CPU until and block until it completes
*

26
components/esp_system/include/esp_private/critical_section.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -227,9 +227,9 @@ typedef spinlock_t esp_os_spinlock_t;
* @endcode
*/
#if OS_SPINLOCK == 1
#define esp_os_enter_critical(lock) portENTER_CRITICAL(lock)
#define esp_os_enter_critical(lock) portENTER_CRITICAL(lock)
#else
#define esp_os_enter_critical(lock) vPortEnterCritical()
#define esp_os_enter_critical(lock) vPortEnterCritical()
#endif
/**
@ -256,9 +256,9 @@ typedef spinlock_t esp_os_spinlock_t;
* @endcode
*/
#if OS_SPINLOCK == 1
#define esp_os_exit_critical(lock) portEXIT_CRITICAL(lock)
#define esp_os_exit_critical(lock) portEXIT_CRITICAL(lock)
#else
#define esp_os_exit_critical(lock) vPortExitCritical()
#define esp_os_exit_critical(lock) vPortExitCritical()
#endif
/**
@ -285,9 +285,9 @@ typedef spinlock_t esp_os_spinlock_t;
* @endcode
*/
#if OS_SPINLOCK == 1
#define esp_os_enter_critical_isr(lock) portENTER_CRITICAL_ISR(lock)
#define esp_os_enter_critical_isr(lock) portENTER_CRITICAL_ISR(lock)
#else
#define esp_os_enter_critical_isr(lock) vPortEnterCritical()
#define esp_os_enter_critical_isr(lock) vPortEnterCritical()
#endif
/**
@ -314,9 +314,9 @@ typedef spinlock_t esp_os_spinlock_t;
* @endcode
*/
#if OS_SPINLOCK == 1
#define esp_os_exit_critical_isr(lock) portEXIT_CRITICAL_ISR(lock)
#define esp_os_exit_critical_isr(lock) portEXIT_CRITICAL_ISR(lock)
#else
#define esp_os_exit_critical_isr(lock) vPortExitCritical()
#define esp_os_exit_critical_isr(lock) vPortExitCritical()
#endif
/**
@ -344,9 +344,9 @@ typedef spinlock_t esp_os_spinlock_t;
* @endcode
*/
#if OS_SPINLOCK == 1
#define esp_os_enter_critical_safe(lock) portENTER_CRITICAL_SAFE(lock)
#define esp_os_enter_critical_safe(lock) portENTER_CRITICAL_SAFE(lock)
#else
#define esp_os_enter_critical_safe(lock) vPortEnterCritical()
#define esp_os_enter_critical_safe(lock) vPortEnterCritical()
#endif
/**
@ -373,9 +373,9 @@ typedef spinlock_t esp_os_spinlock_t;
* @endcode
*/
#if OS_SPINLOCK == 1
#define esp_os_exit_critical_safe(lock) portEXIT_CRITICAL_SAFE(lock)
#define esp_os_exit_critical_safe(lock) portEXIT_CRITICAL_SAFE(lock)
#else
#define esp_os_exit_critical_safe(lock) vPortExitCritical()
#define esp_os_exit_critical_safe(lock) vPortExitCritical()
#endif
#ifdef __cplusplus

2
components/esp_system/include/esp_private/crosscore_int.h
View File

@ -23,7 +23,6 @@ extern "C" {
*/
void esp_crosscore_int_init(void);
/**
* Send an interrupt to a CPU indicating it should yield its
* currently running task in favour of a higher-priority task
@ -36,7 +35,6 @@ void esp_crosscore_int_init(void);
*/
void esp_crosscore_int_send_yield(int core_id);
/**
* Send an interrupt to a CPU indicating it should update its
* CCOMPARE1 value due to a frequency switch.

8
components/esp_system/include/esp_private/dbg_stubs.h
View File

@ -21,8 +21,8 @@ typedef enum {
ESP_DBG_STUB_TABLE_SIZE,
ESP_DBG_STUB_CONTROL_DATA, ///< stubs descriptor entry
ESP_DBG_STUB_ENTRY_FIRST,
ESP_DBG_STUB_ENTRY_GCOV ///< GCOV entry
= ESP_DBG_STUB_ENTRY_FIRST,
ESP_DBG_STUB_ENTRY_GCOV ///< GCOV entry
= ESP_DBG_STUB_ENTRY_FIRST,
ESP_DBG_STUB_ENTRY_CAPABILITIES,
ESP_DBG_STUB_ENTRY_MAX
} esp_dbg_stub_id_t;
@ -42,7 +42,7 @@ void esp_dbg_stubs_init(void);
*
* @note Should be called before any esp_apptrace_xxx call.
*
* @param id Stub ID.
* @param id Stub ID.
* @param entry Stub entry. Usually it is stub entry function address,
* but can be any value meaningfull for OpenOCD command/code
* such as capabilities
@ -53,7 +53,7 @@ esp_err_t esp_dbg_stub_entry_set(esp_dbg_stub_id_t id, uint32_t entry);
/**
* @brief Retrives the corresponding stub entry
*
* @param id Stub ID.
* @param id Stub ID.
* @param entry Stub entry. Usually it is stub entry function address,
* but can be any value meaningfull for OpenOCD command/code
* such as capabilities

1
components/esp_system/include/esp_private/eh_frame_parser.h
View File

@ -24,5 +24,4 @@ void esp_eh_frame_print_backtrace(const void *frame_or);
}
#endif
#endif // EH_FRAME_PARSER_H

1
components/esp_system/include/esp_private/esp_int_wdt.h
View File

@ -10,7 +10,6 @@
extern "C" {
#endif
/**
* @brief Initialize the non-CPU-specific parts of interrupt watchdog.
*

9
components/esp_system/include/esp_private/esp_task_wdt_impl.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -14,7 +14,6 @@
extern "C" {
#endif
/**
* @brief Allocate and initialize the Task Watchdog Timer (TWDT) with the given configuration.
*
@ -29,7 +28,6 @@ esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
twdt_isr_callback callback,
twdt_ctx_t *obj);
/**
* @brief Reconfigure a timer.
*
@ -52,7 +50,6 @@ esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt
*/
void esp_task_wdt_impl_timer_free(twdt_ctx_t obj);
/**
* @brief Feed the Task Watchdog Timer (TWDT)
*
@ -65,7 +62,6 @@ void esp_task_wdt_impl_timer_free(twdt_ctx_t obj);
*/
esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj);
/**
* @brief Function invoked as soon as the Task Watchdog Timer (TWDT) ISR callback is called.
*
@ -73,7 +69,6 @@ esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj);
*/
void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj);
/**
* @brief Stop the Task Watchdog Timer (TWDT).
*
@ -82,7 +77,6 @@ void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj);
*/
esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj);
/**
* @brief Restart the Task Watchdog Timer (TWDT)
*
@ -95,7 +89,6 @@ esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj);
*/
esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj);
#ifdef __cplusplus
}
#endif

1
components/esp_system/include/esp_private/panic_internal.h
View File

@ -14,7 +14,6 @@
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif

7
components/esp_system/include/esp_private/startup_internal.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -19,7 +19,6 @@
extern "C" {
#endif
// Port layer defines the entry point. It then transfer control to a `sys_startup_fn_t`, stored in this
// array, one per core.
typedef void (*sys_startup_fn_t)(void);
@ -87,8 +86,8 @@ typedef struct {
#endif
extern uint64_t g_startup_time; // Startup time that serves as the point of origin for system time. Should be set by the entry
// function in the port layer. May be 0 as well if this is not backed by a persistent counter, in which case
// startup time = system time = 0 at the point the entry function sets this variable.
// function in the port layer. May be 0 as well if this is not backed by a persistent counter, in which case
// startup time = system time = 0 at the point the entry function sets this variable.
#ifdef __cplusplus
}

4
components/esp_system/include/esp_private/system_internal.h
View File

@ -29,12 +29,12 @@ extern "C" {
* This is an internal function called by esp_restart. It is called directly
* by the panic handler and brownout detector interrupt.
*/
void esp_restart_noos(void) __attribute__ ((noreturn));
void esp_restart_noos(void) __attribute__((noreturn));
/**
* @brief Similar to esp_restart_noos, but resets all the digital peripherals.
*/
void esp_restart_noos_dig(void) __attribute__ ((noreturn));
void esp_restart_noos_dig(void) __attribute__((noreturn));
/**
* @brief Internal function to set reset reason hint

1
components/esp_system/include/esp_private/usb_console.h
View File

@ -24,7 +24,6 @@ extern "C" {
* "cdcacm" VFS driver, or by the USB CDC driver in TinyUSB.
*/
/**
* RX/TX callback function type
* @param arg callback-specific context pointer

7
components/esp_system/include/esp_system.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -65,7 +65,6 @@ esp_err_t esp_register_shutdown_handler(shutdown_handler_t handle);
*/
esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handle);
/**
* @brief Restart PRO and APP CPUs.
*
@ -74,7 +73,7 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handle);
* Peripherals (except for Wi-Fi, BT, UART0, SPI1, and legacy timers) are not reset.
* This function does not return.
*/
void esp_restart(void) __attribute__ ((__noreturn__));
void esp_restart(void) __attribute__((__noreturn__));
/**
* @brief Get reason of last reset
@ -107,7 +106,7 @@ uint32_t esp_get_free_internal_heap_size(void);
*
* @return Minimum free heap ever available
*/
uint32_t esp_get_minimum_free_heap_size( void );
uint32_t esp_get_minimum_free_heap_size(void);
/**
* @brief Trigger a software abort

1
components/esp_system/include/esp_task.h
View File

@ -42,7 +42,6 @@
/* Ping Task */
#define ESP_TASK_PING_STACK (2048 + TASK_EXTRA_STACK_SIZE)
/* idf task */
#define ESP_TASK_TIMER_PRIO (ESP_TASK_PRIO_MAX - 3)
#define ESP_TASK_TIMER_STACK (CONFIG_ESP_TIMER_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)

18
components/esp_system/include/libunwind.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,16 +11,16 @@
#include <stdint.h>
#if CONFIG_IDF_TARGET_ARCH_RISCV
#include "libunwind-riscv.h"
#include "libunwind-riscv.h"
#elif CONFIG_IDF_TARGET_X86
#include "libunwind-x86.h"
#include "libunwind-x86.h"
#else
/* This header must be a standalone one, so, it shall not trigger an error when
* pre-processed without including any of the architecture header above.
* The implementation can trigger a compile error if UNW_UNKNOWN_TARGET
* macro is defined. */
#define UNW_UNKNOWN_TARGET 1
typedef void* ExecutionFrame;
/* This header must be a standalone one, so, it shall not trigger an error when
* pre-processed without including any of the architecture header above.
* The implementation can trigger a compile error if UNW_UNKNOWN_TARGET
* macro is defined. */
#define UNW_UNKNOWN_TARGET 1
typedef void* ExecutionFrame;
#endif
#ifdef __cplusplus

16
components/esp_system/int_wdt.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -123,16 +123,16 @@ void esp_int_wdt_init(void)
wdt_hal_write_protect_enable(&iwdt_context);
#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#define APB_DCRSET (0x200c)
#define APB_ITCTRL (0x3f00)
#define ERI_ADDR(APB) (0x100000 + (APB))
#define _SYM2STR(x) # x
#define SYM2STR(x) _SYM2STR(x)
#define APB_DCRSET (0x200c)
#define APB_ITCTRL (0x3f00)
#define ERI_ADDR(APB) (0x100000 + (APB))
#define _SYM2STR(x) # x
#define SYM2STR(x) _SYM2STR(x)
uint32_t eriadrs, scratch = 0, immediate = 0;
if (soc_has_cache_lock_bug()) {
if (xPortGetCoreID() != CONFIG_BTDM_CTRL_PINNED_TO_CORE) {
__asm__ __volatile__ (
__asm__ __volatile__(
/* Enable Xtensa Debug Module Integration Mode */
"movi %[ERI], " SYM2STR(ERI_ADDR(APB_ITCTRL)) "\n"
"rer %[REG], %[ERI]\n"
@ -145,7 +145,7 @@ void esp_int_wdt_init(void)
"movi %[IMM], 0x10000\n"
"or %[REG], %[IMM], %[REG]\n"
"wer %[REG], %[ERI]\n"
: [ERI] "=r" (eriadrs), [REG] "+r" (scratch), [IMM] "+r" (immediate)
: [ERI] "=r"(eriadrs), [REG] "+r"(scratch), [IMM] "+r"(immediate)
);
}
}

33
components/esp_system/panic.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -68,7 +68,7 @@
#include "riscv/semihosting.h"
#endif
#define ESP_SEMIHOSTING_SYS_PANIC_REASON 0x116
#define ESP_SEMIHOSTING_SYS_PANIC_REASON 0x116
#define MWDT_DEFAULT_TICKS_PER_US 500
@ -90,7 +90,6 @@ static void panic_print_char_uart(const char c)
}
#endif // CONFIG_ESP_CONSOLE_UART
#if CONFIG_ESP_CONSOLE_USB_CDC
static void panic_print_char_usb_cdc(const char c)
{
@ -119,7 +118,6 @@ static void panic_print_char_usb_serial_jtag(const char c)
}
#endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG || CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
void panic_print_char(const char c)
{
#if CONFIG_ESP_CONSOLE_UART
@ -186,7 +184,7 @@ void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms)
{
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
#if SOC_TIMER_GROUPS >= 2
// IDF-3825
// IDF-3825
wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
#endif
@ -298,17 +296,17 @@ void esp_panic_handler(panic_info_t *info)
// in debug mode.
#if CONFIG_ESP_DEBUG_OCDAWARE
if (esp_cpu_dbgr_is_attached()) {
char *panic_reason_str = NULL;
if (info->pseudo_excause) {
panic_reason_str = (char *)info->reason;
} else if (g_panic_abort && strlen(g_panic_abort_details)) {
panic_reason_str = g_panic_abort_details;
}
if (panic_reason_str) {
/* OpenOCD will print the halt cause when target is stopped at the below breakpoint (info->addr) */
long args[] = {(long)panic_reason_str, strlen(panic_reason_str)};
semihosting_call_noerrno(ESP_SEMIHOSTING_SYS_PANIC_REASON, args);
}
char *panic_reason_str = NULL;
if (info->pseudo_excause) {
panic_reason_str = (char *)info->reason;
} else if (g_panic_abort && strlen(g_panic_abort_details)) {
panic_reason_str = g_panic_abort_details;
}
if (panic_reason_str) {
/* OpenOCD will print the halt cause when target is stopped at the below breakpoint (info->addr) */
long args[] = {(long)panic_reason_str, strlen(panic_reason_str)};
semihosting_call_noerrno(ESP_SEMIHOSTING_SYS_PANIC_REASON, args);
}
panic_print_str("Setting breakpoint at 0x");
panic_print_hex((uint32_t)info->addr);
panic_print_str(" and returning...\r\n");
@ -402,7 +400,7 @@ void esp_panic_handler(panic_info_t *info)
// start RTC WDT if it hasn't been started yet and set the timeout to more than the delay time
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
uint32_t stage_timeout_ticks = (uint32_t)(((CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS + 1) * 1000
* rtc_clk_slow_freq_get_hz()) / 1000ULL);
* rtc_clk_slow_freq_get_hz()) / 1000ULL);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
// 64KB of core dump data (stacks of about 30 tasks) will produce ~85KB base64 data.
@ -454,7 +452,6 @@ void esp_panic_handler(panic_info_t *info)
#endif /* CONFIG_ESP_SYSTEM_PANIC_GDBSTUB */
}
void IRAM_ATTR __attribute__((noreturn, no_sanitize_undefined)) panic_abort(const char *details)
{
g_panic_abort = true;

12
components/esp_system/port/arch/riscv/debug_helpers.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -48,12 +48,12 @@ esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
void *frame = snapshot.pxTopOfStack;
#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
esp_rom_printf("Print CPU %d (current core) backtrace\n", current_core);
esp_eh_frame_print_backtrace(frame);
esp_rom_printf("Print CPU %d (current core) backtrace\n", current_core);
esp_eh_frame_print_backtrace(frame);
#else // CONFIG_ESP_SYSTEM_USE_EH_FRAME
esp_rom_printf("Print CPU %d (current core) registers\n", current_core);
panic_print_registers(frame, current_core);
esp_rom_printf("\r\n");
esp_rom_printf("Print CPU %d (current core) registers\n", current_core);
panic_print_registers(frame, current_core);
esp_rom_printf("\r\n");
#endif // CONFIG_ESP_SYSTEM_USE_EH_FRAME
return ESP_OK;

1
components/esp_system/port/arch/riscv/debug_stubs.c
View File

@ -14,7 +14,6 @@
const static char *TAG = "esp_dbg_stubs";
/* Advertises apptrace control block address to host */
static int esp_dbg_stubs_advertise_table(void *stub_table_addr)
{

3
components/esp_system/port/arch/riscv/esp_ipc_isr_port.c
View File

@ -14,7 +14,6 @@
#include "esp_attr.h"
#include "sdkconfig.h"
void esp_ipc_isr_port_init(const int cpuid)
{
uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE
@ -30,7 +29,7 @@ void esp_ipc_isr_port_init(const int cpuid)
#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
esp_cpu_intr_set_priority(ETS_IPC_ISR_INUM, 4);
#else
#error "CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL is not defined!"
#error "CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL is not defined!"
#endif
esp_intr_enable_source(ETS_IPC_ISR_INUM);

2
components/esp_system/port/arch/riscv/esp_ipc_isr_routines.c
View File

@ -8,5 +8,5 @@
void esp_ipc_isr_waiting_for_finish_cmd(void* ipc_isr_finish_cmd)
{
while (*(volatile uint32_t*)ipc_isr_finish_cmd == 0) { };
while (*(volatile uint32_t *)ipc_isr_finish_cmd == 0) { };
}

19
components/esp_system/port/arch/riscv/expression_with_stack.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -21,7 +21,7 @@ static StackType_t *esp_shared_stack_setup_context(StaticTask_t *tcb, void **sp_
memset(stack, 0xa5U, stack_size * sizeof(StackType_t));
//Align stack to a 16-byte boundary, as required by CPU specific:
StackType_t *top_of_stack = (StackType_t *) ALIGNUP(0x10, (uint32_t) (stack + stack_size));
StackType_t *top_of_stack = (StackType_t *) ALIGNUP(0x10, (uint32_t)(stack + stack_size));
StackType_t *adjusted_top_of_stack = top_of_stack - RV_STK_FRMSZ;
//Then put the fake stack inside of TCB:
@ -41,7 +41,8 @@ static StackType_t *esp_shared_stack_setup_context(StaticTask_t *tcb, void **sp_
return ((StackType_t *)adjusted_top_of_stack);
}
static void esp_shared_stack_restore_context(StaticTask_t *tcb, void *sp_min, void *sp_max) {
static void esp_shared_stack_restore_context(StaticTask_t *tcb, void *sp_min, void *sp_max)
{
tcb->pxDummy6 = sp_min;
tcb->pxDummy8 = sp_max;
@ -70,11 +71,11 @@ void esp_execute_shared_stack_function(SemaphoreHandle_t lock, void *stack, size
portENTER_CRITICAL(&shared_stack_spinlock);
stack = esp_shared_stack_setup_context(tcb, &sp_min, &sp_max, stack, stack_size);
__asm__ volatile ("mv t0, sp \n" /* save current SP */
"mv sp, %0 \n" /* set shared stack as new SP */
"addi sp, sp, -16 \n" /* allocate memory for previous SP */
"sw t0, 0(sp) \n" /* store previous SP in a safe place */
:: "r"(stack));
__asm__ volatile("mv t0, sp \n" /* save current SP */
"mv sp, %0 \n" /* set shared stack as new SP */
"addi sp, sp, -16 \n" /* allocate memory for previous SP */
"sw t0, 0(sp) \n" /* store previous SP in a safe place */
:: "r"(stack));
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
esp_hw_stack_guard_monitor_start();
#endif
@ -86,7 +87,7 @@ void esp_execute_shared_stack_function(SemaphoreHandle_t lock, void *stack, size
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
esp_hw_stack_guard_monitor_stop();
#endif
__asm__ volatile ("lw sp, 0(sp)"); /* restore real SP of current task */
__asm__ volatile("lw sp, 0(sp)"); /* restore real SP of current task */
esp_shared_stack_restore_context(tcb, sp_min, sp_max);
portEXIT_CRITICAL(&shared_stack_spinlock);

14
components/esp_system/port/arch/riscv/panic_arch.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -38,7 +38,6 @@
#include "esp_private/hw_stack_guard.h"
#endif
#define DIM(array) (sizeof(array)/sizeof(*array))
/**
@ -77,7 +76,7 @@ static inline void print_assist_debug_details(const void *frame)
panic_print_hex((int) esp_hw_stack_guard_get_pc());
panic_print_str("\r\n");
panic_print_str("Stack pointer: 0x");
panic_print_hex((int) ((RvExcFrame *)frame)->sp);
panic_print_hex((int)((RvExcFrame *)frame)->sp);
panic_print_str("\r\n");
panic_print_str("Stack bounds: 0x");
panic_print_hex((int) sp_min);
@ -123,7 +122,7 @@ static inline void print_memprot_err_details(const void *frame __attribute__((un
PRINT_MEMPROT_ERROR(res);
}
panic_print_str( "\r\n world: ");
panic_print_str("\r\n world: ");
esp_mprot_pms_world_t world;
res = esp_mprot_get_violate_world(s_memp_intr.mem_type, &world, s_memp_intr.core);
if (res == ESP_OK) {
@ -132,7 +131,7 @@ static inline void print_memprot_err_details(const void *frame __attribute__((un
PRINT_MEMPROT_ERROR(res);
}
panic_print_str( "\r\n operation type: ");
panic_print_str("\r\n operation type: ");
uint32_t operation;
res = esp_mprot_get_violate_operation(s_memp_intr.mem_type, &operation, s_memp_intr.core);
if (res == ESP_OK) {
@ -142,7 +141,7 @@ static inline void print_memprot_err_details(const void *frame __attribute__((un
}
if (esp_mprot_has_byte_enables(s_memp_intr.mem_type)) {
panic_print_str("\r\n byte-enables: " );
panic_print_str("\r\n byte-enables: ");
uint32_t byte_enables;
res = esp_mprot_get_violate_byte_enables(s_memp_intr.mem_type, &byte_enables, s_memp_intr.core);
if (res == ESP_OK) {
@ -170,7 +169,6 @@ static void panic_print_register_array(const char* names[], const uint32_t* regs
}
}
void panic_print_registers(const void *f, int core)
{
/**
@ -203,7 +201,7 @@ bool panic_soc_check_pseudo_cause(void *f, panic_info_t *info)
/* Cache errors when reading instructions will result in an illegal instructions,
before any cache error interrupts trigger. We override the exception cause if
any cache errors are active to more accurately report the actual reason */
if(esp_cache_err_has_active_err() && (frame->mcause == MCAUSE_ILLEGAL_INSTRUCTION) ) {
if (esp_cache_err_has_active_err() && (frame->mcause == MCAUSE_ILLEGAL_INSTRUCTION)) {
pseudo_cause = true;
frame->mcause = ETS_CACHEERR_INUM;
}

2
components/esp_system/port/arch/xtensa/debug_helpers.c
View File

@ -227,7 +227,7 @@ esp_err_t IRAM_ATTR esp_backtrace_print_all_tasks(int depth)
}
// Print backtrace
char* name = pcTaskGetName(task_hdl);
print_str(name ? name : "No Name" , false);
print_str(name ? name : "No Name", false);
esp_err_t bt_ret = esp_backtrace_print_from_frame(depth, &stk_frame, false);
if (bt_ret != ESP_OK) {
ret = bt_ret;

1
components/esp_system/port/arch/xtensa/esp_ipc_isr_port.c
View File

@ -15,7 +15,6 @@
#include "esp_attr.h"
#include "sdkconfig.h"
void esp_ipc_isr_port_init(const int cpuid)
{
uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE + cpuid; // ETS_FROM_CPU_INTR2_SOURCE and ETS_FROM_CPU_INTR3_SOURCE

7
components/esp_system/port/arch/xtensa/expression_with_stack.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,7 +33,7 @@ static void esp_switch_stack_setup(StackType_t *stack, size_t stack_size)
StackType_t *top_of_stack = stack + stack_size;
//Align stack to a 16byte boundary, as required by CPU specific:
top_of_stack = (StackType_t *)(((UBaseType_t)(top_of_stack - 16) & ~0xf));
top_of_stack = (StackType_t *)(((UBaseType_t)(top_of_stack - 16) & ~0xf));
#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
vPortSetStackWatchpoint(stack);
@ -42,7 +42,6 @@ static void esp_switch_stack_setup(StackType_t *stack, size_t stack_size)
xtensa_shared_stack = top_of_stack;
}
void esp_execute_shared_stack_function(SemaphoreHandle_t lock, void *stack, size_t stack_size, shared_stack_function function)
{
assert(lock);
@ -58,7 +57,7 @@ void esp_execute_shared_stack_function(SemaphoreHandle_t lock, void *stack, size
portEXIT_CRITICAL(&xtensa_shared_stack_spinlock);
setjmp(xtensa_shared_stack_env);
if(!xtensa_shared_stack_function_done) {
if (!xtensa_shared_stack_function_done) {
esp_shared_stack_invoke_function();
}

8
components/esp_system/port/arch/xtensa/panic_arch.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -120,7 +120,6 @@ static void print_illegal_instruction_details(const void *f)
panic_print_hex(*(pepc + 2));
}
static void print_debug_exception_details(const void *f)
{
int debug_rsn;
@ -360,7 +359,6 @@ static inline void print_cache_err_details(const void *f)
}
#endif
void panic_arch_fill_info(void *f, panic_info_t *info)
{
XtExcFrame *frame = (XtExcFrame *) f;
@ -389,7 +387,7 @@ void panic_arch_fill_info(void *f, panic_info_t *info)
info->details = print_illegal_instruction_details;
}
info->addr = ((void *) ((XtExcFrame *) frame)->pc);
info->addr = ((void *)((XtExcFrame *) frame)->pc);
}
/**
@ -447,7 +445,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if (frame->exccause == PANIC_RSN_CACHEERR) {
#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && CONFIG_IDF_TARGET_ESP32S2
if ( esp_memprot_is_intr_ena_any() ) {
if (esp_memprot_is_intr_ena_any()) {
info->details = print_memprot_err_details;
info->reason = "Memory protection fault";
} else

14
components/esp_system/port/arch/xtensa/trax.c
View File

@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -32,10 +32,12 @@ int trax_enable(trax_ena_select_t which)
#endif
#if CONFIG_IDF_TARGET_ESP32
#ifndef CONFIG_ESP32_TRAX_TWOBANKS
if (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP) return ESP_ERR_NO_MEM;
if (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP) {
return ESP_ERR_NO_MEM;
}
#endif
if (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP) {
trace_ll_set_mode((which == TRAX_ENA_PRO_APP_SWAP)?TRACEMEM_MUX_PROBLK1_APPBLK0:TRACEMEM_MUX_PROBLK0_APPBLK1);
trace_ll_set_mode((which == TRAX_ENA_PRO_APP_SWAP) ? TRACEMEM_MUX_PROBLK1_APPBLK0 : TRACEMEM_MUX_PROBLK0_APPBLK1);
} else {
trace_ll_set_mode(TRACEMEM_MUX_BLK0_ONLY);
}
@ -51,16 +53,14 @@ int trax_enable(trax_ena_select_t which)
#elif CONFIG_IDF_TARGET_ESP32S3
if (which == TRAX_ENA_PRO) {
trace_ll_set_mem_block(0, TRACEMEM_MUX_BLK0_NUM);
}
else if (which == TRAX_ENA_APP) {
} else if (which == TRAX_ENA_APP) {
trace_ll_set_mem_block(1, TRACEMEM_MUX_BLK0_NUM);
}
#ifdef CONFIG_ESP32S3_TRAX_TWOBANKS
else if (which == TRAX_ENA_PRO_APP) {
trace_ll_set_mem_block(0, TRACEMEM_MUX_BLK0_NUM);
trace_ll_set_mem_block(1, TRACEMEM_MUX_BLK1_NUM);
}
else if (which == TRAX_ENA_PRO_APP_SWAP) {
} else if (which == TRAX_ENA_PRO_APP_SWAP) {
trace_ll_set_mem_block(1, TRACEMEM_MUX_BLK0_NUM);
trace_ll_set_mem_block(0, TRACEMEM_MUX_BLK1_NUM);
}

8
components/esp_system/port/cpu_start.c
View File

@ -193,7 +193,7 @@ void IRAM_ATTR call_start_cpu1(void)
// Configure the global pointer register
// (This should be the first thing IDF app does, as any other piece of code could be
// relaxed by the linker to access something relative to __global_pointer$)
__asm__ __volatile__ (
__asm__ __volatile__(
".option push\n"
".option norelax\n"
"la gp, __global_pointer$\n"
@ -305,7 +305,7 @@ static void start_other_core(void)
if (!REG_GET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN)) {
REG_SET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
}
if(REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)){
if (REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)) {
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
}
#endif
@ -387,7 +387,7 @@ void IRAM_ATTR call_start_cpu0(void)
// Configure the global pointer register
// (This should be the first thing IDF app does, as any other piece of code could be
// relaxed by the linker to access something relative to __global_pointer$)
__asm__ __volatile__ (
__asm__ __volatile__(
".option push\n"
".option norelax\n"
"la gp, __global_pointer$\n"
@ -692,7 +692,7 @@ void IRAM_ATTR call_start_cpu0(void)
esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
// In a single thread mode, the freertos is not started yet. So don't have to use a critical section.
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif
#endif

4
components/esp_system/port/esp_ipc_isr.c
View File

@ -34,7 +34,6 @@ static int32_t volatile s_count_of_nested_calls[portNUM_PROCESSORS] = { 0 };
static BaseType_t s_stored_interrupt_level;
static uint32_t volatile esp_ipc_isr_finish_cmd;
/**
* @brief Type of calling
*/
@ -48,7 +47,6 @@ typedef enum {
static void esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for);
/* Initializing IPC_ISR */
void esp_ipc_isr_init(void)
@ -63,7 +61,6 @@ void esp_ipc_isr_init(void)
/* End initializing IPC_ISR */
/* Public API functions */
void IRAM_ATTR esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg)
@ -175,7 +172,6 @@ void IRAM_ATTR esp_ipc_isr_stall_resume(void)
/* End public API functions */
/* Private functions*/
static void IRAM_ATTR esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for)

12
components/esp_system/port/esp_system_chip.c
View File

@ -67,19 +67,19 @@ void IRAM_ATTR esp_restart_noos_dig(void)
}
#endif
uint32_t esp_get_free_heap_size( void )
uint32_t esp_get_free_heap_size(void)
{
return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
return heap_caps_get_free_size(MALLOC_CAP_DEFAULT);
}
uint32_t esp_get_free_internal_heap_size( void )
uint32_t esp_get_free_internal_heap_size(void)
{
return heap_caps_get_free_size( MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL );
return heap_caps_get_free_size(MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
}
uint32_t esp_get_minimum_free_heap_size( void )
uint32_t esp_get_minimum_free_heap_size(void)
{
return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
return heap_caps_get_minimum_free_size(MALLOC_CAP_DEFAULT);
}
const char *esp_get_idf_version(void)

14
components/esp_system/port/esp_system_linux.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,19 +20,19 @@ void esp_restart_noos_dig(void)
abort();
}
uint32_t esp_get_free_heap_size( void )
uint32_t esp_get_free_heap_size(void)
{
return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
return heap_caps_get_free_size(MALLOC_CAP_DEFAULT);
}
uint32_t esp_get_free_internal_heap_size( void )
uint32_t esp_get_free_internal_heap_size(void)
{
return heap_caps_get_free_size( MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL );
return heap_caps_get_free_size(MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
}
uint32_t esp_get_minimum_free_heap_size( void )
uint32_t esp_get_minimum_free_heap_size(void)
{
return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
return heap_caps_get_minimum_free_size(MALLOC_CAP_DEFAULT);
}
const char *esp_get_idf_version(void)

1
components/esp_system/port/include/esp_clk_internal.h
View File

@ -27,7 +27,6 @@ extern "C" {
*/
void esp_clk_init(void);
/**
* @brief Disables clock of some peripherals
*

1
components/esp_system/port/include/private/esp_private/brownout.h
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __ESP_BROWNOUT_H
#define __ESP_BROWNOUT_H

3
components/esp_system/port/include/private/esp_private/cache_err_int.h
View File

@ -12,7 +12,6 @@
extern "C" {
#endif
/**
* @brief initialize cache invalid access interrupt
*
@ -24,7 +23,6 @@ extern "C" {
*/
void esp_cache_err_int_init(void);
/**
* @brief get the CPU which caused cache invalid access interrupt. Helper function in
* panic handling.
@ -35,7 +33,6 @@ void esp_cache_err_int_init(void);
*/
int esp_cache_err_get_cpuid(void);
/**
* @brief Returns a pointer to the cache error message
*

96
components/esp_system/port/include/private/esp_private/hw_stack_guard.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -37,26 +37,25 @@ uint32_t esp_hw_stack_guard_get_pc(void);
#define ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET (ASSIST_DEBUG_CORE_0_SP_MAX_REG - ASSIST_DEBUG_CORE_0_INTR_ENA_REG)
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 reg1
lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
sw a0, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
sw a1, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
sw a0, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
sw a1, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 reg1 reg2
lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
andi \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
andi \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_START_CPU0 reg1 reg2
lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
lui \reg1, ASSIST_DEBUG_CORE_0_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
.endm
#if SOC_CPU_CORES_NUM > 1
#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM (ASSIST_DEBUG_CORE_1_INTR_ENA_REG >> 12)
@ -64,61 +63,61 @@ uint32_t esp_hw_stack_guard_get_pc(void);
#define ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET (ASSIST_DEBUG_CORE_1_SP_MAX_REG - ASSIST_DEBUG_CORE_1_INTR_ENA_REG)
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 reg1
lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
sw a0, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
sw a1, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
sw a0, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
sw a1, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 reg1 reg2
lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
andi \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
andi \reg2, \reg2, ~ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_START_CPU1 reg1 reg2
lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
lui \reg1, ASSIST_DEBUG_CORE_1_INTR_ENA_REG_IMM
lw \reg2, 0(\reg1)
ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, 0(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE reg1
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, @1f
/* Core 1 */
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 \reg1
j 2f
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, @1f
/* Core 1 */
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 \reg1
j 2f
1:
/* Core 0 */
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 \reg1
/* Core 0 */
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 \reg1
2:
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE reg1 reg2
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, @1f
/* Core 1 */
ESP_HW_STACK_GUARD_MONITOR_START_CPU1 \reg1 \reg2
j 2f
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, @1f
/* Core 1 */
ESP_HW_STACK_GUARD_MONITOR_START_CPU1 \reg1 \reg2
j 2f
1:
/* Core 0 */
ESP_HW_STACK_GUARD_MONITOR_START_CPU0 \reg1 \reg2
/* Core 0 */
ESP_HW_STACK_GUARD_MONITOR_START_CPU0 \reg1 \reg2
2:
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE reg1 reg2
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, @1f
/* Core 1 */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 \reg1 \reg2
j 2f
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, @1f
/* Core 1 */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 \reg1 \reg2
j 2f
1:
/* Core 0 */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 \reg1 \reg2
/* Core 0 */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 \reg1 \reg2
2:
.endm
@ -130,5 +129,4 @@ uint32_t esp_hw_stack_guard_get_pc(void);
#endif // SOC_CPU_CORES_NUM > 1
#endif // __ASSEMBLER__

1
components/esp_system/port/include/private/esp_private/trax.h
View File

@ -53,7 +53,6 @@ int trax_enable(trax_ena_select_t ena);
*/
int trax_start_trace(trax_downcount_unit_t units_until_stop);
/**
* @brief Trigger a Trax trace stop after the indicated delay. If this is called
* before and the previous delay hasn't ended yet, this will overwrite

90
components/esp_system/port/include/riscv/libunwind-riscv.h
View File

@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,7 +16,6 @@
#include "esp_attr.h"
#include "riscv/rvruntime-frames.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -114,7 +113,8 @@ typedef enum {
/**
* @brief Get the current context
*/
FORCE_INLINE_ATTR void UNW_GET_CONTEXT(ExecutionFrame* frame) {
FORCE_INLINE_ATTR void UNW_GET_CONTEXT(ExecutionFrame* frame)
{
__asm__ __volatile__("sw t0, %1(%0)\n"
"auipc t0, 0\n"
"sw t0, %2(%0)\n"
@ -146,37 +146,37 @@ FORCE_INLINE_ATTR void UNW_GET_CONTEXT(ExecutionFrame* frame) {
"sw s11, %28(%0)\n"
"sw t3, %29(%0)\n"
:
: "r" (frame),
"i" (UNW_RISCV_T0 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_PC * ARCH_WORD_SIZE),
"i" (UNW_RISCV_RA * ARCH_WORD_SIZE),
"i" (UNW_RISCV_SP * ARCH_WORD_SIZE),
"i" (UNW_RISCV_GP * ARCH_WORD_SIZE),
"i" (UNW_RISCV_TP * ARCH_WORD_SIZE),
"i" (UNW_RISCV_T1 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_T2 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S0 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S1 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A0 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A1 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A2 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A3 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A4 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A5 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A6 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_A7 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S2 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S3 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S4 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S5 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S6 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S7 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S8 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S9 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S10 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_S11 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_T3 * ARCH_WORD_SIZE)
);
: "r"(frame),
"i"(UNW_RISCV_T0 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_PC * ARCH_WORD_SIZE),
"i"(UNW_RISCV_RA * ARCH_WORD_SIZE),
"i"(UNW_RISCV_SP * ARCH_WORD_SIZE),
"i"(UNW_RISCV_GP * ARCH_WORD_SIZE),
"i"(UNW_RISCV_TP * ARCH_WORD_SIZE),
"i"(UNW_RISCV_T1 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_T2 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S0 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S1 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A0 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A1 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A2 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A3 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A4 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A5 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A6 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_A7 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S2 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S3 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S4 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S5 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S6 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S7 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S8 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S9 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S10 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_S11 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_T3 * ARCH_WORD_SIZE)
);
/* GCC doesn't allow us to have more than 30 operands in a single
* __asm__ __volatile__ definition, so we have to split it into 2 */
__asm__ __volatile__("sw t4, %1(%0)\n"
@ -195,17 +195,17 @@ FORCE_INLINE_ATTR void UNW_GET_CONTEXT(ExecutionFrame* frame) {
/* We have to restore t0 as it may be in use by the function that makes the use of this assembly snippet */
"lw t0, %9(%0)\n"
:
: "r" (frame),
"i" (UNW_RISCV_T4 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_T5 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_T6 * ARCH_WORD_SIZE),
"i" (UNW_RISCV_MSTATUS * ARCH_WORD_SIZE),
"i" (UNW_RISCV_MTVEC * ARCH_WORD_SIZE),
"i" (UNW_RISCV_MCAUSE * ARCH_WORD_SIZE),
"i" (UNW_RISCV_MTVAL * ARCH_WORD_SIZE),
"i" (UNW_RISCV_MHARTID * ARCH_WORD_SIZE),
"i" (UNW_RISCV_T0 * ARCH_WORD_SIZE)
);
: "r"(frame),
"i"(UNW_RISCV_T4 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_T5 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_T6 * ARCH_WORD_SIZE),
"i"(UNW_RISCV_MSTATUS * ARCH_WORD_SIZE),
"i"(UNW_RISCV_MTVEC * ARCH_WORD_SIZE),
"i"(UNW_RISCV_MCAUSE * ARCH_WORD_SIZE),
"i"(UNW_RISCV_MTVAL * ARCH_WORD_SIZE),
"i"(UNW_RISCV_MHARTID * ARCH_WORD_SIZE),
"i"(UNW_RISCV_T0 * ARCH_WORD_SIZE)
);
}
#ifdef __cplusplus

3
components/esp_system/port/include/x86/libunwind-x86.h
View File

@ -33,8 +33,7 @@ extern "C" {
* @brief Definition of the x86 DWARF registers set.
* The following registers order has been taken from GCC's `i386.c` file:
*/
typedef struct x86ExcFrame
{
typedef struct x86ExcFrame {
union {
struct {
uint32_t eax;

50
components/esp_system/port/soc/esp32/cache_err_int.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -49,20 +49,20 @@ void esp_cache_err_int_init(void)
if (core_id == PRO_CPU_NUM) {
DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
DPORT_CACHE_IA_INT_PRO_OPPOSITE |
DPORT_CACHE_IA_INT_PRO_DRAM1 |
DPORT_CACHE_IA_INT_PRO_DROM0 |
DPORT_CACHE_IA_INT_PRO_IROM0 |
DPORT_CACHE_IA_INT_PRO_IRAM0 |
DPORT_CACHE_IA_INT_PRO_IRAM1);
DPORT_CACHE_IA_INT_PRO_OPPOSITE |
DPORT_CACHE_IA_INT_PRO_DRAM1 |
DPORT_CACHE_IA_INT_PRO_DROM0 |
DPORT_CACHE_IA_INT_PRO_IROM0 |
DPORT_CACHE_IA_INT_PRO_IRAM0 |
DPORT_CACHE_IA_INT_PRO_IRAM1);
} else {
DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
DPORT_CACHE_IA_INT_APP_OPPOSITE |
DPORT_CACHE_IA_INT_APP_DRAM1 |
DPORT_CACHE_IA_INT_APP_DROM0 |
DPORT_CACHE_IA_INT_APP_IROM0 |
DPORT_CACHE_IA_INT_APP_IRAM0 |
DPORT_CACHE_IA_INT_APP_IRAM1);
DPORT_CACHE_IA_INT_APP_OPPOSITE |
DPORT_CACHE_IA_INT_APP_DRAM1 |
DPORT_CACHE_IA_INT_APP_DROM0 |
DPORT_CACHE_IA_INT_APP_IROM0 |
DPORT_CACHE_IA_INT_APP_IRAM0 |
DPORT_CACHE_IA_INT_APP_IRAM1);
}
ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
}
@ -70,24 +70,24 @@ void esp_cache_err_int_init(void)
int esp_cache_err_get_cpuid(void)
{
const uint32_t pro_mask =
DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 |
DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE;
DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 |
DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE;
if (DPORT_GET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG3_REG, pro_mask)) {
return PRO_CPU_NUM;
}
const uint32_t app_mask =
DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 |
DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 |
DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 |
DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 |
DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE;
DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 |
DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 |
DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 |
DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 |
DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE;
if (DPORT_GET_PERI_REG_MASK(DPORT_APP_DCACHE_DBUG3_REG, app_mask)) {
return APP_CPU_NUM;

47
components/esp_system/port/soc/esp32/clk.c
View File

@ -99,14 +99,14 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
esp_clk_slowclk_cal_set(cal_val);
}
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
rtc_init(cfg);
@ -184,7 +184,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
/* This function is not exposed as an API at this point.
@ -215,34 +215,33 @@ __attribute__((weak)) void esp_perip_clk_init(void)
*/
if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT)
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|| (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
|| (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
#endif
) {
) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
}
else {
} else {
common_perip_clk = DPORT_WDG_CLK_EN |
DPORT_PCNT_CLK_EN |
DPORT_LEDC_CLK_EN |
DPORT_TIMERGROUP1_CLK_EN |
DPORT_PWM0_CLK_EN |
DPORT_TWAI_CLK_EN |
DPORT_PWM1_CLK_EN |
DPORT_PWM2_CLK_EN |
DPORT_PWM3_CLK_EN;
DPORT_PCNT_CLK_EN |
DPORT_LEDC_CLK_EN |
DPORT_TIMERGROUP1_CLK_EN |
DPORT_PWM0_CLK_EN |
DPORT_TWAI_CLK_EN |
DPORT_PWM1_CLK_EN |
DPORT_PWM2_CLK_EN |
DPORT_PWM3_CLK_EN;
hwcrypto_perip_clk = DPORT_PERI_EN_AES |
DPORT_PERI_EN_SHA |
DPORT_PERI_EN_RSA |
DPORT_PERI_EN_SECUREBOOT;
DPORT_PERI_EN_SHA |
DPORT_PERI_EN_RSA |
DPORT_PERI_EN_SECUREBOOT;
wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
DPORT_WIFI_CLK_BT_EN_M |
DPORT_WIFI_CLK_UNUSED_BIT5 |
DPORT_WIFI_CLK_UNUSED_BIT12 |
DPORT_WIFI_CLK_SDIOSLAVE_EN |
DPORT_WIFI_CLK_SDIO_HOST_EN |
DPORT_WIFI_CLK_EMAC_EN;
DPORT_WIFI_CLK_BT_EN_M |
DPORT_WIFI_CLK_UNUSED_BIT5 |
DPORT_WIFI_CLK_UNUSED_BIT12 |
DPORT_WIFI_CLK_SDIOSLAVE_EN |
DPORT_WIFI_CLK_SDIO_HOST_EN |
DPORT_WIFI_CLK_EMAC_EN;
}
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.

7
components/esp_system/port/soc/esp32c2/cache_err_int.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,7 +20,6 @@
static const char *TAG = "CACHE_ERR";
#define DIM(array) (sizeof(array)/sizeof(*array))
/**
@ -90,8 +89,8 @@ const register_bit_t cache_ilg_bits[] = {
* be set in the register will have its associated message printed.
*/
static inline const char* test_and_print_register_bits(const uint32_t status,
const register_bit_t *reg_bits,
const uint32_t size)
const register_bit_t *reg_bits,
const uint32_t size)
{
/* Browse the flag/bit array and test each one with the given status
* register. */

9
components/esp_system/port/soc/esp32c2/clk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -54,8 +54,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
#if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
@ -124,7 +123,7 @@ static const char *TAG = "clk";
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
@ -170,7 +169,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);

4
components/esp_system/port/soc/esp32c3/cache_err_int.c
View File

@ -89,8 +89,8 @@ const register_bit_t cache_ilg_bits[] = {
* be set in the register will have its associated message printed.
*/
static inline const char* test_and_print_register_bits(const uint32_t status,
const register_bit_t *reg_bits,
const uint32_t size)
const register_bit_t *reg_bits,
const uint32_t size)
{
/* Browse the flag/bit array and test each one with the given status
* register. */

13
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -55,8 +55,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
#if !CONFIG_IDF_ENV_FPGA
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
@ -64,9 +63,9 @@ static const char *TAG = "clk";
rst_reas = esp_rom_get_reset_reason(0);
if (rst_reas == RESET_REASON_CHIP_POWER_ON
#if SOC_EFUSE_HAS_EFUSE_RST_BUG
|| rst_reas == RESET_REASON_CORE_EFUSE_CRC
|| rst_reas == RESET_REASON_CORE_EFUSE_CRC
#endif
) {
) {
cfg.cali_ocode = 1;
}
rtc_init(cfg);
@ -129,7 +128,7 @@ static const char *TAG = "clk";
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
@ -179,7 +178,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);

8
components/esp_system/port/soc/esp32c3/reset_reason.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,9 +26,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;

16
components/esp_system/port/soc/esp32c5/clk.c
View File

@ -41,7 +41,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
static const char *TAG = "clk";
// TODO: [ESP32C5] IDF-8642
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
#if SOC_PMU_SUPPORTED
pmu_init();
@ -105,7 +105,7 @@ static const char *TAG = "clk";
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
@ -162,7 +162,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
@ -191,11 +191,11 @@ __attribute__((weak)) void esp_perip_clk_init(void)
* scenarios), the module needs to switch to the required clock source by
* itself. */ //TODO - WIFI-5233
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t) ( \
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
: MODEM_CLOCK_LPCLK_SRC_RC32K);
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(\
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
: MODEM_CLOCK_LPCLK_SRC_RC32K);
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
#endif

6
components/esp_system/port/soc/esp32c5/reset_reason.c
View File

@ -25,9 +25,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;

1
components/esp_system/port/soc/esp32c6/cache_err_int.c
View File

@ -20,7 +20,6 @@
static const char *TAG = "CACHE_ERR";
const char cache_error_msg[] = "Cache access error";
const char *esp_cache_err_panic_string(void)

21
components/esp_system/port/soc/esp32c6/clk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -40,8 +40,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
#if !CONFIG_IDF_ENV_FPGA
pmu_init();
@ -106,7 +105,7 @@ static const char *TAG = "clk";
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
@ -158,7 +157,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
@ -186,12 +185,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
* scenarios), the module needs to switch to the required clock source by
* itself. */ //TODO - WIFI-5233
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t) ( \
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(\
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");

8
components/esp_system/port/soc/esp32c6/reset_reason.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,9 +23,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;

17
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -40,8 +40,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
#if !CONFIG_IDF_ENV_FPGA
pmu_init();
@ -105,7 +104,7 @@ static const char *TAG = "clk";
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
// Set crypto clock (`clk_sec`) to use 96M PLL clock
REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
@ -160,7 +159,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
@ -181,10 +180,10 @@ void rtc_clk_select_rtc_slow_clk(void)
__attribute__((weak)) void esp_perip_clk_init(void)
{
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) (\
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
: ESP_PD_DOMAIN_MAX);
esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t)(\
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
: ESP_PD_DOMAIN_MAX);
esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");

8
components/esp_system/port/soc/esp32h2/reset_reason.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,9 +23,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;

9
components/esp_system/port/soc/esp32p4/clk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -39,8 +39,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
static const char *TAG = "clk";
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
#if SOC_PMU_SUPPORTED
pmu_init();
@ -100,7 +99,7 @@ static const char *TAG = "clk";
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
@ -149,7 +148,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);

10
components/esp_system/port/soc/esp32p4/reset_reason.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,16 +23,16 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;
case RESET_REASON_SYS_PMU_PWR_DOWN:
case RESET_REASON_CPU_PMU_PWR_DOWN:
/* Check when doing sleep bringup TODO IDF-7529 */
/* Check when doing sleep bringup TODO IDF-7529 */
return ESP_RST_DEEPSLEEP;
case RESET_REASON_SYS_HP_WDT:

4
components/esp_system/port/soc/esp32s2/cache_err_int.c
View File

@ -70,8 +70,8 @@ void esp_cache_err_int_init(void)
int esp_cache_err_get_cpuid(void)
{
if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 ||
REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) {
return PRO_CPU_NUM;
REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) {
return PRO_CPU_NUM;
}
return -1;
}

7
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -60,7 +60,7 @@ typedef enum {
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
@ -132,7 +132,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
@ -185,7 +185,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
@ -309,7 +309,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
}

8
components/esp_system/port/soc/esp32s2/reset_reason.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,9 +23,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;

12
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -54,7 +54,7 @@ typedef enum {
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
__attribute__((weak)) void esp_clk_init(void)
__attribute__((weak)) void esp_clk_init(void)
{
rtc_config_t cfg = RTC_CONFIG_DEFAULT();
soc_reset_reason_t rst_reas;
@ -124,7 +124,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
}
// Re calculate the ccount to make time calculation correct.
esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz );
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
}
static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
@ -174,7 +174,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
} else {
const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
}
} while (cal_val == 0);
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
@ -214,8 +214,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW ||
rst_reas[0] == RESET_REASON_CPU0_RTC_WDT || rst_reas[0] == RESET_REASON_CPU0_MWDT1)
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|| (rst_reas[1] == RESET_REASON_CPU1_MWDT0 || rst_reas[1] == RESET_REASON_CPU1_SW ||
rst_reas[1] == RESET_REASON_CPU1_RTC_WDT || rst_reas[1] == RESET_REASON_CPU1_MWDT1)
|| (rst_reas[1] == RESET_REASON_CPU1_MWDT0 || rst_reas[1] == RESET_REASON_CPU1_SW ||
rst_reas[1] == RESET_REASON_CPU1_RTC_WDT || rst_reas[1] == RESET_REASON_CPU1_MWDT1)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);

8
components/esp_system/port/soc/esp32s3/reset_reason.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,9 +23,9 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
case RESET_REASON_CPU0_SW:
case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT ||
reset_reason_hint == ESP_RST_INT_WDT) {
return reset_reason_hint;
}
return ESP_RST_SW;

1
components/esp_system/port/soc/esp32s3/system_internal.c
View File

@ -80,7 +80,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
wdt_hal_write_protect_disable(&wdt0_context);

8
components/esp_system/port/usb_console.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -55,7 +55,6 @@ typedef enum {
REBOOT_BOOTLOADER_DFU,
} reboot_type_t;
static reboot_type_t s_queue_reboot = REBOOT_NONE;
static int s_prev_rts_state;
static intr_handle_t s_usb_int_handle;
@ -87,12 +86,10 @@ void esp_usb_console_write_char(char c);
#define ISR_FLAG 0
#endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Optional write lock routines; used only if esp_rom_printf output via CDC is enabled */
static inline void write_lock_acquire(void);
static inline void write_lock_release(void);
/* Other forward declarations */
void esp_usb_console_before_restart(void);
@ -273,7 +270,7 @@ esp_err_t esp_usb_console_init(void)
* It is not because we actually need the interrupt to work with cache disabled!
*/
err = esp_intr_alloc(ETS_USB_INTR_SOURCE, ISR_FLAG | ESP_INTR_FLAG_INTRDISABLED,
esp_usb_console_interrupt, NULL, &s_usb_int_handle);
esp_usb_console_interrupt, NULL, &s_usb_int_handle);
if (err != ESP_OK) {
esp_unregister_shutdown_handler(esp_usb_console_before_restart);
return err;
@ -441,7 +438,6 @@ bool esp_usb_console_write_available(void)
return cdc_acm_irq_tx_ready(s_cdc_acm_device) != 0;
}
#ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Used as an output function by esp_rom_printf.
* The LF->CRLF replacement logic replicates the one in esp_rom_uart_putc.

8
components/esp_system/stack_check.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,14 +16,14 @@ const static char *TAG = "stack_chk";
void *__stack_chk_guard = NULL;
static void __attribute__ ((constructor))
__esp_stack_guard_setup (void)
static void __attribute__((constructor))
__esp_stack_guard_setup(void)
{
ESP_LOGD(TAG, "Intialize random stack guard");
__stack_chk_guard = (void *)esp_random();
}
IRAM_ATTR void __stack_chk_fail (void)
IRAM_ATTR void __stack_chk_fail(void)
{
esp_system_abort(DRAM_STR("Stack smashing protect failure!"));
}

17
components/esp_system/startup.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,7 +23,7 @@
// Ensure that system configuration matches the underlying number of cores.
// This should enable us to avoid checking for both everytime.
#if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
#error "System has been configured to run on multiple cores, but target SoC only has a single core."
#error "System has been configured to run on multiple cores, but target SoC only has a single core."
#endif
uint64_t g_startup_time = 0;
@ -45,9 +45,9 @@ static volatile bool s_system_inited[SOC_CPU_CORES_NUM] = { false };
const sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM] = { [0] = start_cpu0,
#if SOC_CPU_CORES_NUM > 1
[1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
[1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
#endif
};
};
static volatile bool s_system_full_inited = false;
#else
@ -56,7 +56,6 @@ const sys_startup_fn_t g_startup_fn[1] = { start_cpu0 };
static const char* TAG = "cpu_start";
/**
* Xtensa gcc is configured to emit a .ctors section, RISC-V gcc is configured with --enable-initfini-array
* so it emits an .init_array section instead.
@ -78,12 +77,14 @@ static void do_global_ctors(void)
extern void (*__init_array_end)(void);
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
struct object { long placeholder[ 10 ]; };
void __register_frame_info (const void *begin, struct object *ob);
struct object {
long placeholder[ 10 ];
};
void __register_frame_info(const void *begin, struct object * ob);
extern char __eh_frame[];
static struct object ob;
__register_frame_info( __eh_frame, &ob );
__register_frame_info(__eh_frame, &ob);
#endif // CONFIG_COMPILER_CXX_EXCEPTIONS
void (**p)(void);

2
components/esp_system/startup_funcs.c
View File

@ -248,7 +248,7 @@ ESP_SYSTEM_INIT_FN(init_secure, CORE, BIT(0), 150)
#ifdef ROM_LOG_MODE
ESP_SYSTEM_INIT_FN(init_rom_log, CORE, BIT(0), 160)
{
if(ets_efuse_get_uart_print_control() == ROM_LOG_MODE) {
if (ets_efuse_get_uart_print_control() == ROM_LOG_MODE) {
return ESP_OK;
}

38
components/esp_system/task_wdt/task_wdt.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,17 +25,14 @@
#include "esp_private/esp_task_wdt.h"
#include "esp_private/esp_task_wdt_impl.h"
#if CONFIG_IDF_TARGET_ARCH_RISCV
#include "riscv/rvruntime-frames.h"
#endif //CONFIG_IDF_TARGET_ARCH_RISCV
#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
#include "esp_private/eh_frame_parser.h"
#endif // CONFIG_ESP_SYSTEM_USE_EH_FRAME
#if CONFIG_IDF_TARGET_ARCH_RISCV && !CONFIG_ESP_SYSTEM_USE_EH_FRAME
/* Function used to print all the registers pointed by the given frame .*/
extern void panic_print_registers(const void *frame, int core);
@ -291,7 +288,6 @@ static void unsubscribe_idle(uint32_t core_mask)
}
}
/**
* @brief Subscribes the idle tasks of one or more cores
*
@ -318,7 +314,6 @@ static void subscribe_idle(uint32_t core_mask)
}
}
/**
* The behavior of the Task Watchdog depends on the configuration from the `menuconfig`.
* It can be summarized as follow, regardless of the target:
@ -341,8 +336,8 @@ static void subscribe_idle(uint32_t core_mask)
static UBaseType_t get_task_affinity(const TaskHandle_t xTask)
{
if (xTask == NULL) {
/* User entry, we cannot predict on which core it is scheduled to run,
* so let's mark all cores as failing */
/* User entry, we cannot predict on which core it is scheduled to run,
* so let's mark all cores as failing */
#if configNUM_CORES > 1
return BIT(1) | BIT(0);
#else
@ -351,16 +346,16 @@ static UBaseType_t get_task_affinity(const TaskHandle_t xTask)
}
#if CONFIG_FREERTOS_SMP
#if configNUM_CORES > 1
return vTaskCoreAffinityGet(xTask);
#else
return BIT(0);
#endif
#if configNUM_CORES > 1
return vTaskCoreAffinityGet(xTask);
#else
BaseType_t task_affinity = xTaskGetCoreID(xTask);
if (task_affinity == 0 || task_affinity == 1) {
return BIT(task_affinity);
}
return BIT(0);
#endif
#else
BaseType_t task_affinity = xTaskGetCoreID(xTask);
if (task_affinity == 0 || task_affinity == 1) {
return BIT(task_affinity);
}
return BIT(1) | BIT(0);
#endif
}
@ -406,8 +401,6 @@ void task_wdt_timeout_abort(bool current_core)
xt_unhandled_exception(frame);
}
static void task_wdt_timeout_handling(int cores_fail, bool panic)
{
const int current_core = xPortGetCoreID();
@ -450,7 +443,6 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic)
}
}
// ---------------------- Callbacks ------------------------
/**
@ -488,11 +480,11 @@ static void task_wdt_isr(void *arg)
int cpus_fail = 0;
bool panic = p_twdt_obj->panic;
if (esp_task_wdt_print_triggered_tasks(NULL, NULL, &cpus_fail) != ESP_OK) {
if (esp_task_wdt_print_triggered_tasks(NULL, NULL, &cpus_fail) != ESP_OK) {
// If there are no entries, there's nothing to do.
portEXIT_CRITICAL_ISR(&spinlock);
return;
}
}
ESP_EARLY_LOGE(TAG, "%s", DRAM_STR("Tasks currently running:"));
for (int x = 0; x < portNUM_PROCESSORS; x++) {
@ -794,7 +786,7 @@ esp_err_t esp_task_wdt_print_triggered_tasks(task_wdt_msg_handler msg_handler, v
twdt_entry_t *entry;
const char *caption = "Task watchdog got triggered. "
"The following tasks/users did not reset the watchdog in time:";
"The following tasks/users did not reset the watchdog in time:";
if (msg_handler == NULL) {
ESP_EARLY_LOGE(TAG, "%s", caption);

8
components/esp_system/task_wdt/task_wdt_impl_esp_timer.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,7 +33,6 @@ static twdt_ctx_soft_t init_context;
static const char *TAG = "task_wdt_impl_soft";
esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
twdt_isr_callback callback,
twdt_ctx_t *obj)
@ -81,7 +80,6 @@ esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt
return ret;
}
void esp_task_wdt_impl_timer_free(twdt_ctx_t obj)
{
const twdt_ctx_soft_t* ctx = (twdt_ctx_soft_t*) obj;
@ -91,7 +89,6 @@ void esp_task_wdt_impl_timer_free(twdt_ctx_t obj)
}
}
esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj)
{
esp_err_t ret = ESP_OK;
@ -109,13 +106,11 @@ esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj)
return ret;
}
void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj)
{
(void) obj;
}
esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj)
{
esp_err_t ret = ESP_OK;
@ -132,7 +127,6 @@ esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj)
return ret;
}
esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj)
{
esp_err_t ret = ESP_OK;

10
components/esp_system/task_wdt/task_wdt_impl_timergroup.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -39,8 +39,6 @@ typedef struct {
* init function. */
static twdt_ctx_hard_t init_context;
esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
twdt_isr_callback callback,
twdt_ctx_t *obj)
@ -81,7 +79,6 @@ esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
return ret;
}
esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt_config_t *config)
{
esp_err_t ret = ESP_OK;
@ -103,7 +100,6 @@ esp_err_t esp_task_wdt_impl_timer_reconfigure(twdt_ctx_t obj, const esp_task_wdt
return ret;
}
void esp_task_wdt_impl_timer_free(twdt_ctx_t obj)
{
twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
@ -125,7 +121,6 @@ void esp_task_wdt_impl_timer_free(twdt_ctx_t obj)
}
}
esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj)
{
esp_err_t ret = ESP_OK;
@ -144,7 +139,6 @@ esp_err_t esp_task_wdt_impl_timer_feed(twdt_ctx_t obj)
return ret;
}
void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj)
{
twdt_ctx_hard_t* ctx = (twdt_ctx_hard_t*) obj;
@ -157,7 +151,6 @@ void esp_task_wdt_impl_timeout_triggered(twdt_ctx_t obj)
}
}
esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj)
{
esp_err_t ret = ESP_OK;
@ -176,7 +169,6 @@ esp_err_t esp_task_wdt_impl_timer_stop(twdt_ctx_t obj)
return ret;
}
esp_err_t esp_task_wdt_impl_timer_restart(twdt_ctx_t obj)
{
esp_err_t ret = ESP_OK;

11
components/esp_system/test_apps/esp_system_unity_tests/main/port/arch/riscv/test_ipc_isr.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,18 +9,21 @@
#if CONFIG_ESP_IPC_ISR_ENABLE
void esp_test_ipc_isr_callback(void *arg) {
void esp_test_ipc_isr_callback(void *arg)
{
uint32_t value = 0xa5a5;
*(volatile uint32_t*)arg = value;
}
void esp_test_ipc_isr_get_other_core_id(void *arg) {
void esp_test_ipc_isr_get_other_core_id(void *arg)
{
uint32_t core_id;
__asm volatile("csrr %0, mhartid" : "=r"(core_id));
*(volatile uint32_t*)arg = core_id;
}
void esp_test_ipc_isr_get_cycle_count_other_cpu(void *arg) {
void esp_test_ipc_isr_get_cycle_count_other_cpu(void *arg)
{
uint32_t cycle_count;
__asm volatile("rdcycle %0;" : "=r"(cycle_count));
*(volatile uint32_t*)arg = cycle_count;

21
components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -30,7 +30,6 @@
#define ACTION_INT_WDT -2
#define TASK_PRIORITY 5
// Set to (-1) for abort(), (-2) for interrupt watchdog
static int backtrace_trigger_source;
@ -55,7 +54,7 @@ static void __attribute__((__noinline__)) recursive_func(int recur_depth, int ac
}
}
static void level_three_isr (void *arg)
static void level_three_isr(void *arg)
{
xt_set_intclear(1 << SW_ISR_LEVEL_3); //Clear interrupt
recursive_func(RECUR_DEPTH, backtrace_trigger_source); //Abort at the max recursive depth
@ -82,9 +81,8 @@ static void check_reset_reason_panic(void)
}
TEST_CASE_MULTIPLE_STAGES("Test backtrace from abort", "[reset_reason][reset=abort,SW_CPU_RESET]",
do_abort,
check_reset_reason_panic)
do_abort,
check_reset_reason_panic)
static void do_wdt_timeout(void)
{
@ -101,9 +99,8 @@ static void check_reset_reason_int_wdt(void)
}
TEST_CASE_MULTIPLE_STAGES("Test backtrace from interrupt watchdog timeout", "[reset_reason][reset=Interrupt wdt timeout on CPU0,SW_CPU_RESET]",
do_wdt_timeout,
check_reset_reason_int_wdt)
do_wdt_timeout,
check_reset_reason_int_wdt)
static void write_char_crash(char c)
{
@ -117,11 +114,9 @@ static void do_rom_crash(void)
esp_rom_printf("foo");
}
TEST_CASE_MULTIPLE_STAGES("Test backtrace with a ROM function", "[reset_reason][reset=StoreProhibited,SW_CPU_RESET]",
do_rom_crash,
check_reset_reason_panic)
do_rom_crash,
check_reset_reason_panic)
#define NUM_TEST_FUNCS 2

7
components/esp_system/test_apps/esp_system_unity_tests/main/test_ipc_isr.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -18,9 +18,9 @@
#ifdef CONFIG_ESP_IPC_ISR_ENABLE
#if CONFIG_IDF_TARGET_ARCH_RISCV
#define STORE_ERROR "Store access fault"
#define STORE_ERROR "Store access fault"
#else
#define STORE_ERROR "StoreProhibited"
#define STORE_ERROR "StoreProhibited"
#endif
void esp_test_ipc_isr_callback(void* arg);
@ -34,7 +34,6 @@ TEST_CASE("Test ipc_isr blocking IPC function calls a ASM function", "[ipc]")
void esp_test_ipc_isr_get_other_core_id(void* arg);
TEST_CASE("Test ipc_isr blocking IPC function calls get_other_core_id", "[ipc]")
{
int val = 0x5a5a;

79
components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
View File

@ -97,7 +97,6 @@
#endif // CONFIG_IDF_TARGET_ESP32
/* This test needs special test runners: rev1 silicon, and SPI flash with
* fast start-up time. Otherwise reset reason will be RTCWDT_RESET.
*/
@ -106,7 +105,6 @@ TEST_CASE("reset reason ESP_RST_POWERON", "[reset][ignore]")
TEST_ASSERT_EQUAL(ESP_RST_POWERON, esp_reset_reason());
}
static __NOINIT_ATTR uint32_t s_noinit_val;
#if CHECK_RTC_MEM
@ -130,7 +128,7 @@ static void setup_values(void)
s_rtc_data_val = CHECK_VALUE;
s_rtc_bss_val = CHECK_VALUE;
TEST_ASSERT_EQUAL_HEX32_MESSAGE(CHECK_VALUE, s_rtc_rodata_val,
"s_rtc_rodata_val should already be set up");
"s_rtc_rodata_val should already be set up");
s_rtc_force_fast_val = CHECK_VALUE;
s_rtc_force_slow_val = CHECK_VALUE;
#endif //CHECK_RTC_MEM
@ -167,15 +165,15 @@ static void check_reset_reason_deep_sleep(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][reset="DEEPSLEEP"]",
do_deep_sleep,
check_reset_reason_deep_sleep);
do_deep_sleep,
check_reset_reason_deep_sleep);
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
static void do_exception(void)
{
setup_values();
*(int*) (0x0) = 0;
*(int*)(0x0) = 0;
}
static void do_abort(void)
@ -200,12 +198,12 @@ static void check_reset_reason_panic(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after exception", "[reset_reason][reset="LOAD_STORE_ERROR","RESET"]",
do_exception,
check_reset_reason_panic);
do_exception,
check_reset_reason_panic);
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after abort", "[reset_reason][reset=abort,"RESET"]",
do_abort,
check_reset_reason_panic);
do_abort,
check_reset_reason_panic);
static void do_restart(void)
{
@ -238,16 +236,15 @@ static void check_reset_reason_sw(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart", "[reset_reason][reset="RESET"]",
do_restart,
check_reset_reason_sw);
do_restart,
check_reset_reason_sw);
#if portNUM_PROCESSORS > 1
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart from APP CPU", "[reset_reason][reset="RESET"]",
do_restart_from_app_cpu,
check_reset_reason_sw);
do_restart_from_app_cpu,
check_reset_reason_sw);
#endif
static void do_int_wdt(void)
{
setup_values();
@ -257,10 +254,9 @@ static void do_int_wdt(void)
BaseType_t prev_level = portSET_INTERRUPT_MASK_FROM_ISR();
#endif
(void) prev_level;
while(1);
while (1);
}
static void do_int_wdt_hw(void)
{
setup_values();
@ -269,7 +265,7 @@ static void do_int_wdt_hw(void)
#else
XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);
#endif
while(1) { }
while (1) { }
}
static void check_reset_reason_int_wdt_sw(void)
@ -289,14 +285,14 @@ static void check_reset_reason_int_wdt_hw(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (panic)",
"[reset_reason][reset="INT_WDT_PANIC","RESET"]",
do_int_wdt,
check_reset_reason_int_wdt_sw);
"[reset_reason][reset="INT_WDT_PANIC","RESET"]",
do_int_wdt,
check_reset_reason_int_wdt_sw);
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (hw)",
"[reset_reason][reset="INT_WDT"]",
do_int_wdt_hw,
check_reset_reason_int_wdt_hw);
"[reset_reason][reset="INT_WDT"]",
do_int_wdt_hw,
check_reset_reason_int_wdt_hw);
#if CONFIG_ESP_TASK_WDT_EN
static void do_task_wdt(void)
@ -308,7 +304,7 @@ static void do_task_wdt(void)
.trigger_panic = true,
};
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_init(&twdt_config));
while(1);
while (1);
}
static void check_reset_reason_task_wdt(void)
@ -327,9 +323,9 @@ static void check_reset_reason_task_wdt(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_TASK_WDT after task watchdog",
"[reset_reason][reset="RESET"]",
do_task_wdt,
check_reset_reason_task_wdt);
"[reset_reason][reset="RESET"]",
do_task_wdt,
check_reset_reason_task_wdt);
#endif // CONFIG_ESP_TASK_WDT_EN
static void do_rtc_wdt(void)
@ -343,7 +339,7 @@ static void do_rtc_wdt(void)
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
while(1);
while (1);
}
static void check_reset_reason_any_wdt(void)
@ -355,10 +351,9 @@ static void check_reset_reason_any_wdt(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_WDT after RTC watchdog",
"[reset_reason][reset="RTC_WDT"]",
do_rtc_wdt,
check_reset_reason_any_wdt);
"[reset_reason][reset="RTC_WDT"]",
do_rtc_wdt,
check_reset_reason_any_wdt);
static void do_brownout(void)
{
@ -383,10 +378,9 @@ static void check_reset_reason_brownout(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event",
"[reset_reason][ignore][reset="BROWNOUT"]",
do_brownout,
check_reset_reason_brownout);
"[reset_reason][ignore][reset="BROWNOUT"]",
do_brownout,
check_reset_reason_brownout);
#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
#ifndef CONFIG_FREERTOS_UNICORE
@ -406,7 +400,7 @@ static int fibonacci(int n, void* func(void))
printf("WINDOWBASE = %-2"PRIi32" WINDOWSTART = 0x%"PRIx32"\n", base, start);
if (n <= 1) {
StackType_t *last_addr_stack = esp_cpu_get_sp();
StackType_t *used_stack = (StackType_t *) (start_addr_stack - last_addr_stack);
StackType_t *used_stack = (StackType_t *)(start_addr_stack - last_addr_stack);
printf("addr_stack = %p, used[%p]/all[0x%x] space in stack\n", last_addr_stack, used_stack, size_stack);
func();
return n;
@ -463,16 +457,15 @@ static void test2_finish(void)
}
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart in a task with spiram stack", "[spiram_stack][reset="RESET"]",
init_restart_task,
test1_finish);
init_restart_task,
test1_finish);
TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a task with spiram stack", "[spiram_stack][reset="STORE_ERROR","RESET"]",
init_task_do_exception,
test2_finish);
init_task_do_exception,
test2_finish);
#endif //CONFIG_IDF_TARGET_ARCH_XTENSA
#endif // CONFIG_FREERTOS_UNICORE
#endif // CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
/* Not tested here: ESP_RST_SDIO */

23
components/esp_system/test_apps/esp_system_unity_tests/main/test_shared_stack_printf.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -14,8 +14,8 @@
#include "esp_expression_with_stack.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-8832: RISC-V FPU does not work on shared stack,
// esp_execute_shared_stack_function might be deprecated because of
// the FPU issue and all the other issues with it.
// esp_execute_shared_stack_function might be deprecated because of
// the FPU issue and all the other issues with it.
#define SHARED_STACK_SIZE 8192
@ -56,22 +56,21 @@ TEST_CASE("test printf using shared buffer stack", "[shared_stack]")
printf("shared_stack: %p\n", (void *)shared_stack);
printf("shared_stack expected top: %p\n", (void *)(shared_stack + SHARED_STACK_SIZE));
esp_execute_shared_stack_function(printf_lock,
shared_stack,
SHARED_STACK_SIZE,
external_stack_function);
shared_stack,
SHARED_STACK_SIZE,
external_stack_function);
TEST_ASSERT(((shared_stack_sp >= shared_stack) &&
(shared_stack_sp < (shared_stack + SHARED_STACK_SIZE))));
(shared_stack_sp < (shared_stack + SHARED_STACK_SIZE))));
esp_execute_shared_stack_function(printf_lock,
shared_stack,
SHARED_STACK_SIZE,
another_external_stack_function);
shared_stack,
SHARED_STACK_SIZE,
another_external_stack_function);
TEST_ASSERT(((shared_stack_sp >= shared_stack) &&
(shared_stack_sp < (shared_stack + SHARED_STACK_SIZE))));
(shared_stack_sp < (shared_stack + SHARED_STACK_SIZE))));
vSemaphoreDelete(printf_lock);
free(shared_stack);

65
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
View File

@ -43,7 +43,6 @@
#define ESP_EXT0_WAKEUP_LEVEL_HIGH 1
__attribute__((unused)) static struct timeval tv_start, tv_stop;
static void check_sleep_reset(void)
{
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
@ -90,7 +89,6 @@ TEST_CASE_MULTIPLE_STAGES("wake up from deep sleep using timer", "[deepsleep][re
do_deep_sleep_timer,
check_sleep_reset)
static void do_light_sleep_deep_sleep_timer(void)
{
esp_sleep_enable_timer_wakeup(1000000);
@ -155,7 +153,7 @@ TEST_CASE("light sleep stress test with periodic esp_timer", "[deepsleep]")
esp_sleep_enable_timer_wakeup(1000);
esp_timer_handle_t timer;
esp_timer_create_args_t config = {
.callback = &timer_func,
.callback = &timer_func,
};
TEST_ESP_OK(esp_timer_create(&config, &timer));
esp_timer_start_periodic(timer, 500);
@ -179,7 +177,6 @@ TEST_CASE("light sleep stress test with periodic esp_timer", "[deepsleep]")
#define MAX_SLEEP_TIME_ERROR_US 100
#endif
TEST_CASE("light sleep duration is correct", "[deepsleep][ignore]")
{
// don't power down XTAL — powering it up takes different time on
@ -191,11 +188,11 @@ TEST_CASE("light sleep duration is correct", "[deepsleep][ignore]")
esp_light_sleep_start();
const int sleep_intervals_ms[] = {
1, 1, 2, 3, 4, 5, 6, 7, 8, 10, 15,
20, 25, 50, 100, 200, 500,
1, 1, 2, 3, 4, 5, 6, 7, 8, 10, 15,
20, 25, 50, 100, 200, 500,
};
const int sleep_intervals_count = sizeof(sleep_intervals_ms)/sizeof(sleep_intervals_ms[0]);
const int sleep_intervals_count = sizeof(sleep_intervals_ms) / sizeof(sleep_intervals_ms[0]);
for (int i = 0; i < sleep_intervals_count; ++i) {
uint64_t sleep_time = sleep_intervals_ms[i] * 1000;
esp_sleep_enable_timer_wakeup(sleep_time);
@ -206,20 +203,19 @@ TEST_CASE("light sleep duration is correct", "[deepsleep][ignore]")
int64_t stop_hs = esp_timer_get_time();
uint64_t stop = esp_clk_rtc_time();
int diff_us = (int) (stop - start);
int diff_hs_us = (int) (stop_hs - start_hs);
printf("%lld %d\n", sleep_time, (int) (diff_us - sleep_time));
int diff_us = (int)(stop - start);
int diff_hs_us = (int)(stop_hs - start_hs);
printf("%lld %d\n", sleep_time, (int)(diff_us - sleep_time));
int32_t threshold = MAX(sleep_time / 100, MAX_SLEEP_TIME_ERROR_US);
TEST_ASSERT_INT32_WITHIN(threshold, sleep_time, diff_us);
TEST_ASSERT_INT32_WITHIN(threshold, sleep_time, diff_hs_us);
fflush(stdout);
}
vTaskDelay(10/portTICK_PERIOD_MS);
vTaskDelay(10 / portTICK_PERIOD_MS);
}
}
TEST_CASE("light sleep and frequency switching", "[deepsleep]")
{
#ifndef CONFIG_PM_ENABLE
@ -270,10 +266,10 @@ static void check_sleep_reset_and_sleep(void)
}
TEST_CASE_MULTIPLE_STAGES("enter deep sleep more than once", "[deepsleep][reset=DEEPSLEEP_RESET,DEEPSLEEP_RESET,DEEPSLEEP_RESET]",
do_deep_sleep,
check_sleep_reset_and_sleep,
check_sleep_reset_and_sleep,
check_sleep_reset);
do_deep_sleep,
check_sleep_reset_and_sleep,
check_sleep_reset_and_sleep,
check_sleep_reset);
static void do_abort(void)
{
@ -288,9 +284,9 @@ static void check_abort_reset_and_sleep(void)
}
TEST_CASE_MULTIPLE_STAGES("enter deep sleep after abort", "[deepsleep][reset=abort,SW_CPU_RESET,DEEPSLEEP_RESET]",
do_abort,
check_abort_reset_and_sleep,
check_sleep_reset);
do_abort,
check_abort_reset_and_sleep,
check_sleep_reset);
#if SOC_RTC_FAST_MEM_SUPPORTED
static RTC_DATA_ATTR uint32_t s_wake_stub_var;
@ -319,11 +315,10 @@ static void check_wake_stub(void)
}
TEST_CASE_MULTIPLE_STAGES("can set sleep wake stub", "[deepsleep][reset=DEEPSLEEP_RESET]",
prepare_wake_stub,
check_wake_stub);
prepare_wake_stub,
check_wake_stub);
#endif // SOC_RTC_FAST_MEM_SUPPORTED
#if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
/* Version of prepare_wake_stub() that sets up the deep sleep call while running
@ -349,7 +344,7 @@ static void prepare_wake_stub_from_rtc(void)
a memory capability (as it's an implementation detail). So to test this we need to allocate
the stack statically.
*/
#define STACK_SIZE 1500
#define STACK_SIZE 1500
#if CONFIG_IDF_TARGET_ESP32S3
uint8_t *sleep_stack = (uint8_t *)heap_caps_malloc(STACK_SIZE, MALLOC_CAP_RTCRAM);
TEST_ASSERT((uint32_t)sleep_stack >= SOC_RTC_DRAM_LOW && (uint32_t)sleep_stack < SOC_RTC_DRAM_HIGH);
@ -366,25 +361,25 @@ static void prepare_wake_stub_from_rtc(void)
/* to make things extra sure, start a periodic timer to write to RTC FAST RAM at high frequency */
const esp_timer_create_args_t timer_args = {
.callback = increment_rtc_memory_cb,
.arg = NULL,
.dispatch_method = ESP_TIMER_TASK,
.name = "Write RTC MEM"
.callback = increment_rtc_memory_cb,
.arg = NULL,
.dispatch_method = ESP_TIMER_TASK,
.name = "Write RTC MEM"
};
esp_timer_handle_t timer;
ESP_ERROR_CHECK( esp_timer_create(&timer_args, &timer) );
ESP_ERROR_CHECK( esp_timer_start_periodic(timer, 200) );
ESP_ERROR_CHECK(esp_timer_create(&timer_args, &timer));
ESP_ERROR_CHECK(esp_timer_start_periodic(timer, 200));
printf("Creating test task with stack %p\n", sleep_stack);
TEST_ASSERT_NOT_NULL(xTaskCreateStatic( (void *)prepare_wake_stub, "sleep", STACK_SIZE, NULL,
UNITY_FREERTOS_PRIORITY, sleep_stack, &sleep_task));
TEST_ASSERT_NOT_NULL(xTaskCreateStatic((void *)prepare_wake_stub, "sleep", STACK_SIZE, NULL,
UNITY_FREERTOS_PRIORITY, sleep_stack, &sleep_task));
vTaskDelay(1000 / portTICK_PERIOD_MS);
TEST_FAIL_MESSAGE("Should be asleep by now");
}
TEST_CASE_MULTIPLE_STAGES("can set sleep wake stub from stack in RTC RAM", "[deepsleep][reset=DEEPSLEEP_RESET]",
prepare_wake_stub_from_rtc,
check_wake_stub);
prepare_wake_stub_from_rtc,
check_wake_stub);
#endif // CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
@ -395,7 +390,7 @@ __attribute__((unused)) static float get_time_ms(void)
gettimeofday(&tv_stop, NULL);
float dt = (tv_stop.tv_sec - tv_start.tv_sec) * 1e3f +
(tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
(tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
return fabs(dt);
}
@ -520,7 +515,7 @@ static void trigger_deepsleep(void)
esp_set_time_from_rtc();
// Delay for time error accumulation.
vTaskDelay(10000/portTICK_PERIOD_MS);
vTaskDelay(10000 / portTICK_PERIOD_MS);
// Save start time. Deep sleep.
gettimeofday(&start, NULL);

2
components/esp_system/test_apps/esp_system_unity_tests/main/test_stack_check.c
View File

@ -11,7 +11,7 @@ static void recur_and_smash(void)
{
static int cnt;
volatile uint8_t buf[50];
volatile int num = sizeof(buf)+10;
volatile int num = sizeof(buf) + 10;
if (cnt++ < 1) {
recur_and_smash();

2
components/esp_system/test_apps/esp_system_unity_tests/main/test_system_time.c
View File

@ -15,7 +15,7 @@ TEST_CASE("Test effect of rtc clk calibration compensation on system time", "[es
int64_t t1 = esp_system_get_time();
// Modify calibration value
esp_clk_slowclk_cal_set(prev_cal/2);
esp_clk_slowclk_cal_set(prev_cal / 2);
// Internally, the origin point of rtc clk has been adjusted
// so that t2 > t1 remains true

3
components/esp_system/test_eh_frame_parser/esp_private/panic_internal.h
View File

@ -13,8 +13,9 @@
static inline void panic_print_str(const char* str)
{
/* Ignore "Backtrace:" string. */
if (strcmp(str, "Backtrace:") != 0)
if (strcmp(str, "Backtrace:") != 0) {
printf("%s", str);
}
}
static inline void panic_print_hex(const uint32_t value)

48
components/esp_system/test_eh_frame_parser/main.c
View File

@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -181,7 +181,8 @@ static uint32_t iteration = 1;
* @brief Override the default function called when a backtrace step is
* generated.
*/
void esp_eh_frame_generated_step(uint32_t pc, uint32_t sp) {
void esp_eh_frame_generated_step(uint32_t pc, uint32_t sp)
{
/* The first PCs in the backtrace are calls to `browse_list()` + 2.
* This is due to the fact that the list contains all the numbers
* between NUMBER_TO_TEST to 0 included. Moreover, another call
@ -198,19 +199,19 @@ void esp_eh_frame_generated_step(uint32_t pc, uint32_t sp) {
* browse_list (NUMBER_TO_TEST + 2 iterations), is_even
* (NUMBER_TO_TEST/2 calls) and is_odd (NUMBER_TO_TEST/2 calls) calls.
*/
if (iteration >= NUMBER_OF_ITERATION)
if (iteration >= NUMBER_OF_ITERATION) {
return;
else if (iteration % 2 == 0)
} else if (iteration % 2 == 0) {
assert(is_pc_in_function(pc, "is_odd"));
else
} else {
assert(is_pc_in_function(pc, "is_even"));
}
}
/* Number of times this function has been entered. */
iteration++;
}
/**
* @brief Handler called when SIGSEV signal is sent to the program.
*
@ -219,7 +220,8 @@ void esp_eh_frame_generated_step(uint32_t pc, uint32_t sp) {
* @param ucontext Context of the program when the error occurred. This
* is used to retrieve the CPU registers value.
*/
void signal_handler(int signal, siginfo_t *info, void *ucontext) {
void signal_handler(int signal, siginfo_t *info, void *ucontext)
{
/* Setup the execution frame as expected by the eh_frame_parser.
* Indeed, the registers index defined in ucontext.h are NOT the same
* the registers index DWARF is expecting. */
@ -250,7 +252,7 @@ void signal_handler(int signal, siginfo_t *info, void *ucontext) {
printf("\e[32m\e[1mAll tests passed \e[0m\r\n");
} else {
printf("\e[31m\e[1mWrong length of backtrace (%d iteration, expected %d) \e[0m\r\n",
iteration, NUMBER_OF_ITERATION);
iteration, NUMBER_OF_ITERATION);
exit(1);
}
@ -265,7 +267,8 @@ void signal_handler(int signal, siginfo_t *info, void *ucontext) {
*
* @param l List to browse.
*/
void browse_list(struct list_t* l) {
void browse_list(struct list_t* l)
{
browse_list(l->next);
}
@ -274,7 +277,8 @@ void browse_list(struct list_t* l) {
*
* @param n Number to add in the list.
*/
void add_number_to_list(uint32_t n) {
void add_number_to_list(uint32_t n)
{
struct list_t* l = malloc(sizeof(struct list_t));
l->value = n;
l->next = head.next;
@ -289,7 +293,8 @@ void add_number_to_list(uint32_t n) {
*
* @return true if even, false else.
*/
bool is_even(uint32_t n) {
bool is_even(uint32_t n)
{
add_number_to_list(n);
if (n == 0) {
browse_list(head.next);
@ -306,7 +311,8 @@ bool is_even(uint32_t n) {
*
* @return true if odd, false else.
*/
bool is_odd(uint32_t n) {
bool is_odd(uint32_t n)
{
add_number_to_list(n);
if (n == 0) {
browse_list(head.next);
@ -331,8 +337,9 @@ static inline void initialize_functions_info(void)
* Thus, we will look for these instructions. */
uint8_t* instructions = (uint8_t*) funs[i].start;
while ((instructions[0] != 0xc9 || instructions[1] != 0xc3) &&
(instructions[0] != 0x5d || instructions[1] != 0xc3) )
(instructions[0] != 0x5d || instructions[1] != 0xc3)) {
instructions++;
}
instructions += 1;
funs[i].end = (uintptr_t) instructions;
}
@ -341,7 +348,8 @@ static inline void initialize_functions_info(void)
/**
* Test the eh_frame_parser for backtracing
*/
void test2(void) {
void test2(void)
{
/* Initialize the structure holding information about the signal to override. */
struct sigaction sig = {
.sa_mask = 0,
@ -367,7 +375,8 @@ void test2(void) {
* Important: the stack must still be alive when analyzing it, thus it must be done
* within the nested functions.
*/
int analyse_callstack() {
int analyse_callstack()
{
unw_context_t ucp = { 0 };
unw_cursor_t cur = { 0 };
unw_word_t pc = 0;
@ -393,15 +402,18 @@ int analyse_callstack() {
return UNW_ESUCCESS;
}
int __attribute__((noinline)) inner_function2(void) {
int __attribute__((noinline)) inner_function2(void)
{
return analyse_callstack();
}
int __attribute__((noinline)) inner_function1(void) {
int __attribute__((noinline)) inner_function1(void)
{
return inner_function2();
}
void __attribute__((noinline)) test1() {
void __attribute__((noinline)) test1()
{
(void) inner_function1();
}

2
components/esp_system/ubsan.c
View File

@ -34,7 +34,6 @@
#include "esp_rom_sys.h"
#include "esp_cpu.h"
struct source_location {
const char *file_name;
uint32_t line;
@ -110,7 +109,6 @@ struct invalid_builtin_data {
unsigned char kind;
};
static void __ubsan_default_handler(struct source_location *loc, const char *func) __attribute__((noreturn));
/*

1
tools/ci/astyle-rules.yml
View File

@ -68,7 +68,6 @@ components_not_formatted_temporary:
- "/components/esp_phy/"
- "/components/esp_pm/"
- "/components/esp_rom/"
- "/components/esp_system/"
- "/components/esp_timer/"
- "/components/esp_wifi/"
- "/components/esp-tls/"